svn commit: r206119 - in user/jmallett/octeon/sys/mips: include mips
Juli Mallett
jmallett at FreeBSD.org
Sat Apr 3 03:31:15 UTC 2010
Author: jmallett
Date: Sat Apr 3 03:31:14 2010
New Revision: 206119
URL: http://svn.freebsd.org/changeset/base/206119
Log:
Checkpoint a WIP...
o) Move to 8K pages from 4K pages and use a single PTE to populate TLBLo0 and
TLBLo1, with the PFN adjusted appropriately in TLBLo1.
o) Keep the same kstack and uarea size (8K) and move to using a single page for
both.
Note that we can remove the awkward (and broken) allocation of 3 pages to
get a kstack and the subsequent modification to ensure that the kstack would
not have to share its TLB entry and would fit into a single TLB entry.
This means we can also remove mdthread's realstack.
o) Likewise remove similar balancing acts in fpage allocation.
o) Don't use pmap_update_page in pmap_kenter, use pmap_invalidate_page. We do
a lot of pmap_kenter calls in a row at early startup in particular and it
doesn't make sense to keep thrashing the TLB.
Modified:
user/jmallett/octeon/sys/mips/include/param.h
user/jmallett/octeon/sys/mips/include/proc.h
user/jmallett/octeon/sys/mips/include/pte.h
user/jmallett/octeon/sys/mips/mips/exception.S
user/jmallett/octeon/sys/mips/mips/genassym.c
user/jmallett/octeon/sys/mips/mips/machdep.c
user/jmallett/octeon/sys/mips/mips/pmap.c
user/jmallett/octeon/sys/mips/mips/swtch.S
user/jmallett/octeon/sys/mips/mips/tlb.S
user/jmallett/octeon/sys/mips/mips/trap.c
user/jmallett/octeon/sys/mips/mips/vm_machdep.c
Modified: user/jmallett/octeon/sys/mips/include/param.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/param.h Sat Apr 3 00:47:48 2010 (r206118)
+++ user/jmallett/octeon/sys/mips/include/param.h Sat Apr 3 03:31:14 2010 (r206119)
@@ -102,26 +102,20 @@
#define CACHE_LINE_SHIFT 6
#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
-#define PAGE_SHIFT 12 /* LOG2(PAGE_SIZE) */
+#define PAGE_SHIFT 13 /* LOG2(PAGE_SIZE) */
#define PAGE_SIZE (1<<PAGE_SHIFT) /* bytes/page */
#define PAGE_MASK (PAGE_SIZE-1)
#define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t)))
#define MAXPAGESIZES 1 /* maximum number of supported page sizes */
-#define BLKDEV_IOSIZE 2048 /* xxx: Why is this 1/2 page? */
+#define BLKDEV_IOSIZE 2048 /* xxx: Why is this 1/4 page? */
#define MAXDUMPPGS 1 /* xxx: why is this only one? */
-/*
- * The kernel stack needs to be aligned on a (PAGE_SIZE * 2) boundary.
- *
- * Although we allocate 3 pages for the kernel stack we end up using
- * only the 2 pages that are aligned on a (PAGE_SIZE * 2) boundary.
- */
-#define KSTACK_PAGES 3 /* kernel stack*/
+#define KSTACK_PAGES 1 /* kernel stack*/
#define KSTACK_GUARD_PAGES 1 /* pages of kstack guard; 0 disables */
-#define UPAGES 2
+#define UPAGES 1
/* pages ("clicks") (4096 bytes) to disk blocks */
#define ctod(x) ((x) << (PAGE_SHIFT - DEV_BSHIFT))
Modified: user/jmallett/octeon/sys/mips/include/proc.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/proc.h Sat Apr 3 00:47:48 2010 (r206118)
+++ user/jmallett/octeon/sys/mips/include/proc.h Sat Apr 3 03:31:14 2010 (r206119)
@@ -44,7 +44,7 @@
*/
struct mdthread {
int md_flags; /* machine-dependent flags */
- int md_upte[KSTACK_PAGES - 1]; /* ptes for mapping u pcb */
+ int md_upte[KSTACK_PAGES]; /* ptes for mapping u pcb */
int md_ss_addr; /* single step address for ptrace */
int md_ss_instr; /* single step instruction for ptrace */
register_t md_saved_intr;
@@ -53,7 +53,6 @@ struct mdthread {
int md_pc_ctrl; /* performance counter control */
int md_pc_count; /* performance counter */
int md_pc_spill; /* performance counter spill */
- vm_offset_t md_realstack;
void *md_tls;
};
Modified: user/jmallett/octeon/sys/mips/include/pte.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/pte.h Sat Apr 3 00:47:48 2010 (r206118)
+++ user/jmallett/octeon/sys/mips/include/pte.h Sat Apr 3 03:31:14 2010 (r206119)
@@ -102,7 +102,7 @@ typedef pt_entry_t *pd_entry_t;
/*#define PTE_NV 0x00000000 Not Used */
#define PTE_M 0x00000004
#define PTE_RW PTE_M
-#define PTE_ODDPG 0x00001000
+#define PTE_ODDPG 0x00000040
/*#define PG_ATTR 0x0000003f Not Used */
#define PTE_UNCACHED 0x00000010
#ifdef CPU_SB1
@@ -119,10 +119,11 @@ typedef pt_entry_t *pd_entry_t;
#define PTE_HVPN 0xffffe000 /* Hardware page no mask */
#define PTE_ASID 0x000000ff /* Address space ID */
+#define TLB_PAGE_SHIFT (PAGE_SHIFT - 1)
#define PTE_SHIFT 6
#define pfn_is_ext(x) ((x) & 0x3c000000)
-#define vad_to_pfn(x) (((vm_offset_t)(x) >> PTE_SHIFT) & PTE_FRAME)
-#define pfn_to_vad(x) (((x) & PTE_FRAME) << PTE_SHIFT)
+#define vad_to_pfn(x) ((((vm_offset_t)(x) >> TLB_PAGE_SHIFT) << PTE_SHIFT) & PTE_FRAME)
+#define pfn_to_vad(x) ((((x) & PTE_FRAME) >> PTE_SHIFT) << TLB_PAGE_SHIFT)
/* User virtual to pte offset in page table */
#define vad_to_pte_offset(adr) (((adr) >> PAGE_SHIFT) & (NPTEPG -1))
Modified: user/jmallett/octeon/sys/mips/mips/exception.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/exception.S Sat Apr 3 00:47:48 2010 (r206118)
+++ user/jmallett/octeon/sys/mips/mips/exception.S Sat Apr 3 03:31:14 2010 (r206119)
@@ -148,11 +148,10 @@ MipsDoTLBMiss:
andi k0, k0, 0xff8 #0c: k0=page tab offset
PTR_ADDU k1, k1, k0 #0d: k1=pte address
lw k0, 0(k1) #0e: k0=lo0 pte
- lw k1, 4(k1) #0f: k1=lo1 pte
CLEAR_PTE_WIRED(k0)
MTC0 k0, COP_0_TLB_LO0 #12: lo0 is loaded
- CLEAR_PTE_WIRED(k1)
- MTC0 k1, COP_0_TLB_LO1 #15: lo1 is loaded
+ addu k0, PTE_ODDPG
+ MTC0 k0, COP_0_TLB_LO1 #15: lo1 is loaded
HAZARD_DELAY
tlbwr #1a: write to tlb
HAZARD_DELAY
@@ -857,33 +856,12 @@ NLEAF(MipsTLBInvalidException)
beqz k0, 3f
nop
- /* Is this the odd or even entry? */
- andi k0, k1, 4
- bnez k0, odd_page
- nop
-
-even_page:
lw k0, 0(k1)
CLEAR_PTE_WIRED(k0)
MTC0 k0, COP_0_TLB_LO0
-
- lw k0, 4(k1)
- CLEAR_PTE_WIRED(k0)
- MTC0 k0, COP_0_TLB_LO1
-
- b tlb_insert_entry
- nop
-
-odd_page:
- lw k0, 0(k1)
- CLEAR_PTE_WIRED(k0)
+ addu k0, PTE_ODDPG
MTC0 k0, COP_0_TLB_LO1
- lw k0, -4(k1)
- CLEAR_PTE_WIRED(k0)
- MTC0 k0, COP_0_TLB_LO0
-
-tlb_insert_entry:
tlbp
HAZARD_DELAY
mfc0 k0, COP_0_TLB_INDEX
@@ -913,7 +891,7 @@ tlb_insert_random:
*/
GET_CPU_PCPU(k1)
PTR_L k0, PC_CURTHREAD(k1)
- PTR_L k0, TD_REALKSTACK(k0)
+ PTR_L k0, TD_KSTACK(k0)
sltu k0, k0, sp
bnez k0, _C_LABEL(MipsKernGenException)
nop
@@ -929,7 +907,7 @@ tlb_insert_random:
sll k1, k1, PAGE_SHIFT + 1
PTR_LA k0, _C_LABEL(pcpu_space)
- PTR_ADDU k0, (PAGE_SIZE * 2)
+ PTR_ADDU k0, PAGE_SIZE * 2
PTR_ADDU k0, k0, k1
/*
@@ -960,7 +938,7 @@ tlb_insert_random:
*/
GET_CPU_PCPU(k1)
PTR_L k0, PC_CURTHREAD(k1)
- PTR_S zero, TD_REALKSTACK(k0)
+ PTR_S zero, TD_KSTACK(k0)
move a1, a0
PANIC("kernel stack overflow - trapframe at %p")
@@ -1018,12 +996,10 @@ NLEAF(MipsTLBMissException)
andi k0, k0, 0xff8 # k0=page tab offset
PTR_ADDU k1, k1, k0 # k1=pte address
lw k0, 0(k1) # k0=lo0 pte
- lw k1, 4(k1) # k1=lo1 pte
CLEAR_PTE_WIRED(k0)
MTC0 k0, COP_0_TLB_LO0 # lo0 is loaded
- CLEAR_PTE_WIRED(k1)
- MTC0 k1, COP_0_TLB_LO1 # lo1 is loaded
-
+ addu k0, PTE_ODDPG
+ MTC0 k0, COP_0_TLB_LO1 # lo1 is loaded
HAZARD_DELAY
tlbwr # write to tlb
HAZARD_DELAY
Modified: user/jmallett/octeon/sys/mips/mips/genassym.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/genassym.c Sat Apr 3 00:47:48 2010 (r206118)
+++ user/jmallett/octeon/sys/mips/mips/genassym.c Sat Apr 3 03:31:14 2010 (r206119)
@@ -65,7 +65,7 @@ __FBSDID("$FreeBSD$");
ASSYM(TD_PCB, offsetof(struct thread, td_pcb));
ASSYM(TD_UPTE, offsetof(struct thread, td_md.md_upte));
-ASSYM(TD_REALKSTACK, offsetof(struct thread, td_md.md_realstack));
+ASSYM(TD_KSTACK, offsetof(struct thread, td_kstack));
ASSYM(TD_FLAGS, offsetof(struct thread, td_flags));
ASSYM(TD_LOCK, offsetof(struct thread, td_lock));
ASSYM(TD_FRAME, offsetof(struct thread, td_frame));
Modified: user/jmallett/octeon/sys/mips/mips/machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/machdep.c Sat Apr 3 00:47:48 2010 (r206118)
+++ user/jmallett/octeon/sys/mips/mips/machdep.c Sat Apr 3 03:31:14 2010 (r206119)
@@ -302,14 +302,13 @@ mips_proc0_init(void)
(long)kstack0));
thread0.td_kstack = kstack0;
thread0.td_kstack_pages = KSTACK_PAGES;
- thread0.td_md.md_realstack = roundup2(thread0.td_kstack, PAGE_SIZE * 2);
/*
* Do not use cpu_thread_alloc to initialize these fields
* thread0 is the only thread that has kstack located in KSEG0
* while cpu_thread_alloc handles kstack allocated in KSEG2.
*/
- thread0.td_pcb = (struct pcb *)(thread0.td_md.md_realstack +
- (thread0.td_kstack_pages - 1) * PAGE_SIZE) - 1;
+ thread0.td_pcb = (struct pcb *)(thread0.td_kstack +
+ thread0.td_kstack_pages * PAGE_SIZE) - 1;
thread0.td_frame = &thread0.td_pcb->pcb_regs;
/* Steal memory for the dynamic per-cpu area. */
Modified: user/jmallett/octeon/sys/mips/mips/pmap.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/pmap.c Sat Apr 3 00:47:48 2010 (r206118)
+++ user/jmallett/octeon/sys/mips/mips/pmap.c Sat Apr 3 03:31:14 2010 (r206119)
@@ -729,7 +729,13 @@ pmap_kenter(vm_offset_t va, vm_paddr_t p
opte = *pte;
*pte = npte;
- pmap_update_page(kernel_pmap, va, npte);
+ /*
+ * The original code did an update_page() here, but
+ * we often do a lot of pmap_kenter() calls and then
+ * start using the addresses later, at which point
+ * the TLB has overflown many times.
+ */
+ pmap_invalidate_page(kernel_pmap, va);
}
/*
@@ -851,36 +857,11 @@ pmap_init_fpage()
int i, j;
struct sysmaps *sysmaps;
- /*
- * We allocate a total of (FPAGES*MAXCPU + FPAGES_SHARED + 1) pages
- * at first. FPAGES & FPAGES_SHARED should be EVEN Then we'll adjust
- * 'kva' to be even-page aligned so that the fpage area can be wired
- * in the TLB with a single TLB entry.
- */
kva = kmem_alloc_nofault(kernel_map,
- (FPAGES * MAXCPU + 1 + FPAGES_SHARED) * PAGE_SIZE);
+ (FPAGES * MAXCPU + FPAGES_SHARED) * PAGE_SIZE);
if ((void *)kva == NULL)
panic("pmap_init_fpage: fpage allocation failed");
- /*
- * Make up start at an even page number so we can wire down the
- * fpage area in the tlb with a single tlb entry.
- */
- if ((((vm_offset_t)kva) >> PAGE_SHIFT) & 1) {
- /*
- * 'kva' is not even-page aligned. Adjust it and free the
- * first page which is unused.
- */
- kmem_free(kernel_map, (vm_offset_t)kva, PAGE_SIZE);
- kva = ((vm_offset_t)kva) + PAGE_SIZE;
- } else {
- /*
- * 'kva' is even page aligned. We don't need the last page,
- * free it.
- */
- kmem_free(kernel_map, ((vm_offset_t)kva) + FSPACE, PAGE_SIZE);
- }
-
for (i = 0; i < MAXCPU; i++) {
sysmaps = &sysmaps_pcpu[i];
mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
Modified: user/jmallett/octeon/sys/mips/mips/swtch.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/swtch.S Sat Apr 3 00:47:48 2010 (r206118)
+++ user/jmallett/octeon/sys/mips/mips/swtch.S Sat Apr 3 03:31:14 2010 (r206119)
@@ -293,36 +293,28 @@ blocked_loop:
PTR_S a1, PC_CURTHREAD(a3)
PTR_L a2, TD_PCB(a1)
PTR_S a2, PC_CURPCB(a3)
- PTR_L v0, TD_REALKSTACK(a1)
+ PTR_L v0, TD_KSTACK(a1)
li s0, (MIPS_KSEG2_START+VM_KERNEL_ALLOC_OFFSET) # If Uarea addr is below kseg2,
bltu v0, s0, sw2 # no need to insert in TLB.
- lw a1, TD_UPTE+0(s7) # t0 = first u. pte
- lw a2, TD_UPTE+4(s7) # t1 = 2nd u. pte
- and s0, v0, PTE_ODDPG
- beq s0, zero, entry0
- nop
-
- PANIC_KSEG0("USPACE sat on odd page boundary", t1)
-
+ lw a1, TD_UPTE(s7) # t0 = u. pte
/*
* Wiredown the USPACE of newproc in TLB entry#0. Check whether target
* USPACE is already in another place of TLB before that, and if so
* invalidate that TLB entry.
- * NOTE: This is hard coded to UPAGES == 2.
+ * NOTE: This is hard coded to UPAGES == 1.
* Also, there should be no TLB faults at this point.
*/
-entry0:
- mtc0 v0, COP_0_TLB_HI # VPN = va
+ MTC0 v0, COP_0_TLB_HI # VPN = va
HAZARD_DELAY
tlbp # probe VPN
HAZARD_DELAY
mfc0 s0, COP_0_TLB_INDEX
nop
-pgm:
- REG_LI t1, MIPS_KSEG0_START # invalidate tlb entry
+
+ li t1, MIPS_KSEG0_START # invalidate tlb entry
bltz s0, entry0set
nop
- sll s0, PAGE_SHIFT + 1
+ sll s0, PAGE_SHIFT
addu t1, s0
mtc0 t1, COP_0_TLB_HI
mtc0 zero, COP_0_TLB_LO0
@@ -331,13 +323,13 @@ pgm:
tlbwi
HAZARD_DELAY
mtc0 v0, COP_0_TLB_HI # set VPN again
+
entry0set:
/* SMP!! - Works only for unshared TLB case - i.e. no v-cpus */
mtc0 zero, COP_0_TLB_INDEX # TLB entry #0
-# or a1, PG_G
- mtc0 a1, COP_0_TLB_LO0 # upte[0]
-# or a2, PG_G
- mtc0 a2, COP_0_TLB_LO1 # upte[1]
+ mtc0 a1, COP_0_TLB_LO0 # upte
+ addu a1, PTE_ODDPG
+ mtc0 a1, COP_0_TLB_LO1 # upte + odd
HAZARD_DELAY
tlbwi # set TLB entry #0
HAZARD_DELAY
Modified: user/jmallett/octeon/sys/mips/mips/tlb.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/tlb.S Sat Apr 3 00:47:48 2010 (r206118)
+++ user/jmallett/octeon/sys/mips/mips/tlb.S Sat Apr 3 03:31:14 2010 (r206119)
@@ -152,10 +152,10 @@ LEAF(Mips_TLBFlush)
#
# Load invalid entry, each TLB entry should have it's own bogus
# address calculated by following expression:
- # MIPS_KSEG0_START + 2 * i * PAGE_SIZE;
+ # MIPS_KSEG0_START + i * PAGE_SIZE;
# One bogus value for every TLB entry might cause MCHECK exception
#
- sll t3, t1, PAGE_SHIFT + 1
+ sll t3, t1, PAGE_SHIFT
li v0, MIPS_KSEG0_START # invalid address
addu v0, t3
/*
@@ -166,7 +166,7 @@ LEAF(Mips_TLBFlush)
ITLBNOPFIX
MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid
addu t1, t1, 1 # Increment index.
- addu v0, v0, 8 * 1024
+ addu v0, v0, PAGE_SIZE
MIPS_CPU_NOP_DELAY
tlbwi # Write the TLB entry.
MIPS_CPU_NOP_DELAY
@@ -212,9 +212,9 @@ LEAF(Mips_TLBFlushAddr)
nop
# Load invalid entry, each TLB entry should have it's own bogus
# address calculated by following expression:
- # MIPS_KSEG0_START + 2 * i * PAGE_SIZE;
+ # MIPS_KSEG0_START + i * PAGE_SIZE;
# One bogus value for every TLB entry might cause MCHECK exception
- sll v0, PAGE_SHIFT + 1
+ sll v0, PAGE_SHIFT
addu t1, v0
MTC0 t1, COP_0_TLB_HI # Mark entry high as invalid
@@ -250,26 +250,24 @@ LEAF(Mips_TLBUpdate)
mfc0 v1, COP_0_STATUS_REG # Save the status register.
mtc0 zero, COP_0_STATUS_REG # Disable interrupts
ITLBNOPFIX
- and t1, a0, 0x1000 # t1 = Even/Odd flag
li v0, (PTE_HVPN | PTE_ASID)
and a0, a0, v0
MFC0 t0, COP_0_TLB_HI # Save current PID
MTC0 a0, COP_0_TLB_HI # Init high reg
- and a2, a1, PTE_G # Copy global bit
MIPS_CPU_NOP_DELAY
tlbp # Probe for the entry.
CLEAR_PTE_WIRED(a1)
nop
+
mfc0 v0, COP_0_TLB_INDEX # See what we got
- bne t1, zero, 2f # Decide even odd
-# EVEN
- nop
bltz v0, 1f # index < 0 => !found
MIPS_CPU_NOP_DELAY
tlbr # update, read entry first
MIPS_CPU_NOP_DELAY
MTC0 a1, COP_0_TLB_LO0 # init low reg0.
+ addu a1, PTE_ODDPG
+ MTC0 a1, COP_0_TLB_LO1 # init low reg1.
MIPS_CPU_NOP_DELAY
tlbwi # update slot found
b 4f
@@ -278,34 +276,11 @@ LEAF(Mips_TLBUpdate)
mtc0 zero, COP_0_TLB_PG_MASK # init mask.
MTC0 a0, COP_0_TLB_HI # init high reg.
MTC0 a1, COP_0_TLB_LO0 # init low reg0.
- MTC0 a2, COP_0_TLB_LO1 # init low reg1.
- MIPS_CPU_NOP_DELAY
- tlbwr # enter into a random slot
- MIPS_CPU_NOP_DELAY
- b 4f
- nop
-# ODD
-2:
- nop
- bltz v0, 3f # index < 0 => !found
- MIPS_CPU_NOP_DELAY
-
- tlbr # read the entry first
- MIPS_CPU_NOP_DELAY
- MTC0 a1, COP_0_TLB_LO1 # init low reg1.
- MIPS_CPU_NOP_DELAY
- tlbwi # update slot found
- MIPS_CPU_NOP_DELAY
- b 4f
- nop
-3:
- mtc0 zero, COP_0_TLB_PG_MASK # init mask.
- MTC0 a0, COP_0_TLB_HI # init high reg.
- MTC0 a2, COP_0_TLB_LO0 # init low reg0.
+ addu a1, PTE_ODDPG
MTC0 a1, COP_0_TLB_LO1 # init low reg1.
MIPS_CPU_NOP_DELAY
tlbwr # enter into a random slot
-
+ MIPS_CPU_NOP_DELAY
4: # Make shure pipeline
MIPS_CPU_NOP_DELAY
MTC0 t0, COP_0_TLB_HI # restore PID
@@ -373,10 +348,10 @@ LEAF(mips_TBIAP)
#
# Load invalid entry, each TLB entry should have it's own bogus
# address calculated by following expression:
- # MIPS_KSEG0_START + 2 * i * PAGE_SIZE;
+ # MIPS_KSEG0_START + i * PAGE_SIZE;
# One bogus value for every TLB entry might cause MCHECK exception
#
- sll t3, t1, PAGE_SHIFT + 1
+ sll t3, t1, PAGE_SHIFT
li v0, MIPS_KSEG0_START # invalid address
addu v0, t3
@@ -401,7 +376,7 @@ LEAF(mips_TBIAP)
tlbwi # invalidate the TLB entry
2:
addu t1, t1, 1
- addu v0, 1 << (PAGE_SHIFT + 1)
+ addu v0, PAGE_SIZE
bne t1, t2, 1b
nop
Modified: user/jmallett/octeon/sys/mips/mips/trap.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/trap.c Sat Apr 3 00:47:48 2010 (r206118)
+++ user/jmallett/octeon/sys/mips/mips/trap.c Sat Apr 3 03:31:14 2010 (r206119)
@@ -96,6 +96,7 @@ __FBSDID("$FreeBSD$");
#include <sys/syslog.h>
+#define TRAP_DEBUG
#ifdef TRAP_DEBUG
int trap_debug = 1;
#endif
Modified: user/jmallett/octeon/sys/mips/mips/vm_machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/vm_machdep.c Sat Apr 3 00:47:48 2010 (r206118)
+++ user/jmallett/octeon/sys/mips/mips/vm_machdep.c Sat Apr 3 03:31:14 2010 (r206119)
@@ -215,16 +215,6 @@ cpu_thread_swapin(struct thread *td)
{
pt_entry_t *pte;
int i;
- vm_offset_t unused_kstack_page;
-
- /*
- * Unmap the unused kstack page.
- */
- unused_kstack_page = td->td_kstack;
- if (td->td_md.md_realstack == td->td_kstack)
- unused_kstack_page += (KSTACK_PAGES - 1) * PAGE_SIZE;
-
- pmap_kremove(unused_kstack_page);
/*
* The kstack may be at a different physical address now.
@@ -232,11 +222,11 @@ cpu_thread_swapin(struct thread *td)
* part of the thread struct so cpu_switch() can quickly map in
* the pcb struct and kernel stack.
*/
- if (!(pte = pmap_segmap(kernel_pmap, td->td_md.md_realstack)))
+ if (!(pte = pmap_segmap(kernel_pmap, td->td_kstack)))
panic("cpu_thread_swapin: invalid segmap");
- pte += ((vm_offset_t)td->td_md.md_realstack >> PAGE_SHIFT) & (NPTEPG - 1);
+ pte += ((vm_offset_t)td->td_kstack >> PAGE_SHIFT) & (NPTEPG - 1);
- for (i = 0; i < KSTACK_PAGES - 1; i++) {
+ for (i = 0; i < KSTACK_PAGES; i++) {
td->td_md.md_upte[i] = *pte & ~(PTE_RO|PTE_WIRED);
pte++;
}
@@ -250,29 +240,18 @@ cpu_thread_swapout(struct thread *td)
void
cpu_thread_alloc(struct thread *td)
{
- vm_offset_t unused_kstack_page;
pt_entry_t *pte;
int i;
- if (td->td_kstack & (1 << PAGE_SHIFT)) {
- td->td_md.md_realstack = td->td_kstack + PAGE_SIZE;
- unused_kstack_page = td->td_kstack;
- } else {
- td->td_md.md_realstack = td->td_kstack;
- unused_kstack_page = td->td_kstack +
- (KSTACK_PAGES - 1) * PAGE_SIZE;
- }
- pmap_kremove(unused_kstack_page);
-
- td->td_pcb = (struct pcb *)(td->td_md.md_realstack +
- (td->td_kstack_pages - 1) * PAGE_SIZE) - 1;
+ td->td_pcb = (struct pcb *)(td->td_kstack +
+ td->td_kstack_pages * PAGE_SIZE) - 1;
td->td_frame = &td->td_pcb->pcb_regs;
- if (!(pte = pmap_segmap(kernel_pmap, td->td_md.md_realstack)))
+ if (!(pte = pmap_segmap(kernel_pmap, td->td_kstack)))
panic("cpu_thread_alloc: invalid segmap");
- pte += ((vm_offset_t)td->td_md.md_realstack >> PAGE_SHIFT) & (NPTEPG - 1);
+ pte += ((vm_offset_t)td->td_kstack >> PAGE_SHIFT) & (NPTEPG - 1);
- for (i = 0; i < KSTACK_PAGES - 1; i++) {
+ for (i = 0; i < KSTACK_PAGES; i++) {
td->td_md.md_upte[i] = *pte & ~(PTE_RO|PTE_WIRED);
pte++;
}
More information about the svn-src-user
mailing list