svn commit: r185821 - user/kmacy/head_arpv2/sys/dev/jme
Kip Macy
kmacy at FreeBSD.org
Tue Dec 9 18:18:56 PST 2008
Author: kmacy
Date: Wed Dec 10 02:18:55 2008
New Revision: 185821
URL: http://svn.freebsd.org/changeset/base/185821
Log:
revert to HEAD version
Modified:
user/kmacy/head_arpv2/sys/dev/jme/if_jme.c
user/kmacy/head_arpv2/sys/dev/jme/if_jmereg.h
user/kmacy/head_arpv2/sys/dev/jme/if_jmevar.h
Modified: user/kmacy/head_arpv2/sys/dev/jme/if_jme.c
==============================================================================
--- user/kmacy/head_arpv2/sys/dev/jme/if_jme.c Wed Dec 10 02:10:44 2008 (r185820)
+++ user/kmacy/head_arpv2/sys/dev/jme/if_jme.c Wed Dec 10 02:18:55 2008 (r185821)
@@ -150,6 +150,9 @@ static void jme_init_ssb(struct jme_soft
static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *);
static void jme_set_vlan(struct jme_softc *);
static void jme_set_filter(struct jme_softc *);
+static void jme_stats_clear(struct jme_softc *);
+static void jme_stats_save(struct jme_softc *);
+static void jme_stats_update(struct jme_softc *);
static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS);
static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
@@ -651,6 +654,14 @@ jme_attach(device_t dev)
goto fail;
}
+ if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) {
+ if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 &&
+ CHIPMODE_REVFM(sc->jme_chip_rev) == 2)
+ sc->jme_flags |= JME_FLAG_DMA32BIT;
+ sc->jme_flags |= JME_FLAG_TXCLK;
+ sc->jme_flags |= JME_FLAG_HWMIB;
+ }
+
/* Reset the ethernet controller. */
jme_reset(sc);
@@ -880,35 +891,41 @@ jme_detach(device_t dev)
return (0);
}
+#define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \
+ SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
+
static void
jme_sysctl_node(struct jme_softc *sc)
{
+ struct sysctl_ctx_list *ctx;
+ struct sysctl_oid_list *child, *parent;
+ struct sysctl_oid *tree;
+ struct jme_hw_stats *stats;
int error;
- SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev),
- SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO,
- "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to,
- 0, sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout");
-
- SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev),
- SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO,
- "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt,
- 0, sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet");
-
- SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev),
- SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO,
- "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to,
- 0, sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout");
-
- SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev),
- SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO,
- "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt,
- 0, sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet");
-
- SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev),
- SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO,
- "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit,
- 0, sysctl_hw_jme_proc_limit, "I",
+ stats = &sc->jme_stats;
+ ctx = device_get_sysctl_ctx(sc->jme_dev);
+ child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev));
+
+ SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to",
+ CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 0,
+ sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout");
+
+ SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt",
+ CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 0,
+ sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet");
+
+ SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to",
+ CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 0,
+ sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout");
+
+ SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt",
+ CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 0,
+ sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet");
+
+ SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
+ CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 0,
+ sysctl_hw_jme_proc_limit, "I",
"max number of Rx events to process");
/* Pull in device tunables. */
@@ -977,8 +994,43 @@ jme_sysctl_node(struct jme_softc *sc)
sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
}
}
+
+ if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
+ return;
+
+ tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
+ NULL, "JME statistics");
+ parent = SYSCTL_CHILDREN(tree);
+
+ /* Rx statistics. */
+ tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
+ NULL, "Rx MAC statistics");
+ child = SYSCTL_CHILDREN(tree);
+ JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
+ &stats->rx_good_frames, "Good frames");
+ JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
+ &stats->rx_crc_errs, "CRC errors");
+ JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs",
+ &stats->rx_mii_errs, "MII errors");
+ JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
+ &stats->rx_fifo_oflows, "FIFO overflows");
+ JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty",
+ &stats->rx_desc_empty, "Descriptor empty");
+ JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
+ &stats->rx_bad_frames, "Bad frames");
+
+ /* Tx statistics. */
+ tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
+ NULL, "Tx MAC statistics");
+ child = SYSCTL_CHILDREN(tree);
+ JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
+ &stats->tx_good_frames, "Good frames");
+ JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
+ &stats->tx_bad_frames, "Bad frames");
}
+#undef JME_SYSCTL_STAT_ADD32
+
struct jme_dmamap_arg {
bus_addr_t jme_busaddr;
};
@@ -1007,6 +1059,8 @@ jme_dma_alloc(struct jme_softc *sc)
int error, i;
lowaddr = BUS_SPACE_MAXADDR;
+ if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
+ lowaddr = BUS_SPACE_MAXADDR_32BIT;
again:
/* Create parent ring tag. */
@@ -1106,25 +1160,32 @@ again:
}
sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr;
- /* Tx/Rx descriptor queue should reside within 4GB boundary. */
- tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr + JME_TX_RING_SIZE;
- rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr + JME_RX_RING_SIZE;
- if ((JME_ADDR_HI(tx_ring_end) !=
- JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) ||
- (JME_ADDR_HI(rx_ring_end) !=
- JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) {
- device_printf(sc->jme_dev, "4GB boundary crossed, "
- "switching to 32bit DMA address mode.\n");
- jme_dma_free(sc);
- /* Limit DMA address space to 32bit and try again. */
- lowaddr = BUS_SPACE_MAXADDR_32BIT;
- goto again;
+ if (lowaddr != BUS_SPACE_MAXADDR_32BIT) {
+ /* Tx/Rx descriptor queue should reside within 4GB boundary. */
+ tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr +
+ JME_TX_RING_SIZE;
+ rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr +
+ JME_RX_RING_SIZE;
+ if ((JME_ADDR_HI(tx_ring_end) !=
+ JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) ||
+ (JME_ADDR_HI(rx_ring_end) !=
+ JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) {
+ device_printf(sc->jme_dev, "4GB boundary crossed, "
+ "switching to 32bit DMA address mode.\n");
+ jme_dma_free(sc);
+ /* Limit DMA address space to 32bit and try again. */
+ lowaddr = BUS_SPACE_MAXADDR_32BIT;
+ goto again;
+ }
}
+ lowaddr = BUS_SPACE_MAXADDR;
+ if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
+ lowaddr = BUS_SPACE_MAXADDR_32BIT;
/* Create parent buffer tag. */
error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1, 0, /* algnmnt, boundary */
- BUS_SPACE_MAXADDR, /* lowaddr */
+ lowaddr, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
@@ -1445,6 +1506,11 @@ jme_setwol(struct jme_softc *sc)
JME_LOCK_ASSERT(sc);
if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
+ /* Remove Tx MAC/offload clock to save more power. */
+ if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
+ CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
+ ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
+ GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
/* No PME capability, PHY power down. */
jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
MII_BMCR, BMCR_PDOWN);
@@ -1466,7 +1532,11 @@ jme_setwol(struct jme_softc *sc)
CSR_WRITE_4(sc, JME_PMCS, pmcs);
CSR_WRITE_4(sc, JME_GPREG0, gpr);
-
+ /* Remove Tx MAC/offload clock to save more power. */
+ if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
+ CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
+ ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
+ GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
/* Request PME. */
pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
@@ -1941,6 +2011,7 @@ jme_mac_config(struct jme_softc *sc)
{
struct mii_data *mii;
uint32_t ghc, gpreg, rxmac, txmac, txpause;
+ uint32_t txclk;
JME_LOCK_ASSERT(sc);
@@ -1950,6 +2021,7 @@ jme_mac_config(struct jme_softc *sc)
DELAY(10);
CSR_WRITE_4(sc, JME_GHC, 0);
ghc = 0;
+ txclk = 0;
rxmac = CSR_READ_4(sc, JME_RXMAC);
rxmac &= ~RXMAC_FC_ENB;
txmac = CSR_READ_4(sc, JME_TXMAC);
@@ -1982,14 +2054,17 @@ jme_mac_config(struct jme_softc *sc)
switch (IFM_SUBTYPE(mii->mii_media_active)) {
case IFM_10_T:
ghc |= GHC_SPEED_10;
+ txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
break;
case IFM_100_TX:
ghc |= GHC_SPEED_100;
+ txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
break;
case IFM_1000_T:
if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
break;
ghc |= GHC_SPEED_1000;
+ txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000;
if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
break;
@@ -2019,6 +2094,8 @@ jme_mac_config(struct jme_softc *sc)
0x1B, 0x0004);
}
}
+ if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
+ ghc |= txclk;
CSR_WRITE_4(sc, JME_GHC, ghc);
CSR_WRITE_4(sc, JME_RXMAC, rxmac);
CSR_WRITE_4(sc, JME_TXMAC, txmac);
@@ -2132,6 +2209,7 @@ jme_link_task(void *arg, int pending)
/* Program MAC with resolved speed/duplex/flow-control. */
if ((sc->jme_flags & JME_FLAG_LINK) != 0) {
jme_mac_config(sc);
+ jme_stats_clear(sc);
CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
@@ -2521,6 +2599,7 @@ jme_tick(void *arg)
* faster and limit the maximum delay to a hz.
*/
jme_txeof(sc);
+ jme_stats_update(sc);
jme_watchdog(sc);
callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
}
@@ -2637,13 +2716,19 @@ jme_init_locked(struct jme_softc *sc)
* decrease FIFO threshold to reduce the FIFO overruns for
* frames larger than 4000 bytes.
* For best performance of standard MTU sized frames use
- * maximum allowable FIFO threshold, 128QW.
+ * maximum allowable FIFO threshold, 128QW. Note these do
+ * not hold on chip full mask verion >=2. For these
+ * controllers 64QW and 128QW are not valid value.
*/
- if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
- ETHER_CRC_LEN) > JME_RX_FIFO_SIZE)
+ if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2)
sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
- else
- sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
+ else {
+ if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
+ ETHER_CRC_LEN) > JME_RX_FIFO_SIZE)
+ sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
+ else
+ sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
+ }
sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
@@ -2824,6 +2909,8 @@ jme_stop(struct jme_softc *sc)
txd->tx_ndesc = 0;
}
}
+ jme_stats_update(sc);
+ jme_stats_save(sc);
}
static void
@@ -3055,6 +3142,76 @@ jme_set_filter(struct jme_softc *sc)
CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
}
+static void
+jme_stats_clear(struct jme_softc *sc)
+{
+
+ JME_LOCK_ASSERT(sc);
+
+ if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
+ return;
+
+ /* Disable and clear counters. */
+ CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
+ /* Activate hw counters. */
+ CSR_WRITE_4(sc, JME_STATCSR, 0);
+ CSR_READ_4(sc, JME_STATCSR);
+ bzero(&sc->jme_stats, sizeof(struct jme_hw_stats));
+}
+
+static void
+jme_stats_save(struct jme_softc *sc)
+{
+
+ JME_LOCK_ASSERT(sc);
+
+ if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
+ return;
+ /* Save current counters. */
+ bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats));
+ /* Disable and clear counters. */
+ CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
+}
+
+static void
+jme_stats_update(struct jme_softc *sc)
+{
+ struct jme_hw_stats *stat, *ostat;
+ uint32_t reg;
+
+ JME_LOCK_ASSERT(sc);
+
+ if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
+ return;
+ stat = &sc->jme_stats;
+ ostat = &sc->jme_ostats;
+ stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD);
+ stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD);
+ reg = CSR_READ_4(sc, JME_STAT_CRCMII);
+ stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >>
+ STAT_RX_CRC_ERR_SHIFT;
+ stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >>
+ STAT_RX_MII_ERR_SHIFT;
+ reg = CSR_READ_4(sc, JME_STAT_RXERR);
+ stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >>
+ STAT_RXERR_OFLOW_SHIFT;
+ stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >>
+ STAT_RXERR_MPTY_SHIFT;
+ reg = CSR_READ_4(sc, JME_STAT_FAIL);
+ stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT;
+ stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT;
+
+ /* Account for previous counters. */
+ stat->rx_good_frames += ostat->rx_good_frames;
+ stat->rx_crc_errs += ostat->rx_crc_errs;
+ stat->rx_mii_errs += ostat->rx_mii_errs;
+ stat->rx_fifo_oflows += ostat->rx_fifo_oflows;
+ stat->rx_desc_empty += ostat->rx_desc_empty;
+ stat->rx_bad_frames += ostat->rx_bad_frames;
+ stat->tx_good_frames += ostat->tx_good_frames;
+ stat->tx_bad_frames += ostat->tx_bad_frames;
+}
+
static int
sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
{
Modified: user/kmacy/head_arpv2/sys/dev/jme/if_jmereg.h
==============================================================================
--- user/kmacy/head_arpv2/sys/dev/jme/if_jmereg.h Wed Dec 10 02:10:44 2008 (r185820)
+++ user/kmacy/head_arpv2/sys/dev/jme/if_jmereg.h Wed Dec 10 02:18:55 2008 (r185821)
@@ -240,8 +240,8 @@
#define RXCSR_FIFO_FTHRESH_MASK 0x30000000
#define RXCSR_FIFO_THRESH_16QW 0x00000000
#define RXCSR_FIFO_THRESH_32QW 0x04000000
-#define RXCSR_FIFO_THRESH_64QW 0x08000000
-#define RXCSR_FIFO_THRESH_128QW 0x0C000000
+#define RXCSR_FIFO_THRESH_64QW 0x08000000 /* JMC250/JMC260 REVFM < 2 */
+#define RXCSR_FIFO_THRESH_128QW 0x0C000000 /* JMC250/JMC260 REVFM < 2 */
#define RXCSR_FIFO_THRESH_MASK 0x0C000000
#define RXCSR_DMA_SIZE_16 0x00000000
#define RXCSR_DMA_SIZE_32 0x01000000
@@ -358,6 +358,16 @@
#define JME_GHC 0x0054
#define GHC_LOOPBACK 0x80000000
#define GHC_RESET 0x40000000
+#define GHC_RX_DMA_PWR_DIS 0x04000000 /* JMC250 REVFM >= 2 */
+#define GHC_FIFO_RD_PWR_DIS 0x02000000 /* JMC250 REVFM >= 2 */
+#define GHC_FIFO_WR_PWR_DIS 0x01000000 /* JMC250 REVFM >= 2 */
+#define GHC_TX_OFFLD_CLK_100 0x00800000 /* JMC250/JMC260 REVFM >= 2 */
+#define GHC_TX_OFFLD_CLK_1000 0x00400000 /* JMC250/JMC260 REVFM >= 2 */
+#define GHC_TX_OFFLD_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */
+#define GHC_TX_MAC_CLK_100 0x00200000 /* JMC250/JMC260 REVFM >= 2 */
+#define GHC_TX_MAC_CLK_1000 0x00100000 /* JMC250/JMC260 REVFM >= 2 */
+#define GHC_TX_MAC_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */
+#define GHC_AUTO_PHY_STAT_DIS 0x00000080 /* JMC250/JMC260 REVFM >= 2 */
#define GHC_FULL_DUPLEX 0x00000040
#define GHC_SPEED_UNKNOWN 0x00000000
#define GHC_SPEED_10 0x00000010
@@ -794,6 +804,10 @@
#define CHIPMODE_MODE_128P_MAC 0x00000003
#define CHIPMODE_MODE_128P_DBG 0x00000002
#define CHIPMODE_MODE_128P_PHY 0x00000000
+/* Chip full mask revision. */
+#define CHIPMODE_REVFM(x) ((x) & 0x0F)
+/* Chip ECO revision. */
+#define CHIPMODE_REVECO(x) (((x) >> 4) & 0x0F)
/* Shadow status base address high/low. */
#define JME_SHBASE_ADDR_HI 0x0848
Modified: user/kmacy/head_arpv2/sys/dev/jme/if_jmevar.h
==============================================================================
--- user/kmacy/head_arpv2/sys/dev/jme/if_jmevar.h Wed Dec 10 02:10:44 2008 (r185820)
+++ user/kmacy/head_arpv2/sys/dev/jme/if_jmevar.h Wed Dec 10 02:18:55 2008 (r185821)
@@ -193,6 +193,8 @@ struct jme_softc {
#define JME_FLAG_PMCAP 0x0020
#define JME_FLAG_FASTETH 0x0040
#define JME_FLAG_NOJUMBO 0x0080
+#define JME_FLAG_TXCLK 0x0100
+#define JME_FLAG_DMA32BIT 0x0200
#define JME_FLAG_HWMIB 0x0400
#define JME_FLAG_DETACH 0x4000
#define JME_FLAG_LINK 0x8000
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