svn commit: r220076 - stable/8/sys/dev/dc

Pyun YongHyeon yongari at FreeBSD.org
Sun Mar 27 23:08:02 UTC 2011


Author: yongari
Date: Sun Mar 27 23:08:01 2011
New Revision: 220076
URL: http://svn.freebsd.org/changeset/base/220076

Log:
  MFC r218834-218835:
  r218834:
    Consistently use a tab character instead of space after #define.
    No functional changes.
  
  r218835:
    s/u_intXX_t/uintXX_t/g

Modified:
  stable/8/sys/dev/dc/if_dc.c
  stable/8/sys/dev/dc/if_dcreg.h
Directory Properties:
  stable/8/sys/   (props changed)
  stable/8/sys/amd64/include/xen/   (props changed)
  stable/8/sys/cddl/contrib/opensolaris/   (props changed)
  stable/8/sys/contrib/dev/acpica/   (props changed)
  stable/8/sys/contrib/pf/   (props changed)

Modified: stable/8/sys/dev/dc/if_dc.c
==============================================================================
--- stable/8/sys/dev/dc/if_dc.c	Sun Mar 27 23:03:15 2011	(r220075)
+++ stable/8/sys/dev/dc/if_dc.c	Sun Mar 27 23:08:01 2011	(r220076)
@@ -127,7 +127,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 
-#define DC_USEIOSPACE
+#define	DC_USEIOSPACE
 
 #include <dev/dc/if_dcreg.h>
 
@@ -261,16 +261,16 @@ static void dc_dma_map_addr(void *, bus_
 static void dc_delay(struct dc_softc *);
 static void dc_eeprom_idle(struct dc_softc *);
 static void dc_eeprom_putbyte(struct dc_softc *, int);
-static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *);
-static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *);
-static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *);
+static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *);
+static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *);
+static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *);
 static void dc_eeprom_width(struct dc_softc *);
 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
 
 static void dc_mii_writebit(struct dc_softc *, int);
 static int dc_mii_readbit(struct dc_softc *);
 static void dc_mii_sync(struct dc_softc *);
-static void dc_mii_send(struct dc_softc *, u_int32_t, int);
+static void dc_mii_send(struct dc_softc *, uint32_t, int);
 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
 static int dc_miibus_readreg(device_t, int, int);
@@ -301,11 +301,11 @@ static void dc_apply_fixup(struct dc_sof
 static int dc_check_multiport(struct dc_softc *);
 
 #ifdef DC_USEIOSPACE
-#define DC_RES			SYS_RES_IOPORT
-#define DC_RID			DC_PCI_CFBIO
+#define	DC_RES			SYS_RES_IOPORT
+#define	DC_RID			DC_PCI_CFBIO
 #else
-#define DC_RES			SYS_RES_MEMORY
-#define DC_RID			DC_PCI_CFBMA
+#define	DC_RES			SYS_RES_MEMORY
+#define	DC_RID			DC_PCI_CFBMA
 #endif
 
 static device_method_t dc_methods[] = {
@@ -341,14 +341,14 @@ static devclass_t dc_devclass;
 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
 
-#define DC_SETBIT(sc, reg, x)				\
+#define	DC_SETBIT(sc, reg, x)				\
 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
 
-#define DC_CLRBIT(sc, reg, x)				\
+#define	DC_CLRBIT(sc, reg, x)				\
 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
 
-#define SIO_SET(x)	DC_SETBIT(sc, DC_SIO, (x))
-#define SIO_CLR(x)	DC_CLRBIT(sc, DC_SIO, (x))
+#define	SIO_SET(x)	DC_SETBIT(sc, DC_SIO, (x))
+#define	SIO_CLR(x)	DC_CLRBIT(sc, DC_SIO, (x))
 
 static void
 dc_delay(struct dc_softc *sc)
@@ -495,10 +495,10 @@ dc_eeprom_putbyte(struct dc_softc *sc, i
  * the EEPROM.
  */
 static void
-dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
+dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest)
 {
 	int i;
-	u_int32_t r;
+	uint32_t r;
 
 	CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
 
@@ -506,7 +506,7 @@ dc_eeprom_getword_pnic(struct dc_softc *
 		DELAY(1);
 		r = CSR_READ_4(sc, DC_SIO);
 		if (!(r & DC_PN_SIOCTL_BUSY)) {
-			*dest = (u_int16_t)(r & 0xFFFF);
+			*dest = (uint16_t)(r & 0xFFFF);
 			return;
 		}
 	}
@@ -518,17 +518,17 @@ dc_eeprom_getword_pnic(struct dc_softc *
  * the EEPROM, too.
  */
 static void
-dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
+dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest)
 {
 
 	SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
 
 	addr *= 2;
 	CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
-	*dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
+	*dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
 	addr += 1;
 	CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
-	*dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
+	*dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
 
 	SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
 }
@@ -537,10 +537,10 @@ dc_eeprom_getword_xircom(struct dc_softc
  * Read a word of data stored in the EEPROM at address 'addr.'
  */
 static void
-dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
+dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest)
 {
 	int i;
-	u_int16_t word = 0;
+	uint16_t word = 0;
 
 	/* Force EEPROM to idle state. */
 	dc_eeprom_idle(sc);
@@ -586,7 +586,7 @@ static void
 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
 {
 	int i;
-	u_int16_t word = 0, *ptr;
+	uint16_t word = 0, *ptr;
 
 	for (i = 0; i < cnt; i++) {
 		if (DC_IS_PNIC(sc))
@@ -595,7 +595,7 @@ dc_read_eeprom(struct dc_softc *sc, cadd
 			dc_eeprom_getword_xircom(sc, off + i, &word);
 		else
 			dc_eeprom_getword(sc, off + i, &word);
-		ptr = (u_int16_t *)(dest + (i * 2));
+		ptr = (uint16_t *)(dest + (i * 2));
 		if (be)
 			*ptr = be16toh(word);
 		else
@@ -680,7 +680,7 @@ dc_mii_sync(struct dc_softc *sc)
  * Clock a series of bits through the MII.
  */
 static void
-dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
+dc_mii_send(struct dc_softc *sc, uint32_t bits, int cnt)
 {
 	int i;
 
@@ -1016,9 +1016,9 @@ dc_miibus_mediainit(device_t dev)
 		ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
 }
 
-#define DC_BITS_512	9
-#define DC_BITS_128	7
-#define DC_BITS_64	6
+#define	DC_BITS_512	9
+#define	DC_BITS_128	7
+#define	DC_BITS_64	6
 
 static uint32_t
 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
@@ -1082,7 +1082,7 @@ dc_setfilt_21143(struct dc_softc *sc)
 {
 	uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
 	struct dc_desc *sframe;
-	u_int32_t h, *sp;
+	uint32_t h, *sp;
 	struct ifmultiaddr *ifma;
 	struct ifnet *ifp;
 	int i;
@@ -1156,7 +1156,7 @@ dc_setfilt_admtek(struct dc_softc *sc)
 	struct ifnet *ifp;
 	struct ifmultiaddr *ifma;
 	int h = 0;
-	u_int32_t hashes[2] = { 0, 0 };
+	uint32_t hashes[2] = { 0, 0 };
 
 	ifp = sc->dc_ifp;
 
@@ -1217,7 +1217,7 @@ dc_setfilt_asix(struct dc_softc *sc)
 	struct ifnet *ifp;
 	struct ifmultiaddr *ifma;
 	int h = 0;
-	u_int32_t hashes[2] = { 0, 0 };
+	uint32_t hashes[2] = { 0, 0 };
 
 	ifp = sc->dc_ifp;
 
@@ -1287,7 +1287,7 @@ dc_setfilt_xircom(struct dc_softc *sc)
 	struct ifnet *ifp;
 	struct ifmultiaddr *ifma;
 	struct dc_desc *sframe;
-	u_int32_t h, *sp;
+	uint32_t h, *sp;
 	int i;
 
 	ifp = sc->dc_ifp;
@@ -1379,7 +1379,7 @@ static void
 dc_setcfg(struct dc_softc *sc, int media)
 {
 	int i, restart = 0, watchdogreg;
-	u_int32_t isr;
+	uint32_t isr;
 
 	if (IFM_SUBTYPE(media) == IFM_NONE)
 		return;
@@ -1563,8 +1563,8 @@ static const struct dc_type *
 dc_devtype(device_t dev)
 {
 	const struct dc_type *t;
-	u_int32_t devid;
-	u_int8_t rev;
+	uint32_t devid;
+	uint8_t rev;
 
 	t = dc_devs;
 	devid = pci_get_devid(dev);
@@ -1607,9 +1607,9 @@ static void
 dc_apply_fixup(struct dc_softc *sc, int media)
 {
 	struct dc_mediainfo *m;
-	u_int8_t *p;
+	uint8_t *p;
 	int i;
-	u_int32_t reg;
+	uint32_t reg;
 
 	m = sc->dc_mi;
 
@@ -1668,11 +1668,11 @@ dc_decode_leaf_sia(struct dc_softc *sc, 
 	if (l->dc_sia_code & DC_SIA_CODE_EXT) {
 		m->dc_gp_len = 2;
 		m->dc_gp_ptr =
-		(u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
+		(uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
 	} else {
 		m->dc_gp_len = 2;
 		m->dc_gp_ptr =
-		(u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
+		(uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
 	}
 
 	m->dc_next = sc->dc_mi;
@@ -1699,7 +1699,7 @@ dc_decode_leaf_sym(struct dc_softc *sc, 
 		m->dc_media = IFM_100_TX | IFM_FDX;
 
 	m->dc_gp_len = 2;
-	m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
+	m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl;
 
 	m->dc_next = sc->dc_mi;
 	sc->dc_mi = m;
@@ -1712,7 +1712,7 @@ static int
 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
 {
 	struct dc_mediainfo *m;
-	u_int8_t *p;
+	uint8_t *p;
 
 	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
 	if (m == NULL) {
@@ -1723,7 +1723,7 @@ dc_decode_leaf_mii(struct dc_softc *sc, 
 	m->dc_media = IFM_AUTO;
 	m->dc_gp_len = l->dc_gpr_len;
 
-	p = (u_int8_t *)l;
+	p = (uint8_t *)l;
 	p += sizeof(struct dc_eblock_mii);
 	m->dc_gp_ptr = p;
 	p += 2 * l->dc_gpr_len;
@@ -2031,13 +2031,13 @@ static int
 dc_attach(device_t dev)
 {
 	uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
-	u_int32_t command;
+	uint32_t command;
 	struct dc_softc *sc;
 	struct ifnet *ifp;
 	struct dc_mediainfo *m;
-	u_int32_t reg, revision;
+	uint32_t reg, revision;
 	int error, mac_offset, phy, rid, tmp;
-	u_int8_t *mac;
+	uint8_t *mac;
 
 	sc = device_get_softc(dev);
 	sc->dc_dev = dev;
@@ -2715,7 +2715,7 @@ dc_newbuf(struct dc_softc *sc, int i)
  * the time.
  */
 
-#define DC_WHOLEFRAME	(DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
+#define	DC_WHOLEFRAME	(DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
 static void
 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
 {
@@ -2724,7 +2724,7 @@ dc_pnic_rx_bug_war(struct dc_softc *sc, 
 	struct mbuf *m = NULL;
 	unsigned char *ptr;
 	int i, total_len;
-	u_int32_t rxstat = 0;
+	uint32_t rxstat = 0;
 
 	i = sc->dc_pnic_rx_bug_save;
 	cur_rx = &sc->dc_ldata.dc_rx_list[idx];
@@ -2835,7 +2835,7 @@ dc_rxeof(struct dc_softc *sc)
 	struct ifnet *ifp;
 	struct dc_desc *cur_rx;
 	int i, total_len, rx_npkts;
-	u_int32_t rxstat;
+	uint32_t rxstat;
 
 	DC_LOCK_ASSERT(sc);
 
@@ -2956,7 +2956,7 @@ dc_txeof(struct dc_softc *sc)
 	struct dc_desc *cur_tx;
 	struct ifnet *ifp;
 	int idx, setup;
-	u_int32_t ctl, txstat;
+	uint32_t ctl, txstat;
 
 	if (sc->dc_cdata.dc_tx_cnt == 0)
 		return;
@@ -3065,7 +3065,7 @@ dc_tick(void *xsc)
 	struct dc_softc *sc;
 	struct mii_data *mii;
 	struct ifnet *ifp;
-	u_int32_t r;
+	uint32_t r;
 
 	sc = xsc;
 	DC_LOCK_ASSERT(sc);
@@ -3142,7 +3142,7 @@ dc_tick(void *xsc)
 static void
 dc_tx_underrun(struct dc_softc *sc)
 {
-	u_int32_t isr;
+	uint32_t isr;
 	int i;
 
 	if (DC_IS_DAVICOM(sc)) {
@@ -3212,7 +3212,7 @@ dc_poll(struct ifnet *ifp, enum poll_cmd
 		dc_start_locked(ifp);
 
 	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
-		u_int32_t	status;
+		uint32_t	status;
 
 		status = CSR_READ_4(sc, DC_ISR);
 		status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
@@ -3226,7 +3226,7 @@ dc_poll(struct ifnet *ifp, enum poll_cmd
 		CSR_WRITE_4(sc, DC_ISR, status);
 
 		if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
-			u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
+			uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
 			ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
 
 			if (dc_rx_resync(sc))
@@ -3255,7 +3255,7 @@ dc_intr(void *arg)
 {
 	struct dc_softc *sc;
 	struct ifnet *ifp;
-	u_int32_t r, status;
+	uint32_t r, status;
 	int curpkts, n;
 
 	sc = arg;
@@ -3917,7 +3917,7 @@ dc_stop(struct dc_softc *sc)
 	struct dc_list_data *ld;
 	struct dc_chain_data *cd;
 	int i;
-	u_int32_t ctl;
+	uint32_t ctl;
 
 	DC_LOCK_ASSERT(sc);
 

Modified: stable/8/sys/dev/dc/if_dcreg.h
==============================================================================
--- stable/8/sys/dev/dc/if_dcreg.h	Sun Mar 27 23:03:15 2011	(r220075)
+++ stable/8/sys/dev/dc/if_dcreg.h	Sun Mar 27 23:08:01 2011	(r220076)
@@ -36,23 +36,23 @@
  * 21143 and clone common register definitions.
  */
 
-#define DC_BUSCTL		0x00	/* bus control */
-#define DC_TXSTART		0x08	/* tx start demand */
-#define DC_RXSTART		0x10	/* rx start demand */
-#define DC_RXADDR		0x18	/* rx descriptor list start addr */
-#define DC_TXADDR		0x20	/* tx descriptor list start addr */
-#define DC_ISR			0x28	/* interrupt status register */
-#define DC_NETCFG		0x30	/* network config register */
-#define DC_IMR			0x38	/* interrupt mask */
-#define DC_FRAMESDISCARDED	0x40	/* # of discarded frames */
-#define DC_SIO			0x48	/* MII and ROM/EEPROM access */
-#define DC_ROM			0x50	/* ROM programming address */
-#define DC_TIMER		0x58	/* general timer */
-#define DC_10BTSTAT		0x60	/* SIA status */
-#define DC_SIARESET		0x68	/* SIA connectivity */
-#define DC_10BTCTRL		0x70	/* SIA transmit and receive */
-#define DC_WATCHDOG		0x78	/* SIA and general purpose port */
-#define DC_SIAGP		0x78	/* SIA and general purpose port (X3201) */
+#define	DC_BUSCTL		0x00	/* bus control */
+#define	DC_TXSTART		0x08	/* tx start demand */
+#define	DC_RXSTART		0x10	/* rx start demand */
+#define	DC_RXADDR		0x18	/* rx descriptor list start addr */
+#define	DC_TXADDR		0x20	/* tx descriptor list start addr */
+#define	DC_ISR			0x28	/* interrupt status register */
+#define	DC_NETCFG		0x30	/* network config register */
+#define	DC_IMR			0x38	/* interrupt mask */
+#define	DC_FRAMESDISCARDED	0x40	/* # of discarded frames */
+#define	DC_SIO			0x48	/* MII and ROM/EEPROM access */
+#define	DC_ROM			0x50	/* ROM programming address */
+#define	DC_TIMER		0x58	/* general timer */
+#define	DC_10BTSTAT		0x60	/* SIA status */
+#define	DC_SIARESET		0x68	/* SIA connectivity */
+#define	DC_10BTCTRL		0x70	/* SIA transmit and receive */
+#define	DC_WATCHDOG		0x78	/* SIA and general purpose port */
+#define	DC_SIAGP		0x78	/* SIA and general purpose port (X3201) */
 
 /*
  * There are two general 'types' of MX chips that we need to be
@@ -64,427 +64,427 @@
  * 'magic' numbers we write to CSR16. The PNIC II falls into the
  * 98713A/98715/98715A/98725 category.
  */
-#define DC_TYPE_98713		0x1
-#define DC_TYPE_98713A		0x2
-#define DC_TYPE_987x5		0x3
+#define	DC_TYPE_98713		0x1
+#define	DC_TYPE_98713A		0x2
+#define	DC_TYPE_987x5		0x3
 
 /* Other type of supported chips. */
-#define DC_TYPE_21143		0x4	/* Intel 21143 */
-#define DC_TYPE_ASIX		0x5	/* ASIX AX88140A/AX88141 */
-#define DC_TYPE_AL981		0x6	/* ADMtek AL981 Comet */
-#define DC_TYPE_AN983		0x7	/* ADMtek AN983 Centaur */
-#define DC_TYPE_DM9102		0x8	/* Davicom DM9102 */
-#define DC_TYPE_PNICII		0x9	/* 82c115 PNIC II */
-#define DC_TYPE_PNIC		0xA	/* 82c168/82c169 PNIC I */
+#define	DC_TYPE_21143		0x4	/* Intel 21143 */
+#define	DC_TYPE_ASIX		0x5	/* ASIX AX88140A/AX88141 */
+#define	DC_TYPE_AL981		0x6	/* ADMtek AL981 Comet */
+#define	DC_TYPE_AN983		0x7	/* ADMtek AN983 Centaur */
+#define	DC_TYPE_DM9102		0x8	/* Davicom DM9102 */
+#define	DC_TYPE_PNICII		0x9	/* 82c115 PNIC II */
+#define	DC_TYPE_PNIC		0xA	/* 82c168/82c169 PNIC I */
 #define	DC_TYPE_XIRCOM		0xB	/* Xircom X3201 */
-#define DC_TYPE_CONEXANT	0xC	/* Conexant LANfinity RS7112 */
+#define	DC_TYPE_CONEXANT	0xC	/* Conexant LANfinity RS7112 */
 
-#define DC_IS_MACRONIX(x)			\
+#define	DC_IS_MACRONIX(x)			\
 	(x->dc_type == DC_TYPE_98713 ||		\
 	 x->dc_type == DC_TYPE_98713A ||	\
 	 x->dc_type == DC_TYPE_987x5)
 
-#define DC_IS_ADMTEK(x)				\
+#define	DC_IS_ADMTEK(x)				\
 	(x->dc_type == DC_TYPE_AL981 ||		\
 	 x->dc_type == DC_TYPE_AN983)
 
-#define DC_IS_INTEL(x)		(x->dc_type == DC_TYPE_21143)
-#define DC_IS_ASIX(x)		(x->dc_type == DC_TYPE_ASIX)
-#define DC_IS_COMET(x)		(x->dc_type == DC_TYPE_AL981)
-#define DC_IS_CENTAUR(x)	(x->dc_type == DC_TYPE_AN983)
-#define DC_IS_DAVICOM(x)	(x->dc_type == DC_TYPE_DM9102)
-#define DC_IS_PNICII(x)		(x->dc_type == DC_TYPE_PNICII)
-#define DC_IS_PNIC(x)		(x->dc_type == DC_TYPE_PNIC)
+#define	DC_IS_INTEL(x)		(x->dc_type == DC_TYPE_21143)
+#define	DC_IS_ASIX(x)		(x->dc_type == DC_TYPE_ASIX)
+#define	DC_IS_COMET(x)		(x->dc_type == DC_TYPE_AL981)
+#define	DC_IS_CENTAUR(x)	(x->dc_type == DC_TYPE_AN983)
+#define	DC_IS_DAVICOM(x)	(x->dc_type == DC_TYPE_DM9102)
+#define	DC_IS_PNICII(x)		(x->dc_type == DC_TYPE_PNICII)
+#define	DC_IS_PNIC(x)		(x->dc_type == DC_TYPE_PNIC)
 #define	DC_IS_XIRCOM(x)		(x->dc_type == DC_TYPE_XIRCOM)
-#define DC_IS_CONEXANT(x)	(x->dc_type == DC_TYPE_CONEXANT)
+#define	DC_IS_CONEXANT(x)	(x->dc_type == DC_TYPE_CONEXANT)
 
 /* MII/symbol mode port types */
-#define DC_PMODE_MII		0x1
-#define DC_PMODE_SYM		0x2
-#define DC_PMODE_SIA		0x3
+#define	DC_PMODE_MII		0x1
+#define	DC_PMODE_SYM		0x2
+#define	DC_PMODE_SIA		0x3
 
 /*
  * Bus control bits.
  */
-#define DC_BUSCTL_RESET		0x00000001
-#define DC_BUSCTL_ARBITRATION	0x00000002
-#define DC_BUSCTL_SKIPLEN	0x0000007C
-#define DC_BUSCTL_BUF_BIGENDIAN	0x00000080
-#define DC_BUSCTL_BURSTLEN	0x00003F00
-#define DC_BUSCTL_CACHEALIGN	0x0000C000
-#define DC_BUSCTL_TXPOLL	0x000E0000
-#define DC_BUSCTL_DBO		0x00100000
-#define DC_BUSCTL_MRME		0x00200000
-#define DC_BUSCTL_MRLE		0x00800000
-#define DC_BUSCTL_MWIE		0x01000000
-#define DC_BUSCTL_ONNOW_ENB	0x04000000
-
-#define DC_SKIPLEN_1LONG	0x00000004
-#define DC_SKIPLEN_2LONG	0x00000008
-#define DC_SKIPLEN_3LONG	0x00000010
-#define DC_SKIPLEN_4LONG	0x00000020
-#define DC_SKIPLEN_5LONG	0x00000040
-
-#define DC_CACHEALIGN_NONE	0x00000000
-#define DC_CACHEALIGN_8LONG	0x00004000
-#define DC_CACHEALIGN_16LONG	0x00008000
-#define DC_CACHEALIGN_32LONG	0x0000C000
-
-#define DC_BURSTLEN_USECA	0x00000000
-#define DC_BURSTLEN_1LONG	0x00000100
-#define DC_BURSTLEN_2LONG	0x00000200
-#define DC_BURSTLEN_4LONG	0x00000400
-#define DC_BURSTLEN_8LONG	0x00000800
-#define DC_BURSTLEN_16LONG	0x00001000
-#define DC_BURSTLEN_32LONG	0x00002000
-
-#define DC_TXPOLL_OFF		0x00000000
-#define DC_TXPOLL_1		0x00020000
-#define DC_TXPOLL_2		0x00040000
-#define DC_TXPOLL_3		0x00060000
-#define DC_TXPOLL_4		0x00080000
-#define DC_TXPOLL_5		0x000A0000
-#define DC_TXPOLL_6		0x000C0000
-#define DC_TXPOLL_7		0x000E0000
+#define	DC_BUSCTL_RESET		0x00000001
+#define	DC_BUSCTL_ARBITRATION	0x00000002
+#define	DC_BUSCTL_SKIPLEN	0x0000007C
+#define	DC_BUSCTL_BUF_BIGENDIAN	0x00000080
+#define	DC_BUSCTL_BURSTLEN	0x00003F00
+#define	DC_BUSCTL_CACHEALIGN	0x0000C000
+#define	DC_BUSCTL_TXPOLL	0x000E0000
+#define	DC_BUSCTL_DBO		0x00100000
+#define	DC_BUSCTL_MRME		0x00200000
+#define	DC_BUSCTL_MRLE		0x00800000
+#define	DC_BUSCTL_MWIE		0x01000000
+#define	DC_BUSCTL_ONNOW_ENB	0x04000000
+
+#define	DC_SKIPLEN_1LONG	0x00000004
+#define	DC_SKIPLEN_2LONG	0x00000008
+#define	DC_SKIPLEN_3LONG	0x00000010
+#define	DC_SKIPLEN_4LONG	0x00000020
+#define	DC_SKIPLEN_5LONG	0x00000040
+
+#define	DC_CACHEALIGN_NONE	0x00000000
+#define	DC_CACHEALIGN_8LONG	0x00004000
+#define	DC_CACHEALIGN_16LONG	0x00008000
+#define	DC_CACHEALIGN_32LONG	0x0000C000
+
+#define	DC_BURSTLEN_USECA	0x00000000
+#define	DC_BURSTLEN_1LONG	0x00000100
+#define	DC_BURSTLEN_2LONG	0x00000200
+#define	DC_BURSTLEN_4LONG	0x00000400
+#define	DC_BURSTLEN_8LONG	0x00000800
+#define	DC_BURSTLEN_16LONG	0x00001000
+#define	DC_BURSTLEN_32LONG	0x00002000
+
+#define	DC_TXPOLL_OFF		0x00000000
+#define	DC_TXPOLL_1		0x00020000
+#define	DC_TXPOLL_2		0x00040000
+#define	DC_TXPOLL_3		0x00060000
+#define	DC_TXPOLL_4		0x00080000
+#define	DC_TXPOLL_5		0x000A0000
+#define	DC_TXPOLL_6		0x000C0000
+#define	DC_TXPOLL_7		0x000E0000
 
 /*
  * Interrupt status bits.
  */
-#define DC_ISR_TX_OK		0x00000001
-#define DC_ISR_TX_IDLE		0x00000002
-#define DC_ISR_TX_NOBUF		0x00000004
-#define DC_ISR_TX_JABBERTIMEO	0x00000008
-#define DC_ISR_LINKGOOD		0x00000010
-#define DC_ISR_TX_UNDERRUN	0x00000020
-#define DC_ISR_RX_OK		0x00000040
-#define DC_ISR_RX_NOBUF		0x00000080
-#define DC_ISR_RX_READ		0x00000100
-#define DC_ISR_RX_WATDOGTIMEO	0x00000200
-#define DC_ISR_TX_EARLY		0x00000400
-#define DC_ISR_TIMER_EXPIRED	0x00000800
-#define DC_ISR_LINKFAIL		0x00001000
-#define DC_ISR_BUS_ERR		0x00002000
-#define DC_ISR_RX_EARLY		0x00004000
-#define DC_ISR_ABNORMAL		0x00008000
-#define DC_ISR_NORMAL		0x00010000
-#define DC_ISR_RX_STATE		0x000E0000
-#define DC_ISR_TX_STATE		0x00700000
-#define DC_ISR_BUSERRTYPE	0x03800000
-#define DC_ISR_100MBPSLINK	0x08000000
-#define DC_ISR_MAGICKPACK	0x10000000
-
-#define DC_RXSTATE_STOPPED	0x00000000	/* 000 - Stopped */
-#define DC_RXSTATE_FETCH	0x00020000	/* 001 - Fetching descriptor */
-#define DC_RXSTATE_ENDCHECK	0x00040000	/* 010 - check for rx end */
-#define DC_RXSTATE_WAIT		0x00060000	/* 011 - waiting for packet */
-#define DC_RXSTATE_SUSPEND	0x00080000	/* 100 - suspend rx */
-#define DC_RXSTATE_CLOSE	0x000A0000	/* 101 - close tx desc */
-#define DC_RXSTATE_FLUSH	0x000C0000	/* 110 - flush from FIFO */
-#define DC_RXSTATE_DEQUEUE	0x000E0000	/* 111 - dequeue from FIFO */
+#define	DC_ISR_TX_OK		0x00000001
+#define	DC_ISR_TX_IDLE		0x00000002
+#define	DC_ISR_TX_NOBUF		0x00000004
+#define	DC_ISR_TX_JABBERTIMEO	0x00000008
+#define	DC_ISR_LINKGOOD		0x00000010
+#define	DC_ISR_TX_UNDERRUN	0x00000020
+#define	DC_ISR_RX_OK		0x00000040
+#define	DC_ISR_RX_NOBUF		0x00000080
+#define	DC_ISR_RX_READ		0x00000100
+#define	DC_ISR_RX_WATDOGTIMEO	0x00000200
+#define	DC_ISR_TX_EARLY		0x00000400
+#define	DC_ISR_TIMER_EXPIRED	0x00000800
+#define	DC_ISR_LINKFAIL		0x00001000
+#define	DC_ISR_BUS_ERR		0x00002000
+#define	DC_ISR_RX_EARLY		0x00004000
+#define	DC_ISR_ABNORMAL		0x00008000
+#define	DC_ISR_NORMAL		0x00010000
+#define	DC_ISR_RX_STATE		0x000E0000
+#define	DC_ISR_TX_STATE		0x00700000
+#define	DC_ISR_BUSERRTYPE	0x03800000
+#define	DC_ISR_100MBPSLINK	0x08000000
+#define	DC_ISR_MAGICKPACK	0x10000000
+
+#define	DC_RXSTATE_STOPPED	0x00000000	/* 000 - Stopped */
+#define	DC_RXSTATE_FETCH	0x00020000	/* 001 - Fetching descriptor */
+#define	DC_RXSTATE_ENDCHECK	0x00040000	/* 010 - check for rx end */
+#define	DC_RXSTATE_WAIT		0x00060000	/* 011 - waiting for packet */
+#define	DC_RXSTATE_SUSPEND	0x00080000	/* 100 - suspend rx */
+#define	DC_RXSTATE_CLOSE	0x000A0000	/* 101 - close tx desc */
+#define	DC_RXSTATE_FLUSH	0x000C0000	/* 110 - flush from FIFO */
+#define	DC_RXSTATE_DEQUEUE	0x000E0000	/* 111 - dequeue from FIFO */
 
 #define	DC_HAS_BROKEN_RXSTATE(x)					\
 	(DC_IS_CENTAUR(x) || DC_IS_CONEXANT(x) || (DC_IS_DAVICOM(x) &&	\
 	pci_get_revid((x)->dc_dev) >= DC_REVISION_DM9102A))
 
-#define DC_TXSTATE_RESET	0x00000000	/* 000 - reset */
-#define DC_TXSTATE_FETCH	0x00100000	/* 001 - fetching descriptor */
-#define DC_TXSTATE_WAITEND	0x00200000	/* 010 - wait for tx end */
-#define DC_TXSTATE_READING	0x00300000	/* 011 - read and enqueue */
-#define DC_TXSTATE_RSVD		0x00400000	/* 100 - reserved */
-#define DC_TXSTATE_SETUP	0x00500000	/* 101 - setup packet */
-#define DC_TXSTATE_SUSPEND	0x00600000	/* 110 - suspend tx */
-#define DC_TXSTATE_CLOSE	0x00700000	/* 111 - close tx desc */
+#define	DC_TXSTATE_RESET	0x00000000	/* 000 - reset */
+#define	DC_TXSTATE_FETCH	0x00100000	/* 001 - fetching descriptor */
+#define	DC_TXSTATE_WAITEND	0x00200000	/* 010 - wait for tx end */
+#define	DC_TXSTATE_READING	0x00300000	/* 011 - read and enqueue */
+#define	DC_TXSTATE_RSVD		0x00400000	/* 100 - reserved */
+#define	DC_TXSTATE_SETUP	0x00500000	/* 101 - setup packet */
+#define	DC_TXSTATE_SUSPEND	0x00600000	/* 110 - suspend tx */
+#define	DC_TXSTATE_CLOSE	0x00700000	/* 111 - close tx desc */
 
 /*
  * Network config bits.
  */
-#define DC_NETCFG_RX_HASHPERF	0x00000001
-#define DC_NETCFG_RX_ON		0x00000002
-#define DC_NETCFG_RX_HASHONLY	0x00000004
-#define DC_NETCFG_RX_BADFRAMES	0x00000008
-#define DC_NETCFG_RX_INVFILT	0x00000010
-#define DC_NETCFG_BACKOFFCNT	0x00000020
-#define DC_NETCFG_RX_PROMISC	0x00000040
-#define DC_NETCFG_RX_ALLMULTI	0x00000080
-#define DC_NETCFG_FULLDUPLEX	0x00000200
-#define DC_NETCFG_LOOPBACK	0x00000C00
-#define DC_NETCFG_FORCECOLL	0x00001000
-#define DC_NETCFG_TX_ON		0x00002000
-#define DC_NETCFG_TX_THRESH	0x0000C000
-#define DC_NETCFG_TX_BACKOFF	0x00020000
-#define DC_NETCFG_PORTSEL	0x00040000	/* 0 == 10, 1 == 100 */
-#define DC_NETCFG_HEARTBEAT	0x00080000
-#define DC_NETCFG_STORENFWD	0x00200000
-#define DC_NETCFG_SPEEDSEL	0x00400000	/* 1 == 10, 0 == 100 */
-#define DC_NETCFG_PCS		0x00800000
-#define DC_NETCFG_SCRAMBLER	0x01000000
-#define DC_NETCFG_NO_RXCRC	0x02000000
-#define DC_NETCFG_RX_ALL	0x40000000
-#define DC_NETCFG_CAPEFFECT	0x80000000
-
-#define DC_OPMODE_NORM		0x00000000
-#define DC_OPMODE_INTLOOP	0x00000400
-#define DC_OPMODE_EXTLOOP	0x00000800
+#define	DC_NETCFG_RX_HASHPERF	0x00000001
+#define	DC_NETCFG_RX_ON		0x00000002
+#define	DC_NETCFG_RX_HASHONLY	0x00000004
+#define	DC_NETCFG_RX_BADFRAMES	0x00000008
+#define	DC_NETCFG_RX_INVFILT	0x00000010
+#define	DC_NETCFG_BACKOFFCNT	0x00000020
+#define	DC_NETCFG_RX_PROMISC	0x00000040
+#define	DC_NETCFG_RX_ALLMULTI	0x00000080
+#define	DC_NETCFG_FULLDUPLEX	0x00000200
+#define	DC_NETCFG_LOOPBACK	0x00000C00
+#define	DC_NETCFG_FORCECOLL	0x00001000
+#define	DC_NETCFG_TX_ON		0x00002000
+#define	DC_NETCFG_TX_THRESH	0x0000C000
+#define	DC_NETCFG_TX_BACKOFF	0x00020000
+#define	DC_NETCFG_PORTSEL	0x00040000	/* 0 == 10, 1 == 100 */
+#define	DC_NETCFG_HEARTBEAT	0x00080000
+#define	DC_NETCFG_STORENFWD	0x00200000
+#define	DC_NETCFG_SPEEDSEL	0x00400000	/* 1 == 10, 0 == 100 */
+#define	DC_NETCFG_PCS		0x00800000
+#define	DC_NETCFG_SCRAMBLER	0x01000000
+#define	DC_NETCFG_NO_RXCRC	0x02000000
+#define	DC_NETCFG_RX_ALL	0x40000000
+#define	DC_NETCFG_CAPEFFECT	0x80000000
+
+#define	DC_OPMODE_NORM		0x00000000
+#define	DC_OPMODE_INTLOOP	0x00000400
+#define	DC_OPMODE_EXTLOOP	0x00000800
 
 #if 0
-#define DC_TXTHRESH_72BYTES	0x00000000
-#define DC_TXTHRESH_96BYTES	0x00004000
-#define DC_TXTHRESH_128BYTES	0x00008000
-#define DC_TXTHRESH_160BYTES	0x0000C000
+#define	DC_TXTHRESH_72BYTES	0x00000000
+#define	DC_TXTHRESH_96BYTES	0x00004000
+#define	DC_TXTHRESH_128BYTES	0x00008000
+#define	DC_TXTHRESH_160BYTES	0x0000C000
 #endif
 
-#define DC_TXTHRESH_MIN		0x00000000
-#define DC_TXTHRESH_INC		0x00004000
-#define DC_TXTHRESH_MAX		0x0000C000
+#define	DC_TXTHRESH_MIN		0x00000000
+#define	DC_TXTHRESH_INC		0x00004000
+#define	DC_TXTHRESH_MAX		0x0000C000
 
 
 /*
  * Interrupt mask bits.
  */
-#define DC_IMR_TX_OK		0x00000001
-#define DC_IMR_TX_IDLE		0x00000002
-#define DC_IMR_TX_NOBUF		0x00000004
-#define DC_IMR_TX_JABBERTIMEO	0x00000008
-#define DC_IMR_LINKGOOD		0x00000010
-#define DC_IMR_TX_UNDERRUN	0x00000020
-#define DC_IMR_RX_OK		0x00000040
-#define DC_IMR_RX_NOBUF		0x00000080
-#define DC_IMR_RX_READ		0x00000100
-#define DC_IMR_RX_WATDOGTIMEO	0x00000200
-#define DC_IMR_TX_EARLY		0x00000400
-#define DC_IMR_TIMER_EXPIRED	0x00000800
-#define DC_IMR_LINKFAIL		0x00001000
-#define DC_IMR_BUS_ERR		0x00002000
-#define DC_IMR_RX_EARLY		0x00004000
-#define DC_IMR_ABNORMAL		0x00008000
-#define DC_IMR_NORMAL		0x00010000
-#define DC_IMR_100MBPSLINK	0x08000000
-#define DC_IMR_MAGICKPACK	0x10000000
+#define	DC_IMR_TX_OK		0x00000001
+#define	DC_IMR_TX_IDLE		0x00000002
+#define	DC_IMR_TX_NOBUF		0x00000004
+#define	DC_IMR_TX_JABBERTIMEO	0x00000008
+#define	DC_IMR_LINKGOOD		0x00000010
+#define	DC_IMR_TX_UNDERRUN	0x00000020
+#define	DC_IMR_RX_OK		0x00000040
+#define	DC_IMR_RX_NOBUF		0x00000080
+#define	DC_IMR_RX_READ		0x00000100
+#define	DC_IMR_RX_WATDOGTIMEO	0x00000200
+#define	DC_IMR_TX_EARLY		0x00000400
+#define	DC_IMR_TIMER_EXPIRED	0x00000800
+#define	DC_IMR_LINKFAIL		0x00001000
+#define	DC_IMR_BUS_ERR		0x00002000
+#define	DC_IMR_RX_EARLY		0x00004000
+#define	DC_IMR_ABNORMAL		0x00008000
+#define	DC_IMR_NORMAL		0x00010000
+#define	DC_IMR_100MBPSLINK	0x08000000
+#define	DC_IMR_MAGICKPACK	0x10000000
 
-#define DC_INTRS	\
+#define	DC_INTRS	\
 	(DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\
 	DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR|		\
 	DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/)
 /*
  * Serial I/O (EEPROM/ROM) bits.
  */
-#define DC_SIO_EE_CS		0x00000001	/* EEPROM chip select */
-#define DC_SIO_EE_CLK		0x00000002	/* EEPROM clock */
-#define DC_SIO_EE_DATAIN	0x00000004	/* EEPROM data output */
-#define DC_SIO_EE_DATAOUT	0x00000008	/* EEPROM data input */
-#define DC_SIO_ROMDATA4		0x00000010
-#define DC_SIO_ROMDATA5		0x00000020
-#define DC_SIO_ROMDATA6		0x00000040
-#define DC_SIO_ROMDATA7		0x00000080
-#define DC_SIO_EESEL		0x00000800
-#define DC_SIO_ROMSEL		0x00001000
-#define DC_SIO_ROMCTL_WRITE	0x00002000
-#define DC_SIO_ROMCTL_READ	0x00004000
-#define DC_SIO_MII_CLK		0x00010000	/* MDIO clock */
-#define DC_SIO_MII_DATAOUT	0x00020000	/* MDIO data out */
-#define DC_SIO_MII_DIR		0x00040000	/* MDIO dir */
-#define DC_SIO_MII_DATAIN	0x00080000	/* MDIO data in */
-
-#define DC_EECMD_WRITE		0x140
-#define DC_EECMD_READ		0x180
-#define DC_EECMD_ERASE		0x1c0
+#define	DC_SIO_EE_CS		0x00000001	/* EEPROM chip select */
+#define	DC_SIO_EE_CLK		0x00000002	/* EEPROM clock */
+#define	DC_SIO_EE_DATAIN	0x00000004	/* EEPROM data output */
+#define	DC_SIO_EE_DATAOUT	0x00000008	/* EEPROM data input */
+#define	DC_SIO_ROMDATA4		0x00000010
+#define	DC_SIO_ROMDATA5		0x00000020
+#define	DC_SIO_ROMDATA6		0x00000040
+#define	DC_SIO_ROMDATA7		0x00000080
+#define	DC_SIO_EESEL		0x00000800
+#define	DC_SIO_ROMSEL		0x00001000
+#define	DC_SIO_ROMCTL_WRITE	0x00002000
+#define	DC_SIO_ROMCTL_READ	0x00004000
+#define	DC_SIO_MII_CLK		0x00010000	/* MDIO clock */
+#define	DC_SIO_MII_DATAOUT	0x00020000	/* MDIO data out */
+#define	DC_SIO_MII_DIR		0x00040000	/* MDIO dir */
+#define	DC_SIO_MII_DATAIN	0x00080000	/* MDIO data in */
+
+#define	DC_EECMD_WRITE		0x140
+#define	DC_EECMD_READ		0x180
+#define	DC_EECMD_ERASE		0x1c0
 
-#define DC_EE_NODEADDR_OFFSET	0x70
-#define DC_EE_NODEADDR		10
+#define	DC_EE_NODEADDR_OFFSET	0x70
+#define	DC_EE_NODEADDR		10
 
 /*
  * General purpose timer register
  */
-#define DC_TIMER_VALUE		0x0000FFFF
-#define DC_TIMER_CONTINUOUS	0x00010000
+#define	DC_TIMER_VALUE		0x0000FFFF
+#define	DC_TIMER_CONTINUOUS	0x00010000
 
 /*
  * 10baseT status register
  */
-#define DC_TSTAT_MIIACT		0x00000001 /* MII port activity */
-#define DC_TSTAT_LS100		0x00000002 /* link status of 100baseTX */
-#define DC_TSTAT_LS10		0x00000004 /* link status of 10baseT */
-#define DC_TSTAT_AUTOPOLARITY	0x00000008
-#define DC_TSTAT_AUIACT		0x00000100 /* AUI activity */
-#define DC_TSTAT_10BTACT	0x00000200 /* 10baseT activity */
-#define DC_TSTAT_NSN		0x00000400 /* non-stable FLPs detected */
-#define DC_TSTAT_REMFAULT	0x00000800
-#define DC_TSTAT_ANEGSTAT	0x00007000
-#define DC_TSTAT_LP_CAN_NWAY	0x00008000 /* link partner supports NWAY */
-#define DC_TSTAT_LPCODEWORD	0xFFFF0000 /* link partner's code word */
-
-#define DC_ASTAT_DISABLE	0x00000000
-#define DC_ASTAT_TXDISABLE	0x00001000
-#define DC_ASTAT_ABDETECT	0x00002000
-#define DC_ASTAT_ACKDETECT	0x00003000
-#define DC_ASTAT_CMPACKDETECT	0x00004000
-#define DC_ASTAT_AUTONEGCMP	0x00005000
-#define DC_ASTAT_LINKCHECK	0x00006000
+#define	DC_TSTAT_MIIACT		0x00000001 /* MII port activity */
+#define	DC_TSTAT_LS100		0x00000002 /* link status of 100baseTX */
+#define	DC_TSTAT_LS10		0x00000004 /* link status of 10baseT */
+#define	DC_TSTAT_AUTOPOLARITY	0x00000008
+#define	DC_TSTAT_AUIACT		0x00000100 /* AUI activity */
+#define	DC_TSTAT_10BTACT	0x00000200 /* 10baseT activity */
+#define	DC_TSTAT_NSN		0x00000400 /* non-stable FLPs detected */
+#define	DC_TSTAT_REMFAULT	0x00000800
+#define	DC_TSTAT_ANEGSTAT	0x00007000
+#define	DC_TSTAT_LP_CAN_NWAY	0x00008000 /* link partner supports NWAY */
+#define	DC_TSTAT_LPCODEWORD	0xFFFF0000 /* link partner's code word */
+
+#define	DC_ASTAT_DISABLE	0x00000000
+#define	DC_ASTAT_TXDISABLE	0x00001000
+#define	DC_ASTAT_ABDETECT	0x00002000
+#define	DC_ASTAT_ACKDETECT	0x00003000
+#define	DC_ASTAT_CMPACKDETECT	0x00004000
+#define	DC_ASTAT_AUTONEGCMP	0x00005000
+#define	DC_ASTAT_LINKCHECK	0x00006000
 
 /*
  * PHY reset register
  */
-#define DC_SIA_RESET		0x00000001
-#define DC_SIA_AUI		0x00000008 /* AUI or 10baseT */
+#define	DC_SIA_RESET		0x00000001
+#define	DC_SIA_AUI		0x00000008 /* AUI or 10baseT */
 
 /*
  * 10baseT control register
  */
-#define DC_TCTL_ENCODER_ENB	0x00000001
-#define DC_TCTL_LOOPBACK	0x00000002
-#define DC_TCTL_DRIVER_ENB	0x00000004
-#define DC_TCTL_LNKPULSE_ENB	0x00000008
-#define DC_TCTL_HALFDUPLEX	0x00000040
-#define DC_TCTL_AUTONEGENBL	0x00000080
-#define DC_TCTL_RX_SQUELCH	0x00000100
-#define DC_TCTL_COLL_SQUELCH	0x00000200
-#define DC_TCTL_COLL_DETECT	0x00000400
-#define DC_TCTL_SQE_ENB		0x00000800
-#define DC_TCTL_LINKTEST	0x00001000
-#define DC_TCTL_AUTOPOLARITY	0x00002000
-#define DC_TCTL_SET_POL_PLUS	0x00004000
-#define DC_TCTL_AUTOSENSE	0x00008000	/* 10bt/AUI autosense */
-#define DC_TCTL_100BTXHALF	0x00010000
-#define DC_TCTL_100BTXFULL	0x00020000
-#define DC_TCTL_100BT4		0x00040000
+#define	DC_TCTL_ENCODER_ENB	0x00000001
+#define	DC_TCTL_LOOPBACK	0x00000002
+#define	DC_TCTL_DRIVER_ENB	0x00000004
+#define	DC_TCTL_LNKPULSE_ENB	0x00000008
+#define	DC_TCTL_HALFDUPLEX	0x00000040
+#define	DC_TCTL_AUTONEGENBL	0x00000080
+#define	DC_TCTL_RX_SQUELCH	0x00000100
+#define	DC_TCTL_COLL_SQUELCH	0x00000200
+#define	DC_TCTL_COLL_DETECT	0x00000400
+#define	DC_TCTL_SQE_ENB		0x00000800
+#define	DC_TCTL_LINKTEST	0x00001000
+#define	DC_TCTL_AUTOPOLARITY	0x00002000
+#define	DC_TCTL_SET_POL_PLUS	0x00004000
+#define	DC_TCTL_AUTOSENSE	0x00008000	/* 10bt/AUI autosense */
+#define	DC_TCTL_100BTXHALF	0x00010000
+#define	DC_TCTL_100BTXFULL	0x00020000
+#define	DC_TCTL_100BT4		0x00040000
 
 /*
  * Watchdog timer register
  */
-#define DC_WDOG_JABBERDIS	0x00000001
-#define DC_WDOG_HOSTUNJAB	0x00000002
-#define DC_WDOG_JABBERCLK	0x00000004
-#define DC_WDOG_RXWDOGDIS	0x00000010
-#define DC_WDOG_RXWDOGCLK	0x00000020
-#define DC_WDOG_MUSTBEZERO	0x00000100
-#define DC_WDOG_AUIBNC		0x00100000
-#define DC_WDOG_ACTIVITY	0x00200000
-#define DC_WDOG_RX_MATCH	0x00400000
-#define DC_WDOG_LINK		0x00800000
-#define DC_WDOG_CTLWREN		0x08000000
+#define	DC_WDOG_JABBERDIS	0x00000001
+#define	DC_WDOG_HOSTUNJAB	0x00000002
+#define	DC_WDOG_JABBERCLK	0x00000004
+#define	DC_WDOG_RXWDOGDIS	0x00000010
+#define	DC_WDOG_RXWDOGCLK	0x00000020
+#define	DC_WDOG_MUSTBEZERO	0x00000100
+#define	DC_WDOG_AUIBNC		0x00100000
+#define	DC_WDOG_ACTIVITY	0x00200000
+#define	DC_WDOG_RX_MATCH	0x00400000
+#define	DC_WDOG_LINK		0x00800000
+#define	DC_WDOG_CTLWREN		0x08000000
 
 /*
  * SIA and General Purpose Port register (X3201)
  */
-#define DC_SIAGP_RXMATCH	0x40000000
-#define DC_SIAGP_INT1		0x20000000
-#define DC_SIAGP_INT0		0x10000000
-#define DC_SIAGP_WRITE_EN	0x08000000
-#define DC_SIAGP_RXMATCH_EN	0x04000000
-#define DC_SIAGP_INT1_EN	0x02000000
-#define DC_SIAGP_INT0_EN	0x01000000
-#define DC_SIAGP_LED3		0x00800000
-#define DC_SIAGP_LED2		0x00400000
-#define DC_SIAGP_LED1		0x00200000
-#define DC_SIAGP_LED0		0x00100000
-#define DC_SIAGP_MD_GP3_OUTPUT	0x00080000
-#define DC_SIAGP_MD_GP2_OUTPUT	0x00040000
-#define DC_SIAGP_MD_GP1_OUTPUT	0x00020000
-#define DC_SIAGP_MD_GP0_OUTPUT	0x00010000
+#define	DC_SIAGP_RXMATCH	0x40000000
+#define	DC_SIAGP_INT1		0x20000000
+#define	DC_SIAGP_INT0		0x10000000
+#define	DC_SIAGP_WRITE_EN	0x08000000
+#define	DC_SIAGP_RXMATCH_EN	0x04000000
+#define	DC_SIAGP_INT1_EN	0x02000000
+#define	DC_SIAGP_INT0_EN	0x01000000
+#define	DC_SIAGP_LED3		0x00800000
+#define	DC_SIAGP_LED2		0x00400000
+#define	DC_SIAGP_LED1		0x00200000
+#define	DC_SIAGP_LED0		0x00100000
+#define	DC_SIAGP_MD_GP3_OUTPUT	0x00080000
+#define	DC_SIAGP_MD_GP2_OUTPUT	0x00040000
+#define	DC_SIAGP_MD_GP1_OUTPUT	0x00020000
+#define	DC_SIAGP_MD_GP0_OUTPUT	0x00010000
 
 /*
  * Size of a setup frame.
  */
-#define DC_SFRAME_LEN		192
+#define	DC_SFRAME_LEN		192
 
 /*
  * 21x4x TX/RX list structure.
  */
 
 struct dc_desc {

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***


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