svn commit: r202420 - in stable/7/sys: conf sparc64/pci
Marius Strobl
marius at FreeBSD.org
Fri Jan 15 21:45:56 UTC 2010
Author: marius
Date: Fri Jan 15 21:45:55 2010
New Revision: 202420
URL: http://svn.freebsd.org/changeset/base/202420
Log:
MFC: r201052, r201200, r202003, r202010, r202023
Add a driver for the `Fire' JBus to PCIe bridges found in at least
the Sun Fire V215/V245 and Sun Ultra 25/45 machines. This driver also
already includes all the code to support the `Oberon' Uranus to PCIe
bridges found in the Fujitsu-Siemens based Mx000 machines but due to
lack of access to such a system for testing, probing of these bridges
is currently disabled.
Unfortunately, the event queue mechanism of these bridges for MSIs/
MSI-Xs matches our current MD and MI interrupt frameworks like square
pegs fit into round holes so for now we are generous and use one event
queue per MSI, which limits us to 35 MSIs/MSI-Xs per Host-PCIe-bridge
(we use one event queue for the PCIe error messages). This seems
tolerable as long as most devices just use one MSI/MSI-X anyway.
Adding knowledge about MSIs/MSI-Xs to the MD interrupt code should
allow us to decouple the 1:1 mapping at the cost of no longer being
able to bind MSIs/MSI-Xs to specific CPUs as we currently have no
reliable way to quiesce a device during the transition of its MSIs/
MSI-Xs to another event queue. This would still require the problem
of interrupt storms generated by devices which have no one-shot
behavior or can't/don't mask interrupts while the filter/handler is
executed (like the older PCIe NICs supported by bge(4)) to be solved
though.
Added:
stable/7/sys/sparc64/pci/fire.c
- copied, changed from r201052, head/sys/sparc64/pci/fire.c
stable/7/sys/sparc64/pci/firereg.h
- copied unchanged from r201052, head/sys/sparc64/pci/firereg.h
stable/7/sys/sparc64/pci/firevar.h
- copied unchanged from r201052, head/sys/sparc64/pci/firevar.h
Modified:
stable/7/sys/conf/files.sparc64
stable/7/sys/conf/options.sparc64
Directory Properties:
stable/7/sys/ (props changed)
stable/7/sys/cddl/contrib/opensolaris/ (props changed)
stable/7/sys/contrib/dev/acpica/ (props changed)
stable/7/sys/contrib/pf/ (props changed)
Modified: stable/7/sys/conf/files.sparc64
==============================================================================
--- stable/7/sys/conf/files.sparc64 Fri Jan 15 21:45:46 2010 (r202419)
+++ stable/7/sys/conf/files.sparc64 Fri Jan 15 21:45:55 2010 (r202420)
@@ -71,6 +71,7 @@ sparc64/isa/isa.c optional isa
sparc64/isa/isa_dma.c optional isa
sparc64/isa/ofw_isa.c optional ebus | isa
sparc64/pci/apb.c optional pci
+sparc64/pci/fire.c optional pci
sparc64/pci/ofw_pcib.c optional pci
sparc64/pci/ofw_pcib_subr.c optional pci
sparc64/pci/ofw_pcibus.c optional pci
Modified: stable/7/sys/conf/options.sparc64
==============================================================================
--- stable/7/sys/conf/options.sparc64 Fri Jan 15 21:45:46 2010 (r202419)
+++ stable/7/sys/conf/options.sparc64 Fri Jan 15 21:45:55 2010 (r202420)
@@ -8,6 +8,8 @@ SUN4U opt_global.h
ATKBD_DFLT_KEYMAP opt_atkbd.h
+FIRE_DEBUG opt_fire.h
+
# Debug IOMMU inserts/removes using diagnostic accesses. This is very loud.
IOMMU_DIAG opt_iommu.h
Copied and modified: stable/7/sys/sparc64/pci/fire.c (from r201052, head/sys/sparc64/pci/fire.c)
==============================================================================
--- head/sys/sparc64/pci/fire.c Sun Dec 27 16:55:44 2009 (r201052, copy source)
+++ stable/7/sys/sparc64/pci/fire.c Fri Jan 15 21:45:55 2010 (r202420)
@@ -83,6 +83,8 @@ __FBSDID("$FreeBSD$");
#include "pcib_if.h"
+struct fire_msiqarg;
+
static bus_space_tag_t fire_alloc_bus_tag(struct fire_softc *sc, int type);
static const struct fire_desc *fire_get_desc(device_t dev);
static void fire_dmamap_sync(bus_dma_tag_t dt __unused, bus_dmamap_t map,
@@ -94,6 +96,9 @@ static void fire_intr_clear(void *arg);
static void fire_intr_disable(void *arg);
static void fire_intr_enable(void *arg);
static int fire_intr_register(struct fire_softc *sc, u_int ino);
+static inline void fire_msiq_common(struct intr_vector *iv,
+ struct fire_msiqarg *fmqa);
+static void fire_msiq_filter(void *cookie);
static void fire_msiq_handler(void *cookie);
static void fire_set_intr(struct fire_softc *sc, u_int index, u_int ino,
driver_filter_t handler, void *arg);
@@ -167,8 +172,7 @@ static device_method_t fire_methods[] =
static devclass_t fire_devclass;
DEFINE_CLASS_0(pcib, fire_driver, fire_methods, sizeof(struct fire_softc));
-EARLY_DRIVER_MODULE(fire, nexus, fire_driver, fire_devclass, 0, 0,
- BUS_PASS_BUS);
+DRIVER_MODULE(fire, nexus, fire_driver, fire_devclass, 0, 0);
MODULE_DEPEND(fire, nexus, 1, 1, 1);
static const struct intr_controller fire_ic = {
@@ -184,6 +188,13 @@ struct fire_icarg {
bus_addr_t fica_clr;
};
+static const struct intr_controller fire_msiqc_filter = {
+ fire_intr_enable,
+ fire_intr_disable,
+ fire_intr_assign,
+ NULL
+};
+
struct fire_msiqarg {
struct fire_icarg fmqa_fica;
struct mtx fmqa_mtx;
@@ -290,7 +301,7 @@ fire_attach(device_t dev)
uint64_t ino_bitmap, val;
phandle_t node;
uint32_t prop, prop_array[2];
- int i, j, mode, nrange;
+ int i, j, mode;
u_int lw;
uint16_t mps;
@@ -725,13 +736,12 @@ fire_attach(device_t dev)
rman_manage_region(&sc->sc_pci_mem_rman, 0, FO_MEM_SIZE) != 0)
panic("%s: failed to set up memory rman", __func__);
- nrange = OF_getprop_alloc(node, "ranges", sizeof(*range),
- (void **)&range);
+ i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
/*
* Make sure that the expected ranges are present. The
* OFW_PCI_CS_MEM64 one is not currently used though.
*/
- if (nrange != FIRE_NRANGE)
+ if (i != FIRE_NRANGE)
panic("%s: unsupported number of ranges", __func__);
/*
* Find the addresses of the various bus spaces.
@@ -743,7 +753,7 @@ fire_attach(device_t dev)
j = OFW_PCI_RANGE_CS(&range[i]);
if (sc->sc_pci_bh[j] != 0)
panic("%s: duplicate range for space %d",
- __func__, j);
+ __func__, j);
sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
}
free(range, M_OFWPROP);
@@ -1612,7 +1622,7 @@ fire_intr_clear(void *arg)
*/
static int
-fire_alloc_msi(device_t dev, device_t child, int count, int maxcount,
+fire_alloc_msi(device_t dev, device_t child, int count, int maxcount __unused,
int *irqs)
{
struct fire_softc *sc;
@@ -1638,16 +1648,11 @@ fire_alloc_msi(device_t dev, device_t ch
mtx_unlock(&sc->sc_msi_mtx);
return (ENXIO);
}
- /*
- * It's unclear whether we need to actually align the MSIs in the
- * mapping table based on the maxcount or just the count. We use
- * maxcount to be on the safe side.
- */
- for (i = 0; i + maxcount < sc->sc_msi_count; i += maxcount) {
- for (j = i; j < i + maxcount; j++)
+ for (i = 0; i + count < sc->sc_msi_count; i += count) {
+ for (j = i; j < i + count; j++)
if (isclr(sc->sc_msi_bitmap, j) == 0)
break;
- if (j == i + maxcount) {
+ if (j == i + count) {
for (j = 0; j < count; j++) {
setbit(sc->sc_msiq_bitmap, msiqrun + j);
setbit(sc->sc_msi_bitmap, i + j);
@@ -1766,33 +1771,67 @@ fire_msiq_handler(void *cookie)
{
struct intr_vector *iv;
struct fire_msiqarg *fmqa;
- struct fire_softc *sc;
- struct fo_msiq_record *qrec;
- device_t dev;
- uint64_t word0;
- u_int head, msi, msiq;
iv = cookie;
fmqa = iv->iv_icarg;
- sc = fmqa->fmqa_fica.fica_sc;
- dev = sc->sc_dev;
- msiq = fmqa->fmqa_msiq;
/*
* Note that since fire_intr_clear() will clear the event queue
- * interrupt after the filter/handler associated with the MSI [sic]
- * has been executed we have to protect the access to the event queue
- * as otherwise nested event queue interrupts cause corruption of the
+ * interrupt after the handler associated with the MSI [sic] has
+ * been executed we have to protect the access to the event queue as
+ * otherwise nested event queue interrupts cause corruption of the
* event queue on MP machines. Obviously especially when abandoning
* the 1:1 mapping it would be better to not clear the event queue
- * interrupt after each filter/handler invocation but only once when
- * the outstanding MSIs have been processed but unfortunately that
+ * interrupt after each handler invocation but only once when the
+ * outstanding MSIs have been processed but unfortunately that
* doesn't work well and leads to interrupt storms with controllers/
- * drivers which don't mask interrupts while the filter/handler is
- * executed. Maybe delaying clearing the MSI until after the filter/
- * handler has been executed could be used to work around this but
- * that's not the intended usage and might in turn cause lost MSIs.
+ * drivers which don't mask interrupts while the handler is executed.
+ * Maybe delaying clearing the MSI until after the handler has been
+ * executed could be used to work around this but that's not the
+ * intended usage and might in turn cause lost MSIs.
*/
mtx_lock_spin(&fmqa->fmqa_mtx);
+ fire_msiq_common(iv, fmqa);
+ mtx_unlock_spin(&fmqa->fmqa_mtx);
+}
+
+static void
+fire_msiq_filter(void *cookie)
+{
+ struct intr_vector *iv;
+ struct fire_msiqarg *fmqa;
+
+ iv = cookie;
+ fmqa = iv->iv_icarg;
+ /*
+ * For filters we don't use fire_intr_clear() since it would clear
+ * the event queue interrupt while we're still processing the event
+ * queue as filters and associated post-filter handler are executed
+ * directly, which in turn would lead to lost MSIs. So we clear the
+ * event queue interrupt only once after processing the event queue.
+ * Given that this still guarantees the filters to not be executed
+ * concurrently and no other CPU can clear the event queue interrupt
+ * while the event queue is still processed, we don't even need to
+ * interlock the access to the event queue in this case.
+ */
+ critical_enter();
+ fire_msiq_common(iv, fmqa);
+ FIRE_PCI_WRITE_8(fmqa->fmqa_fica.fica_sc, fmqa->fmqa_fica.fica_clr,
+ INTCLR_IDLE);
+ critical_exit();
+}
+
+static inline void
+fire_msiq_common(struct intr_vector *iv, struct fire_msiqarg *fmqa)
+{
+ struct fire_softc *sc;
+ struct fo_msiq_record *qrec;
+ device_t dev;
+ uint64_t word0;
+ u_int head, msi, msiq;
+
+ sc = fmqa->fmqa_fica.fica_sc;
+ dev = sc->sc_dev;
+ msiq = fmqa->fmqa_msiq;
head = (FIRE_PCI_READ_8(sc, fmqa->fmqa_head) & FO_PCI_EQ_HD_MASK) >>
FO_PCI_EQ_HD_SHFT;
qrec = &fmqa->fmqa_base[head];
@@ -1834,7 +1873,6 @@ fire_msiq_handler(void *cookie)
FIRE_PCI_READ_8(sc, FO_PCI_EQ_CTRL_CLR_BASE + msiq) |
FO_PCI_EQ_CTRL_CLR_COVERR);
}
- mtx_unlock_spin(&fmqa->fmqa_mtx);
}
static int
@@ -1843,6 +1881,7 @@ fire_setup_intr(device_t dev, device_t c
void **cookiep)
{
struct fire_softc *sc;
+ struct fire_msiqarg *fmqa;
u_long vec;
int error;
u_int msi, msiq;
@@ -1873,31 +1912,39 @@ fire_setup_intr(device_t dev, device_t c
intr, arg, cookiep);
rman_set_start(ires, msi);
rman_set_end(ires, msi);
- if (error == 0) {
+ if (error != 0)
+ return (error);
+ fmqa = intr_vectors[vec].iv_icarg;
+ /*
+ * XXX inject our event queue handler.
+ */
+ if (filt != NULL) {
+ intr_vectors[vec].iv_func = fire_msiq_filter;
+ intr_vectors[vec].iv_ic = &fire_msiqc_filter;
/*
- * XXX inject our event queue handler.
+ * Ensure the event queue interrupt is cleared, it
+ * might have triggered before. Given we supply NULL
+ * as ic_clear, inthand_add() won't do this for us.
*/
+ FIRE_PCI_WRITE_8(sc, fmqa->fmqa_fica.fica_clr,
+ INTCLR_IDLE);
+ } else
intr_vectors[vec].iv_func = fire_msiq_handler;
- /*
- * Record the MSI/MSI-X as long as we we use a 1:1
- * mapping.
- */
- ((struct fire_msiqarg *)intr_vectors[vec].iv_icarg)->
- fmqa_msi = msi;
- FIRE_PCI_WRITE_8(sc, FO_PCI_EQ_CTRL_SET_BASE +
- (msiq << 3), FO_PCI_EQ_CTRL_SET_EN);
- msi <<= 3;
- FIRE_PCI_WRITE_8(sc, FO_PCI_MSI_MAP_BASE + msi,
- (FIRE_PCI_READ_8(sc, FO_PCI_MSI_MAP_BASE + msi) &
- ~FO_PCI_MSI_MAP_EQNUM_MASK) |
- ((msiq << FO_PCI_MSI_MAP_EQNUM_SHFT) &
- FO_PCI_MSI_MAP_EQNUM_MASK));
- FIRE_PCI_WRITE_8(sc, FO_PCI_MSI_CLR_BASE + msi,
- FO_PCI_MSI_CLR_EQWR_N);
- FIRE_PCI_WRITE_8(sc, FO_PCI_MSI_MAP_BASE + msi,
- FIRE_PCI_READ_8(sc, FO_PCI_MSI_MAP_BASE + msi) |
- FO_PCI_MSI_MAP_V);
- }
+ /* Record the MSI/MSI-X as long as we we use a 1:1 mapping. */
+ fmqa->fmqa_msi = msi;
+ FIRE_PCI_WRITE_8(sc, FO_PCI_EQ_CTRL_SET_BASE + (msiq << 3),
+ FO_PCI_EQ_CTRL_SET_EN);
+ msi <<= 3;
+ FIRE_PCI_WRITE_8(sc, FO_PCI_MSI_MAP_BASE + msi,
+ (FIRE_PCI_READ_8(sc, FO_PCI_MSI_MAP_BASE + msi) &
+ ~FO_PCI_MSI_MAP_EQNUM_MASK) |
+ ((msiq << FO_PCI_MSI_MAP_EQNUM_SHFT) &
+ FO_PCI_MSI_MAP_EQNUM_MASK));
+ FIRE_PCI_WRITE_8(sc, FO_PCI_MSI_CLR_BASE + msi,
+ FO_PCI_MSI_CLR_EQWR_N);
+ FIRE_PCI_WRITE_8(sc, FO_PCI_MSI_MAP_BASE + msi,
+ FIRE_PCI_READ_8(sc, FO_PCI_MSI_MAP_BASE + msi) |
+ FO_PCI_MSI_MAP_V);
return (error);
}
@@ -1946,14 +1993,16 @@ fire_teardown_intr(device_t dev, device_
(0 << FO_PCI_EQ_TL_SHFT) & FO_PCI_EQ_TL_MASK);
FIRE_PCI_WRITE_8(sc, FO_PCI_EQ_HD_BASE + msiq,
(0 << FO_PCI_EQ_HD_SHFT) & FO_PCI_EQ_HD_MASK);
+ intr_vectors[vec].iv_ic = &fire_ic;
/*
* The MD interrupt code needs the vector rather than the MSI.
*/
rman_set_start(ires, vec);
rman_set_end(ires, vec);
error = bus_generic_teardown_intr(dev, child, ires, cookie);
+ msi >>= 3;
rman_set_start(ires, msi);
- rman_set_end(ires, msi >> 3);
+ rman_set_end(ires, msi);
return (error);
}
return (bus_generic_teardown_intr(dev, child, ires, cookie));
@@ -2101,7 +2150,7 @@ fire_alloc_bus_tag(struct fire_softc *sc
{
bus_space_tag_t bt;
- bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF,
+ bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF,
M_NOWAIT | M_ZERO);
if (bt == NULL)
panic("%s: out of memory", __func__);
Copied: stable/7/sys/sparc64/pci/firereg.h (from r201052, head/sys/sparc64/pci/firereg.h)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ stable/7/sys/sparc64/pci/firereg.h Fri Jan 15 21:45:55 2010 (r202420, copy of r201052, head/sys/sparc64/pci/firereg.h)
@@ -0,0 +1,1004 @@
+/*-
+ * Copyright (c) 2009 Marius Strobl <marius at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _SPARC64_PCI_FIREREG_H_
+#define _SPARC64_PCI_FIREREG_H_
+
+#define FIRE_NINTR 3 /* 2 OFW + 1 MSIq */
+#define FIRE_NRANGE 4
+#define FIRE_NREG 2
+
+#define FIRE_PCI 0
+#define FIRE_CTRL 1
+
+/* PCI configuration and status registers */
+#define FO_PCI_INT_MAP_BASE 0x01000
+#define FO_PCI_INT_CLR_BASE 0x01400
+#define FO_PCI_EQ_BASE_ADDR 0x10000
+#define FO_PCI_EQ_CTRL_SET_BASE 0x11000
+#define FO_PCI_EQ_CTRL_CLR_BASE 0x11200
+#define FO_PCI_EQ_TL_BASE 0x11600
+#define FO_PCI_EQ_HD_BASE 0x11800
+#define FO_PCI_MSI_MAP_BASE 0x20000
+#define FO_PCI_MSI_CLR_BASE 0x28000
+#define FO_PCI_ERR_COR 0x30000
+#define FO_PCI_ERR_NONFATAL 0x30008
+#define FO_PCI_ERR_FATAL 0x30010
+#define FO_PCI_PM_PME 0x30018
+#define FO_PCI_PME_TO_ACK 0x30020
+#define FO_PCI_IMU_INT_EN 0x31008
+#define FO_PCI_IMU_INT_STAT 0x31010
+#define FO_PCI_IMU_ERR_STAT_CLR 0x31018
+#define FO_PCI_IMU_RDS_ERR_LOG 0x31028
+#define FO_PCI_IMU_SCS_ERR_LOG 0x31030
+#define FO_PCI_IMU_EQS_ERR_LOG 0x31038
+#define FO_PCI_DMC_CORE_BLOCK_INT_EN 0x31800
+#define FO_PCI_DMC_CORE_BLOCK_ERR_STAT 0x31808
+#define FO_PCI_MULTI_CORE_ERR_STAT 0x31810
+#define FO_PCI_MSI_32_BIT_ADDR 0x34000
+#define FO_PCI_MSI_64_BIT_ADDR 0x34008
+#define FO_PCI_MMU 0x40000
+#define FO_PCI_MMU_INT_EN 0x41008
+#define FO_PCI_MMU_INT_STAT 0x41010
+#define FO_PCI_MMU_ERR_STAT_CLR 0x41018
+#define FO_PCI_MMU_TRANS_FAULT_ADDR 0x41028
+#define FO_PCI_MMU_TRANS_FAULT_STAT 0x41030
+#define FO_PCI_ILU_INT_EN 0x51008
+#define FO_PCI_ILU_INT_STAT 0x51010
+#define FO_PCI_ILU_ERR_STAT_CLR 0x51018
+#define FO_PCI_DMC_DBG_SEL_PORTA 0x53000
+#define FO_PCI_DMC_DBG_SEL_PORTB 0x53008
+#define FO_PCI_PEC_CORE_BLOCK_INT_EN 0x51800
+#define FO_PCI_PEC_CORE_BLOCK_INT_STAT 0x51808
+#define FO_PCI_TLU_CTRL 0x80000
+#define FO_PCI_TLU_OEVENT_INT_EN 0x81008
+#define FO_PCI_TLU_OEVENT_INT_STAT 0x81010
+#define FO_PCI_TLU_OEVENT_STAT_CLR 0x81018
+#define FO_PCI_TLU_RX_OEVENT_HDR1_LOG 0x81028
+#define FO_PCI_TLU_RX_OEVENT_HDR2_LOG 0x81030
+#define FO_PCI_TLU_TX_OEVENT_HDR1_LOG 0x81038
+#define FO_PCI_TLU_TX_OEVENT_HDR2_LOG 0x81040
+#define FO_PCI_TLU_DEV_CTRL 0x90008
+#define FO_PCI_TLU_LNK_CTRL 0x90020
+#define FO_PCI_TLU_LNK_STAT 0x90028
+#define FO_PCI_TLU_UERR_INT_EN 0x91008
+#define FO_PCI_TLU_UERR_INT_STAT 0x91010
+#define FO_PCI_TLU_UERR_STAT_CLR 0x91018
+#define FO_PCI_TLU_RX_UERR_HDR1_LOG 0x91028
+#define FO_PCI_TLU_RX_UERR_HDR2_LOG 0x91030
+#define FO_PCI_TLU_TX_UERR_HDR1_LOG 0x91038
+#define FO_PCI_TLU_TX_UERR_HDR2_LOG 0x91040
+#define FO_PCI_TLU_CERR_INT_EN 0xa1008
+#define FO_PCI_TLU_CERR_INT_STAT 0xa1010
+#define FO_PCI_TLU_CERR_STAT_CLR 0xa1018
+#define FO_PCI_LPU_RST 0xe2008
+#define FO_PCI_LPU_INT_STAT 0xe2040
+#define FO_PCI_LPU_INT_MASK 0xe0248
+#define FO_PCI_LPU_LNK_LYR_CFG 0xe2200
+#define FO_PCI_LPU_LNK_LYR_INT_STAT 0xe2210
+#define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL 0xe2240
+#define FO_PCI_LPU_TXLNK_FREQ_LAT_TMR_THRS 0xe2400
+#define FO_PCI_LPU_TXLNK_RPLY_TMR_THRS 0xe2410
+#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR 0xe2430
+#define FO_PCI_LPU_PHY_LYR_INT_STAT 0xe2610
+#define FO_PCI_LPU_LTSSM_CFG2 0xe2788
+#define FO_PCI_LPU_LTSSM_CFG3 0xe2790
+#define FO_PCI_LPU_LTSSM_CFG4 0xe2798
+#define FO_PCI_LPU_LTSSM_CFG5 0xe27a0
+
+/* PCI interrupt mapping registers */
+#define FO_PCI_IMAP_MDO_MODE 0x8000000000000000ULL
+#define FO_PCI_IMAP_V 0x0000000080000000ULL
+#define FIRE_PCI_IMAP_T_JPID_MASK 0x000000007c000000ULL
+#define FIRE_PCI_IMAP_T_JPID_SHFT 26
+#define OBERON_PCI_IMAP_T_DESTID_MASK 0x000000007fe00000ULL
+#define OBERON_PCI_IMAP_T_DESTID_SHFT 21
+#define FO_PCI_IMAP_INT_CTRL_NUM_MASK 0x00000000000003c0ULL
+#define FO_PCI_IMAP_INT_CTRL_NUM_SHFT 6
+
+/* PCI interrupt clear registers - use INTCLR_* from <machine/bus_common.h> */
+
+/* PCI event queue base address register */
+#define FO_PCI_EQ_BASE_ADDR_BYPASS 0xfffc000000000000ULL
+#define FO_PCI_EQ_BASE_ADDR_MASK 0xfffffffffff80000ULL
+#define FO_PCI_EQ_BASE_ADDR_SHFT 19
+
+/* PCI event queue control set registers */
+#define FO_PCI_EQ_CTRL_SET_ENOVERR 0x0200000000000000ULL
+#define FO_PCI_EQ_CTRL_SET_EN 0x0000100000000000ULL
+
+/* PCI event queue control clear registers */
+#define FO_PCI_EQ_CTRL_CLR_COVERR 0x0200000000000000ULL
+#define FO_PCI_EQ_CTRL_CLR_E2I 0x0000800000000000ULL
+#define FO_PCI_EQ_CTRL_CLR_DIS 0x0000100000000000ULL
+
+/* PCI event queue tail registers */
+#define FO_PCI_EQ_TL_OVERR 0x0200000000000000ULL
+#define FO_PCI_EQ_TL_MASK 0x000000000000007fULL
+#define FO_PCI_EQ_TL_SHFT 0
+
+/* PCI event queue head registers */
+#define FO_PCI_EQ_HD_MASK 0x000000000000007fULL
+#define FO_PCI_EQ_HD_SHFT 0
+
+/* PCI MSI mapping registers */
+#define FO_PCI_MSI_MAP_V 0x8000000000000000ULL
+#define FO_PCI_MSI_MAP_EQWR_N 0x4000000000000000ULL
+#define FO_PCI_MSI_MAP_EQNUM_MASK 0x000000000000003fULL
+#define FO_PCI_MSI_MAP_EQNUM_SHFT 0
+
+/* PCI MSI clear registers */
+#define FO_PCI_MSI_CLR_EQWR_N 0x4000000000000000ULL
+
+/*
+ * PCI IMU interrupt enable, interrupt status and error status clear
+ * registers
+ */
+#define FO_PCI_IMU_ERR_INT_SPARE_S_MASK 0x00007c0000000000ULL
+#define FO_PCI_IMU_ERR_INT_SPARE_S_SHFT 42
+#define FO_PCI_IMU_ERR_INT_EQ_OVER_S 0x0000020000000000ULL
+#define FO_PCI_IMU_ERR_INT_EQ_NOT_EN_S 0x0000010000000000ULL
+#define FO_PCI_IMU_ERR_INT_MSI_MAL_ERR_S 0x0000008000000000ULL
+#define FO_PCI_IMU_ERR_INT_MSI_PAR_ERR_S 0x0000004000000000ULL
+#define FO_PCI_IMU_ERR_INT_PMEACK_MES_NOT_EN_S 0x0000002000000000ULL
+#define FO_PCI_IMU_ERR_INT_PMPME_MES_NOT_EN_S 0x0000001000000000ULL
+#define FO_PCI_IMU_ERR_INT_FATAL_MES_NOT_EN_S 0x0000000800000000ULL
+#define FO_PCI_IMU_ERR_INT_NFATAL_MES_NOT_EN_S 0x0000000400000000ULL
+#define FO_PCI_IMU_ERR_INT_COR_MES_NOT_EN_S 0x0000000200000000ULL
+#define FO_PCI_IMU_ERR_INT_MSI_NOT_EN_S 0x0000000100000000ULL
+#define FO_PCI_IMU_ERR_INT_SPARE_P_MASK 0x0000000000007c00ULL
+#define FO_PCI_IMU_ERR_INT_SPARE_P_SHFT 10
+#define FO_PCI_IMU_ERR_INT_EQ_OVER_P 0x0000000000000200ULL
+#define FO_PCI_IMU_ERR_INT_EQ_NOT_EN_P 0x0000000000000100ULL
+#define FO_PCI_IMU_ERR_INT_MSI_MAL_ERR_P 0x0000000000000080ULL
+#define FO_PCI_IMU_ERR_INT_MSI_PAR_ERR_P 0x0000000000000040ULL
+#define FO_PCI_IMU_ERR_INT_PMEACK_MES_NOT_EN_P 0x0000000000000020ULL
+#define FO_PCI_IMU_ERR_INT_PMPME_MES_NOT_EN_P 0x0000000000000010ULL
+#define FO_PCI_IMU_ERR_INT_FATAL_MES_NOT_EN_P 0x0000000000000008ULL
+#define FO_PCI_IMU_ERR_INT_NFATAL_MES_NOT_EN_P 0x0000000000000004ULL
+#define FO_PCI_IMU_ERR_INT_COR_MES_NOT_EN_P 0x0000000000000002ULL
+#define FO_PCI_IMU_ERR_INT_MSI_NOT_EN_P 0x0000000000000001ULL
+
+/* PCI IMU RDS error log register */
+#define FO_PCI_IMU_RDS_ERR_LOG_TYPE_MASK 0xfc00000000000000ULL
+#define FO_PCI_IMU_RDS_ERR_LOG_TYPE_SHFT 58
+#define FO_PCI_IMU_RDS_ERR_LOG_LENGTH_MASK 0x03ff000000000000ULL
+#define FO_PCI_IMU_RDS_ERR_LOG_LENGTH_SHFT 48
+#define FO_PCI_IMU_RDS_ERR_LOG_REQ_ID_MASK 0x0000ffff00000000ULL
+#define FO_PCI_IMU_RDS_ERR_LOG_REQ_ID_SHFT 32
+#define FO_PCI_IMU_RDS_ERR_LOG_TLP_TAG_MASK 0x00000000ff000000ULL
+#define FO_PCI_IMU_RDS_ERR_LOG_TLP_TAG_SHFT 24
+#define FO_PCI_IMU_RDS_ERR_LOG_BE_MCODE_MASK 0x0000000000ff0000ULL
+#define FO_PCI_IMU_RDS_ERR_LOG_BE_MCODE_SHFT 16
+#define FO_PCI_IMU_RDS_ERR_LOG_MSI_DATA_MASK 0x000000000000ffffULL
+#define FO_PCI_IMU_RDS_ERR_LOG_MSI_DATA_SHFT 0
+
+/* PCI IMU SCS error log register */
+#define FO_PCI_IMU_SCS_ERR_LOG_TYPE_MASK 0xfc00000000000000ULL
+#define FO_PCI_IMU_SCS_ERR_LOG_TYPE_SHFT 58
+#define FO_PCI_IMU_SCS_ERR_LOG_LENGTH_MASK 0x03ff000000000000ULL
+#define FO_PCI_IMU_SCS_ERR_LOG_LENGTH_SHFT 48
+#define FO_PCI_IMU_SCS_ERR_LOG_REQ_ID_MASK 0x0000ffff00000000ULL
+#define FO_PCI_IMU_SCS_ERR_LOG_REQ_ID_SHFT 32
+#define FO_PCI_IMU_SCS_ERR_LOG_TLP_TAG_MASK 0x00000000ff000000ULL
+#define FO_PCI_IMU_SCS_ERR_LOG_TLP_TAG_SHFT 24
+#define FO_PCI_IMU_SCS_ERR_LOG_BE_MODE_MASK 0x0000000000ff0000ULL
+#define FO_PCI_IMU_SCS_ERR_LOG_BE_MCODE_SHFT 16
+#define FO_PCI_IMU_SCS_ERR_LOG_EQ_NUM_MASK 0x000000000000003fULL
+#define FO_PCI_IMU_SCS_ERR_LOG_EQ_NUM_SHFT 0
+
+/* PCI IMU EQS error log register */
+#define FO_PCI_IMU_EQS_ERR_LOG_EQ_NUM_MASK 0x000000000000003fULL
+#define FO_PCI_IMU_EQS_ERROR_LOG_EQ_NUM_SHFT 0
+
+/*
+ * PCI ERR COR, ERR NONFATAL, ERR FATAL, PM PME and PME To ACK mapping
+ * registers
+ */
+#define FO_PCI_ERR_PME_V 0x8000000000000000ULL
+#define FO_PCI_ERR_PME_EQNUM_MASK 0x000000000000003fULL
+#define FO_PCI_ERR_PME_EQNUM_SHFT 0
+
+/* PCI DMC core and block interrupt enable register */
+#define FO_PCI_DMC_CORE_BLOCK_INT_EN_DMC 0x8000000000000000ULL
+#define FO_PCI_DMC_CORE_BLOCK_INT_EN_MMU 0x0000000000000002ULL
+#define FO_PCI_DMC_CORE_BLOCK_INT_EN_IMU 0x0000000000000001ULL
+
+/* PCI DMC core and block error status register */
+#define FO_PCI_DMC_CORE_BLOCK_ERR_STAT_MMU 0x0000000000000002ULL
+#define FO_PCI_DMC_CORE_BLOCK_ERR_STAT_IMU 0x0000000000000001ULL
+
+/* PCI multi core error status register */
+#define FO_PCI_MULTI_CORE_ERR_STAT_PEC 0x0000000000000002ULL
+#define FO_PCI_MULTI_CORE_ERR_STAT_DMC 0x0000000000000001ULL
+
+/* PCI MSI 32-bit address register */
+#define FO_PCI_MSI_32_BIT_ADDR_MASK 0x00000000ffff0000ULL
+#define FO_PCI_MSI_32_BIT_ADDR_SHFT 16
+
+/* PCI MSI 64-bit address register */
+#define FO_PCI_MSI_64_BIT_ADDR_MASK 0x0000ffffffff0000ULL
+#define FO_PCI_MSI_64_BIT_ADDR_SHFT 16
+
+/*
+ * PCI MMU interrupt enable, interrupt status and error status clear
+ * registers
+ */
+#define FO_PCI_MMU_ERR_INT_S_MASK 0x0000ffff00000000ULL
+#define FO_PCI_MMU_ERR_INT_S_SHFT 32
+#define FO_PCI_MMU_ERR_INT_TBW_DPE_S 0x0000800000000000ULL
+#define FO_PCI_MMU_ERR_INT_TBW_ERR_S 0x0000400000000000ULL
+#define FO_PCI_MMU_ERR_INT_TBW_UDE_S 0x0000200000000000ULL
+#define FO_PCI_MMU_ERR_INT_TBW_DME_S 0x0000100000000000ULL
+#define FO_PCI_MMU_ERR_INT_SPARE3_S 0x0000080000000000ULL
+#define FO_PCI_MMU_ERR_INT_SPARE2_S 0x0000040000000000ULL
+#define FO_PCI_MMU_ERR_INT_TTC_CAE_S 0x0000020000000000ULL
+#define FIRE_PCI_MMU_ERR_INT_TTC_DPE_S 0x0000010000000000ULL
+#define OBERON_PCI_MMU_ERR_INT_TTC_DUE_S 0x0000010000000000ULL
+#define FO_PCI_MMU_ERR_INT_TTE_PRT_S 0x0000008000000000ULL
+#define FO_PCI_MMU_ERR_INT_TTE_INV_S 0x0000004000000000ULL
+#define FO_PCI_MMU_ERR_INT_TRN_OOR_S 0x0000002000000000ULL
+#define FO_PCI_MMU_ERR_INT_TRN_ERR_S 0x0000001000000000ULL
+#define FO_PCI_MMU_ERR_INT_SPARE1_S 0x0000000800000000ULL
+#define FO_PCI_MMU_ERR_INT_SPARE0_S 0x0000000400000000ULL
+#define FO_PCI_MMU_ERR_INT_BYP_OOR_S 0x0000000200000000ULL
+#define FO_PCI_MMU_ERR_INT_BYP_ERR_S 0x0000000100000000ULL
+#define FO_PCI_MMU_ERR_INT_P_MASK 0x000000000000ffffULL
+#define FO_PCI_MMU_ERR_INT_P_SHFT 0
+#define FO_PCI_MMU_ERR_INT_TBW_DPE_P 0x0000000000008000ULL
+#define FO_PCI_MMU_ERR_INT_TBW_ERR_P 0x0000000000004000ULL
+#define FO_PCI_MMU_ERR_INT_TBW_UDE_P 0x0000000000002000ULL
+#define FO_PCI_MMU_ERR_INT_TBW_DME_P 0x0000000000001000ULL
+#define FO_PCI_MMU_ERR_INT_SPARE3_P 0x0000000000000800ULL
+#define FO_PCI_MMU_ERR_INT_SPARE2_P 0x0000000000000400ULL
+#define FO_PCI_MMU_ERR_INT_TTC_CAE_P 0x0000000000000200ULL
+#define FIRE_PCI_MMU_ERR_INT_TTC_DPE_P 0x0000000000000100ULL
+#define OBERON_PCI_MMU_ERR_INT_TTC_DUE_P 0x0000000000000100ULL
+#define FO_PCI_MMU_ERR_INT_TTE_PRT_P 0x0000000000000080ULL
+#define FO_PCI_MMU_ERR_INT_TTE_INV_P 0x0000000000000040ULL
+#define FO_PCI_MMU_ERR_INT_TRN_OOR_P 0x0000000000000020ULL
+#define FO_PCI_MMU_ERR_INT_TRN_ERR_P 0x0000000000000010ULL
+#define FO_PCI_MMU_ERR_INT_SPARE1_P 0x0000000000000008ULL
+#define FO_PCI_MMU_ERR_INT_SPARE0_P 0x0000000000000004ULL
+#define FO_PCI_MMU_ERR_INT_BYP_OOR_P 0x0000000000000002ULL
+#define FO_PCI_MMU_ERR_INT_BYP_ERR_P 0x0000000000000001ULL
+
+/* PCI MMU translation fault address register */
+#define FO_PCI_MMU_TRANS_FAULT_ADDR_VA_MASK 0xfffffffffffffffcULL
+#define FO_PCI_MMU_TRANS_FAULT_ADDR_VA_SHFT 2
+
+/* PCI MMU translation fault status register */
+#define FO_PCI_MMU_TRANS_FAULT_STAT_ENTRY_MASK 0x000001ff00000000ULL
+#define FO_PCI_MMU_TRANS_FAULT_STAT_ENTRY_SHFT 32
+#define FO_PCI_MMU_TRANS_FAULT_STAT_TYPE_MASK 0x00000000007f0000ULL
+#define FO_PCI_MMU_TRANS_FAULT_STAT_TYPE_SHFT 16
+#define FO_PCI_MMU_TRANS_FAULT_STAT_ID_MASK 0x000000000000ffffULL
+#define FO_PCI_MMU_TRANS_FAULT_STAT_ID_SHFT 0
+
+/*
+ * PCI ILU interrupt enable, interrupt status and error status clear
+ * registers
+ */
+#define FO_PCI_ILU_ERR_INT_SPARE3_S 0x0000008000000000ULL
+#define FO_PCI_ILU_ERR_INT_SPARE2_S 0x0000004000000000ULL
+#define FO_PCI_ILU_ERR_INT_SPARE1_S 0x0000002000000000ULL
+#define FIRE_PCI_ILU_ERR_INT_IHB_PE_S 0x0000001000000000ULL
+#define OBERON_PCI_ILU_ERR_INT_IHB_UE_S 0x0000001000000000ULL
+#define FO_PCI_ILU_ERR_INT_SPARE3_P 0x0000000000000080ULL
+#define FO_PCI_ILU_ERR_INT_SPARE2_P 0x0000000000000040ULL
+#define FO_PCI_ILU_ERR_INT_SPARE1_P 0x0000000000000020ULL
+#define FIRE_PCI_ILU_ERR_INT_IHB_PE_P 0x0000000000000010ULL
+#define OBERON_PCI_ILU_ERR_INT_IHB_UE_P 0x0000000000000010ULL
+
+/* PCI DMC debug select registers for port a/b */
+#define FO_PCI_DMC_DBG_SEL_PORT_BLCK_MASK 0x00000000000003c0ULL
+#define FO_PCI_DMC_DBG_SEL_PORT_BLCK_SHFT 6
+#define FO_PCI_DMC_DBG_SEL_PORT_SUB_MASK 0x0000000000000038ULL
+#define FO_PCI_DMC_DBG_SEL_PORT_SUB_SHFT 3
+#define FO_PCI_DMC_DBG_SEL_PORT_SUB_SGNL_MASK 0x0000000000000007ULL
+#define FO_PCI_DMC_DBG_SEL_PORT_SUB_SGNL_SHFT 0
+
+/* PCI PEC core and block interrupt enable register */
+#define FO_PCI_PEC_CORE_BLOCK_INT_EN_PEC 0x8000000000000000ULL
+#define FO_PCI_PEC_CORE_BLOCK_INT_EN_ILU 0x0000000000000008ULL
+#define FO_PCI_PEC_CORE_BLOCK_INT_EN_UERR 0x0000000000000004ULL
+#define FO_PCI_PEC_CORE_BLOCK_INT_EN_CERR 0x0000000000000002ULL
+#define FO_PCI_PEC_CORE_BLOCK_INT_EN_OEVENT 0x0000000000000001ULL
+
+/* PCI PEC core and block interrupt status register */
+#define FO_PCI_PEC_CORE_BLOCK_INT_STAT_ILU 0x0000000000000008ULL
+#define FO_PCI_PEC_CORE_BLOCK_INT_STAT_UERR 0x0000000000000004ULL
+#define FO_PCI_PEC_CORE_BLOCK_INT_STAT_CERR 0x0000000000000002ULL
+#define FO_PCI_PEC_CORE_BLOCK_INT_STAT_OEVENT 0x0000000000000001ULL
+
+/* PCI TLU control register */
+#define FO_PCI_TLU_CTRL_L0S_TIM_MASK 0x00000000ff000000ULL
+#define FO_PCI_TLU_CTRL_L0S_TIM_SHFT 24
+#define FO_PCI_TLU_CTRL_NWPR_EN 0x0000000000100000ULL
+#define FO_PCI_TLU_CTRL_CTO_SEL_MASK 0x0000000000070000ULL
+#define FO_PCI_TLU_CTRL_CTO_SEL_SHFT 16
+#define FO_PCI_TLU_CTRL_CFG_MASK 0x000000000000ffffULL
+#define FO_PCI_TLU_CTRL_CFG_SHFT 0
+#define FO_PCI_TLU_CTRL_CFG_REMAIN_DETECT_QUIET 0x0000000000000100ULL
+
+/*
+ * PCI TLU other event interrupt enable, interrupt status and status clear
+ * registers
+ */
+#define FO_PCI_TLU_OEVENT_S_MASK 0x00ffffff00000000ULL
+#define FO_PCI_TLU_OEVENT_S_SHFT 32
+#define FO_PCI_TLU_OEVENT_SPARE_S 0x0080000000000000ULL
+#define FO_PCI_TLU_OEVENT_MFC_S 0x0040000000000000ULL
+#define FO_PCI_TLU_OEVENT_CTO_S 0x0020000000000000ULL
+#define FO_PCI_TLU_OEVENT_NFP_S 0x0010000000000000ULL
+#define FO_PCI_TLU_OEVENT_LWC_S 0x0008000000000000ULL
+#define FO_PCI_TLU_OEVENT_MRC_S 0x0004000000000000ULL
+#define FO_PCI_TLU_OEVENT_WUC_S 0x0002000000000000ULL
+#define FO_PCI_TLU_OEVENT_RUC_S 0x0001000000000000ULL
+#define FO_PCI_TLU_OEVENT_CRS_S 0x0000800000000000ULL
+#define FO_PCI_TLU_OEVENT_IIP_S 0x0000400000000000ULL
+#define FO_PCI_TLU_OEVENT_EDP_S 0x0000200000000000ULL
+#define FIRE_PCI_TLU_OEVENT_EHP_S 0x0000100000000000ULL
+#define OBERON_PCI_TLU_OEVENT_EHBUE_S 0x0000100000000000ULL
+#define OBERON_PCI_TLU_OEVENT_EDBUE_S 0x0000100000000000ULL
+#define FO_PCI_TLU_OEVENT_LIN_S 0x0000080000000000ULL
+#define FO_PCI_TLU_OEVENT_LRS_S 0x0000040000000000ULL
+#define FO_PCI_TLU_OEVENT_LDN_S 0x0000020000000000ULL
+#define FO_PCI_TLU_OEVENT_LUP_S 0x0000010000000000ULL
+#define FO_PCI_TLU_OEVENT_LPU_S_MASK 0x000000c000000000ULL
+#define FO_PCI_TLU_OEVENT_LPU_S_SHFT 38
+#define OBERON_PCI_TLU_OEVENT_TLUEITMO_S 0x0000008000000000ULL
+#define FO_PCI_TLU_OEVENT_ERU_S 0x0000002000000000ULL
+#define FO_PCI_TLU_OEVENT_ERO_S 0x0000001000000000ULL
+#define FO_PCI_TLU_OEVENT_EMP_S 0x0000000800000000ULL
+#define FO_PCI_TLU_OEVENT_EPE_S 0x0000000400000000ULL
+#define FIRE_PCI_TLU_OEVENT_ERP_S 0x0000000200000000ULL
+#define OBERON_PCI_TLU_OEVENT_ERBU_S 0x0000000200000000ULL
+#define FIRE_PCI_TLU_OEVENT_EIP_S 0x0000000100000000ULL
+#define OBERON_PCI_TLU_OEVENT_EIUE_S 0x0000000100000000ULL
+#define FO_PCI_TLU_OEVENT_P_MASK 0x0000000000ffffffULL
+#define FO_PCI_TLU_OEVENT_P_SHFT 0
+#define FO_PCI_TLU_OEVENT_SPARE_P 0x0000000000800000ULL
+#define FO_PCI_TLU_OEVENT_MFC_P 0x0000000000400000ULL
+#define FO_PCI_TLU_OEVENT_CTO_P 0x0000000000200000ULL
+#define FO_PCI_TLU_OEVENT_NFP_P 0x0000000000100000ULL
+#define FO_PCI_TLU_OEVENT_LWC_P 0x0000000000080000ULL
+#define FO_PCI_TLU_OEVENT_MRC_P 0x0000000000040000ULL
+#define FO_PCI_TLU_OEVENT_WUC_P 0x0000000000020000ULL
+#define FO_PCI_TLU_OEVENT_RUC_P 0x0000000000010000ULL
+#define FO_PCI_TLU_OEVENT_CRS_P 0x0000000000008000ULL
+#define FO_PCI_TLU_OEVENT_IIP_P 0x0000000000004000ULL
+#define FO_PCI_TLU_OEVENT_EDP_P 0x0000000000002000ULL
+#define FIRE_PCI_TLU_OEVENT_EHP_P 0x0000000000001000ULL
+#define OBERON_PCI_TLU_OEVENT_EHBUE_P 0x0000000000001000ULL
+#define OBERON_PCI_TLU_OEVENT_EDBUE_P 0x0000000000001000ULL
+#define FO_PCI_TLU_OEVENT_LIN_P 0x0000000000000800ULL
+#define FO_PCI_TLU_OEVENT_LRS_P 0x0000000000000400ULL
+#define FO_PCI_TLU_OEVENT_LDN_P 0x0000000000000200ULL
+#define FO_PCI_TLU_OEVENT_LUP_P 0x0000000000000100ULL
+#define FO_PCI_TLU_OEVENT_LPU_P_MASK 0x00000000000000c0ULL
+#define FO_PCI_TLU_OEVENT_LPU_P_SHFT 6
+#define OBERON_PCI_TLU_OEVENT_TLUEITMO_P 0x0000000000000080ULL
+#define FO_PCI_TLU_OEVENT_ERU_P 0x0000000000000020ULL
+#define FO_PCI_TLU_OEVENT_ERO_P 0x0000000000000010ULL
+#define FO_PCI_TLU_OEVENT_EMP_P 0x0000000000000008ULL
+#define FO_PCI_TLU_OEVENT_EPE_P 0x0000000000000004ULL
+#define FIRE_PCI_TLU_OEVENT_ERP_P 0x0000000000000002ULL
+#define OBERON_PCI_TLU_OEVENT_ERBU_P 0x0000000000000002ULL
+#define FIRE_PCI_TLU_OEVENT_EIP_P 0x0000000000000001ULL
+#define OBERON_PCI_TLU_OEVENT_EIUE_P 0x0000000000000001ULL
+
+/* PCI receive/transmit DLU/TLU other event header 1/2 log registers */
+#define FO_PCI_TLU_OEVENT_HDR_LOG_MASK 0xffffffffffffffffULL
+#define FO_PCI_TLU_OEVENT_HDR_LOG_SHFT 0
+
+/* PCI TLU device control register */
+#define FO_PCI_TLU_DEV_CTRL_MRRS_MASK 0x0000000000007000ULL
+#define FO_PCI_TLU_DEV_CTRL_MRRS_SHFT 12
+#define FO_PCI_TLU_DEV_CTRL_MPS_MASK 0x00000000000000e0ULL
+#define FO_PCI_TLU_DEV_CTRL_MPS_SHFT 5
+
+/*
+ * PCI TLU uncorrectable error interrupt enable, interrupt status and
+ * status clear registers
+ */
+#define FO_PCI_TLU_UERR_INT_S_MASK 0x001fffff00000000ULL
+#define FO_PCI_TLU_UERR_INT_S_SHFT 32
+#define FO_PCI_TLU_UERR_INT_UR_S 0x0010000000000000ULL
+#define OBERON_PCI_TLU_UERR_INT_ECRC_S 0x0008000000000000ULL
+#define FO_PCI_TLU_UERR_INT_MFP_S 0x0004000000000000ULL
+#define FO_PCI_TLU_UERR_INT_ROF_S 0x0002000000000000ULL
+#define FO_PCI_TLU_UERR_INT_UC_S 0x0001000000000000ULL
+#define FO_PCI_TLU_UERR_INT_CA_S 0x0000800000000000ULL
+#define FO_PCI_TLU_UERR_INT_CTO_S 0x0000400000000000ULL
+#define FO_PCI_TLU_UERR_INT_FCP_S 0x0000200000000000ULL
+#define FIRE_PCI_TLU_UERR_INT_PP_S 0x0000100000000000ULL
+#define OBERON_PCI_TLU_UERR_INT_POIS_S 0x0000100000000000ULL
+#define FO_PCI_TLU_UERR_INT_DLP_S 0x0000001000000000ULL
+#define FO_PCI_TLU_UERR_INT_TE_S 0x0000000100000000ULL
+#define FO_PCI_TLU_UERR_INT_P_MASK 0x00000000001fffffULL
+#define FO_PCI_TLU_UERR_INT_P_SHFT 0
+#define FO_PCI_TLU_UERR_INT_UR_P 0x0000000000100000ULL
+#define OBERON_PCI_TLU_UERR_INT_ECRC_P 0x0000000000080000ULL
+#define FO_PCI_TLU_UERR_INT_MFP_P 0x0000000000040000ULL
+#define FO_PCI_TLU_UERR_INT_ROF_P 0x0000000000020000ULL
+#define FO_PCI_TLU_UERR_INT_UC_P 0x0000000000010000ULL
+#define FO_PCI_TLU_UERR_INT_CA_P 0x0000000000008000ULL
+#define FO_PCI_TLU_UERR_INT_CTO_P 0x0000000000004000ULL
+#define FO_PCI_TLU_UERR_INT_FCP_P 0x0000000000002000ULL
+#define FIRE_PCI_TLU_UERR_INT_PP_P 0x0000000000001000ULL
+#define OBERON_PCI_TLU_UERR_INT_POIS_P 0x0000000000001000ULL
+#define FO_PCI_TLU_UERR_INT_DLP_P 0x0000000000000010ULL
+#define FO_PCI_TLU_UERR_INT_TE_P 0x0000000000000001ULL
+
+/*
+ * PCI TLU correctable error interrupt enable, interrupt status and
+ * status clear registers
+ */
+#define FO_PCI_TLU_CERR_INT_S_MASK 0x001fffff00000000ULL
+#define FO_PCI_TLU_CERR_INT_S_SHFT 32
+#define FO_PCI_TLU_CERR_INT_RTO_S 0x0000100000000000ULL
+#define FO_PCI_TLU_CERR_INT_RNR_S 0x0000010000000000ULL
+#define FO_PCI_TLU_CERR_INT_BDP_S 0x0000008000000000ULL
+#define FO_PCI_TLU_CERR_INT_BTP_S 0x0000004000000000ULL
+#define FO_PCI_TLU_CERR_INT_RE_S 0x0000000100000000ULL
+#define FO_PCI_TLU_CERR_INT_P_MASK 0x00000000001fffffULL
+#define FO_PCI_TLU_CERR_INT_P_SHFT 0
+#define FO_PCI_TLU_CERR_INT_RTO_P 0x0000000000001000ULL
+#define FO_PCI_TLU_CERR_INT_RNR_P 0x0000000000000100ULL
+#define FO_PCI_TLU_CERR_INT_BDP_P 0x0000000000000080ULL
+#define FO_PCI_TLU_CERR_INT_BTP_P 0x0000000000000040ULL
+#define FO_PCI_TLU_CERR_INT_RE_P 0x0000000000000001ULL
+
+/* PCI TLU reset register */
+#define FO_PCI_LPU_RST_WE 0x0000000080000000ULL
+#define FO_PCI_LPU_RST_UNUSED_MASK 0x0000000000000e00ULL
+#define FO_PCI_LPU_RST_UNUSED_SHFT 9
+#define FO_PCI_LPU_RST_ERR 0x0000000000000100ULL
+#define FO_PCI_LPU_RST_TXLINK 0x0000000000000080ULL
+#define FO_PCI_LPU_RST_RXLINK 0x0000000000000040ULL
+#define FO_PCI_LPU_RST_SMLINK 0x0000000000000020ULL
+#define FO_PCI_LPU_RST_LTSSM 0x0000000000000010ULL
+#define FO_PCI_LPU_RST_TXPHY 0x0000000000000008ULL
+#define FO_PCI_LPU_RST_RXPHY 0x0000000000000004ULL
+#define FO_PCI_LPU_RST_TXPCS 0x0000000000000002ULL
+#define FO_PCI_LPU_RST_RXPCS 0x0000000000000001ULL
+
+/* PCI TLU link control register */
+#define FO_PCI_TLU_LNK_CTRL_EXTSYNC 0x0000000000000080ULL
+#define FO_PCI_TLU_LNK_CTRL_CLK 0x0000000000000040ULL
+#define FO_PCI_TLU_LNK_CTRL_RETRAIN 0x0000000000000020ULL
+#define FO_PCI_TLU_LNK_CTRL_DIS 0x0000000000000010ULL
+#define FO_PCI_TLU_LNK_CTRL_RCB 0x0000000000000008ULL
+#define FO_PCI_TLU_LNK_CTRL_ASPM_L0S_L1S 0x0000000000000003ULL
+#define FO_PCI_TLU_LNK_CTRL_ASPM_L1S 0x0000000000000002ULL
+#define FO_PCI_TLU_LNK_CTRL_ASPM_L0S 0x0000000000000001ULL
+#define FO_PCI_TLU_LNK_CTRL_ASPM_DIS 0x0000000000000000ULL
+
+/* PCI TLU link status register */
+#define FO_PCI_TLU_LNK_STAT_CLK 0x0000000000001000ULL
+#define FO_PCI_TLU_LNK_STAT_TRAIN 0x0000000000000800ULL
+#define FO_PCI_TLU_LNK_STAT_ERR 0x0000000000000400ULL
+#define FO_PCI_TLU_LNK_STAT_WDTH_MASK 0x00000000000003f0ULL
+#define FO_PCI_TLU_LNK_STAT_WDTH_SHFT 4
+#define FO_PCI_TLU_LNK_STAT_SPEED_MASK 0x000000000000000fULL
+#define FO_PCI_TLU_LNK_STAT_SPEED_SHFT 0
+
+/*
+ * PCI receive/transmit DLU/TLU uncorrectable error header 1/2 log
+ * registers
+ */
+#define FO_PCI_TLU_UERR_HDR_LOG_MASK 0xffffffffffffffffULL
+#define FO_PCI_TLU_UERR_HDR_LOG_SHFT 0
+
+/* PCI DLU/LPU interrupt status and mask registers */
+#define FO_PCI_LPU_INT_INT 0x0000000080000000ULL
+#define FIRE_PCI_LPU_INT_PRF_CNT2_OFLW 0x0000000000000080ULL
+#define FIRE_PCI_LPU_INT_PRF_CNT1_OFLW 0x0000000000000040ULL
+#define FO_PCI_LPU_INT_LNK_LYR 0x0000000000000020ULL
+#define FO_PCI_LPU_INT_PHY_ERR 0x0000000000000010ULL
+#define FIRE_PCI_LPU_INT_LTSSM 0x0000000000000008ULL
+#define FIRE_PCI_LPU_INT_PHY_TX 0x0000000000000004ULL
+#define FIRE_PCI_LPU_INT_PHY_RX 0x0000000000000002ULL
+#define FIRE_PCI_LPU_INT_PHY_GB 0x0000000000000001ULL
+
+/* PCI DLU/LPU link layer config register */
+#define FIRE_PCI_LPU_LNK_LYR_CFG_AUTO_UPDT_DIS 0x0000000000080000ULL
+#define FIRE_PCI_LPU_LNK_LYR_CFG_FREQ_NAK_EN 0x0000000000040000ULL
+#define FIRE_PCI_LPU_LNK_LYR_CFG_RPLY_AFTER_REQ 0x0000000000020000ULL
+#define FIRE_PCI_LPU_LNK_LYR_CFG_LAT_THRS_WR_EN 0x0000000000010000ULL
+#define FO_PCI_LPU_LNK_LYR_CFG_VC0_EN 0x0000000000000100ULL
+#define FIRE_PCI_LPU_LNK_LYR_CFG_L0S_ADJ_FAC_EN 0x0000000000000010ULL
+#define FIER_PCI_LPU_LNK_LYR_CFG_TLP_XMIT_FC_EN 0x0000000000000008ULL
+#define FO_PCI_LPU_LNK_LYR_CFG_FREQ_ACK_EN 0x0000000000000004ULL
+#define FO_PCI_LPU_LNK_LYR_CFG_RETRY_DIS 0x0000000000000002ULL
+
+/* PCI DLU/LPU link layer interrupt and status register */
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_LNK_ERR_ACT 0x0000000080000000ULL
+#define OBERON_PCI_LPU_LNK_LYR_INT_STAT_PBUS_PE 0x0000000000800000ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_USPRTD_DLLP 0x0000000000400000ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_DLLP_RX_ERR 0x0000000000200000ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_BAD_DLLP 0x0000000000100000ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_TLP_RX_ERR 0x0000000000040000ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_SRC_ERR_TLP 0x0000000000020000ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_BAD_TLP 0x0000000000010000ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_RBF_UDF_ERR 0x0000000000000200ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_RBF_OVF_ERR 0x0000000000000100ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_EG_TLPM_ERR 0x0000000000000080ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_EG_TFRM_ERR 0x0000000000000040ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_RBF_PE 0x0000000000000020ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_EGRESS_PE 0x0000000000000010ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_RPLY_TMR_TO 0x0000000000000004ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_RPLY_NUM_RO 0x0000000000000002ULL
+#define FO_PCI_LPU_LNK_LYR_INT_STAT_DLNK_PES 0x0000000000000001ULL
+
+/* PCI DLU/LPU flow control update control register */
+#define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL_FC0_C_EN 0x0000000000000004ULL
+#define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL_FC0_NP_EN 0x0000000000000002ULL
+#define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL_FC0_P_EN 0x0000000000000001ULL
+
+/* PCI DLU/LPU txlink ACKNAK latency timer threshold register */
+#define FO_PCI_LPU_TXLNK_FREQ_LAT_TMR_THRS_MASK 0x000000000000ffffULL
+#define FO_PCI_LPU_TXLNK_FREQ_LAT_TMR_THRS_SHFT 0
+
+/* PCI DLU/LPU txlink replay timer threshold register */
+#define FO_PCI_LPU_TXLNK_RPLY_TMR_THRS_MASK 0x00000000000fffffULL
+#define FO_PCI_LPU_TXLNK_RPLY_TMR_THRS_SHFT 0
+
+/* PCI DLU/LPU txlink FIFO pointer register */
+#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_TL_MASK 0x00000000ffff0000ULL
+#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_TL_SHFT 16
+#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_HD_MASK 0x000000000000ffffULL
+#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_HD_SHFT 0
+
+/* PCI DLU/LPU phy layer interrupt and status register */
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_PHY_LYR_ERR 0x0000000080000000ULL
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_KC_DLLP_ERR 0x0000000000000800ULL
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_END_POS_ERR 0x0000000000000400ULL
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_LNK_ERR 0x0000000000000200ULL
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_TRN_ERR 0x0000000000000100ULL
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_EDB_DET 0x0000000000000080ULL
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_SDP_END 0x0000000000000040ULL
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_STP_END_EDB 0x0000000000000020ULL
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_INVC_ERR 0x0000000000000010ULL
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_MULTI_SDP 0x0000000000000008ULL
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_MULTI_STP 0x0000000000000004ULL
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_ILL_SDP_POS 0x0000000000000002ULL
+#define FO_PCI_LPU_PHY_LYR_INT_STAT_ILL_STP_POS 0x0000000000000001ULL
+
+/* PCI DLU/LPU LTSSM config2 register */
+#define FO_PCI_LPU_LTSSM_CFG2_12_TO_MASK 0x00000000ffffffffULL
+#define FO_PCI_LPU_LTSSM_CFG2_12_TO_SHFT 0
+
+/* PCI DLU/LPU LTSSM config3 register */
+#define FO_PCI_LPU_LTSSM_CFG3_2_TO_MASK 0x00000000ffffffffULL
+#define FO_PCI_LPU_LTSSM_CFG3_2_TO_SHFT 0
+
+/* PCI DLU/LPU LTSSM config4 register */
+#define FO_PCI_LPU_LTSSM_CFG4_TRN_CTRL_MASK 0x00000000ff000000ULL
+#define FO_PCI_LPU_LTSSM_CFG4_TRN_CTRL_SHFT 24
+#define FO_PCI_LPU_LTSSM_CFG4_DATA_RATE_MASK 0x0000000000ff0000ULL
+#define FO_PCI_LPU_LTSSM_CFG4_DATA_RATE_SHFT 16
+#define FO_PCI_LPU_LTSSM_CFG4_N_FTS_MASK 0x000000000000ff00ULL
+#define FO_PCI_LPU_LTSSM_CFG4_N_FTS_SHFT 8
+#define FO_PCI_LPU_LTSSM_CFG4_LNK_NUM_MASK 0x00000000000000ffULL
+#define FO_PCI_LPU_LTSSM_CFG4_LNK_NUM_SHFT 0
+
+/* PCI DLU/LPU LTSSM config5 register */
+#define FO_PCI_LPU_LTSSM_CFG5_UNUSED0_MASK 0x00000000ffffe000ULL
+#define FO_PCI_LPU_LTSSM_CFG5_UNUSED0_SHFT 13
+#define FO_PCI_LPU_LTSSM_CFG5_RCV_DET_TST_MODE 0x0000000000001000ULL
+#define FO_PCI_LPU_LTSSM_CFG5_POLL_CMPLNC_DIS 0x0000000000000800ULL
+#define FO_PCI_LPU_LTSSM_CFG5_TX_IDLE_TX_FTS 0x0000000000000400ULL
+#define FO_PCI_LPU_LTSSM_CFG5_RX_FTS_RVR_LK 0x0000000000000200ULL
+#define FO_PCI_LPU_LTSSM_CFG5_UNUSED1_MASK 0x0000000000000180ULL
+#define FO_PCI_LPU_LTSSM_CFG5_UNUSED1_SHFT 7
+#define FO_PCI_LPU_LTSSM_CFG5_LPBK_NTRY_ACTIVE 0x0000000000000040ULL
+#define FO_PCI_LPU_LTSSM_CFG5_LPBK_NTRY_EXIT 0x0000000000000020ULL
+#define FO_PCI_LPU_LTSSM_CFG5_LPBK_ACTIVE_EXIT 0x0000000000000010ULL
+#define FO_PCI_LPU_LTSSM_CFG5_L1_IDLE_RCVRY_LK 0x0000000000000008ULL
+#define FO_PCI_LPU_LTSSM_CFG5_L0_TRN_CNTRL_RST 0x0000000000000004ULL
+#define FO_PCI_LPU_LTSSM_CFG5_L0_LPBK 0x0000000000000002ULL
+#define FO_PCI_LPU_LTSSM_CFG5_UNUSED2 0x0000000000000001ULL
+
+/* Controller configuration and status registers */
+#define FIRE_JBUS_PAR_CTRL 0x60010
+#define FO_XBC_ERR_LOG_EN 0x61000
+#define FO_XBC_INT_EN 0x61008
+#define FO_XBC_INT_STAT 0x61010
+#define FO_XBC_ERR_STAT_CLR 0x61018
+#define FIRE_JBC_FATAL_RST_EN 0x61028
+#define FIRE_JBCINT_ITRANS_ERR_LOG 0x61040
+#define FIRE_JBCINT_ITRANS_ERR_LOG2 0x61048
+#define FIRE_JBCINT_OTRANS_ERR_LOG 0x61040
+#define FIRE_JBCINT_OTRANS_ERR_LOG2 0x61048
+#define FIRE_FATAL_ERR_LOG 0x61050
+#define FIRE_FATAL_ERR_LOG2 0x61058
+#define FIRE_MERGE_TRANS_ERR_LOG 0x61060
+#define FIRE_DMCINT_ODCD_ERR_LOG 0x61068
+#define FIRE_DMCINT_IDC_ERR_LOG 0x61070
+#define FIRE_JBC_CSR_ERR_LOG 0x61078
+#define FIRE_JBC_CORE_BLOCK_INT_EN 0x61800
+#define FIRE_JBC_CORE_BLOCK_ERR_STAT 0x61808
+#define FO_XBC_PRF_CNT_SEL 0x62000
+#define FO_XBC_PRF_CNT0 0x62008
+#define FO_XBC_PRF_CNT1 0x62010
+
+/* JBus parity control register */
+#define FIRE_JBUS_PAR_CTRL_P_EN 0x8000000000000000ULL
+#define FIRE_JBUS_PAR_CTRL_INVRTD_PAR_MASK 0x000000000000003cULL
+#define FIRE_JBUS_PAR_CTRL_INVRTD_PAR_SHFT 2
+#define FIRE_JBUS_PAR_CTRL_NEXT_DATA 0x0000000000000002ULL
+#define FIRE_JBUS_PAR_CTRL_NEXT_ADDR 0x0000000000000001ULL
+
+/* JBC error log enable register - may also apply to UBC */
+#define FIRE_JBC_ERR_LOG_EN_SPARE_MASK 0x00000000e0000000ULL
+#define FIRE_JBC_ERR_LOG_EN_SPARE_SHFT 29
+#define FIRE_JBC_ERR_LOG_EN_PIO_UNMAP_RD 0x0000000010000000ULL
+#define FIRE_JBC_ERR_LOG_EN_ILL_ACC_RD 0x0000000008000000ULL
+#define FIRE_JBC_ERR_LOG_EN_EBUS_TO 0x0000000004000000ULL
+#define FIRE_JBC_ERR_LOG_EN_MB_PEA 0x0000000002000000ULL
+#define FIRE_JBC_ERR_LOG_EN_MB_PER 0x0000000001000000ULL
+#define FIRE_JBC_ERR_LOG_EN_MB_PEW 0x0000000000800000ULL
+#define FIRE_JBC_ERR_LOG_EN_UE_ASYN 0x0000000000400000ULL
+#define FIRE_JBC_ERR_LOG_EN_CE_ASYN 0x0000000000200000ULL
+#define FIRE_JBC_ERR_LOG_EN_JTE 0x0000000000100000ULL
+#define FIRE_JBC_ERR_LOG_EN_JBE 0x0000000000080000ULL
+#define FIRE_JBC_ERR_LOG_EN_JUE 0x0000000000040000ULL
+#define FIRE_JBC_ERR_LOG_EN_IJP 0x0000000000020000ULL
+#define FIRE_JBC_ERR_LOG_EN_ICISE 0x0000000000010000ULL
+#define FIRE_JBC_ERR_LOG_EN_CPE 0x0000000000008000ULL
+#define FIRE_JBC_ERR_LOG_EN_APE 0x0000000000004000ULL
+#define FIRE_JBC_ERR_LOG_EN_WR_DPE 0x0000000000002000ULL
+#define FIRE_JBC_ERR_LOG_EN_RD_DPE 0x0000000000001000ULL
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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