svn commit: r190478 - in stable/7/sys: . contrib/pf dev/ath/ath_hal dev/bge dev/cxgb

[Marius Strobl]

Author: marius
Date: Fri Mar 27 21:21:22 2009
New Revision: 190478
URL: http://svn.freebsd.org/changeset/base/190478

Log:
  MFC: r190319
  
  - Ensure that INTx isn't disabled, as these chips apparently have a
    quirk requiring it to be enabled even when using MSI. This makes
    the latter work again after r189568.
  - Remove a comment which no longer applies since r190335.
  
  Approved by:	re (kib)

Modified:
  stable/7/sys/   (props changed)
  stable/7/sys/contrib/pf/   (props changed)
  stable/7/sys/dev/ath/ath_hal/   (props changed)
  stable/7/sys/dev/bge/if_bge.c
  stable/7/sys/dev/bge/if_bgereg.h
  stable/7/sys/dev/cxgb/   (props changed)

Modified: stable/7/sys/dev/bge/if_bge.c
==============================================================================
--- stable/7/sys/dev/bge/if_bge.c	Fri Mar 27 21:13:14 2009	(r190477)
+++ stable/7/sys/dev/bge/if_bge.c	Fri Mar 27 21:21:22 2009	(r190478)
@@ -1295,8 +1295,7 @@ bge_stop_fw(sc)
 }
 
 /*
- * Do endian, PCI and DMA initialization. Also check the on-board ROM
- * self-test results.
+ * Do endian, PCI and DMA initialization.
  */
 static int
 bge_chipinit(struct bge_softc *sc)
@@ -1404,9 +1403,11 @@ bge_chipinit(struct bge_softc *sc)
 
 	/*
 	 * Disable memory write invalidate.  Apparently it is not supported
-	 * properly by these devices.
+	 * properly by these devices.  Also ensure that INTx isn't disabled,
+	 * as these chips need it even when using MSI.
 	 */
-	PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
+	PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
+	    PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
 
 	/* Set the timer prescaler (always 66Mhz) */
 	CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);

Modified: stable/7/sys/dev/bge/if_bgereg.h
==============================================================================
--- stable/7/sys/dev/bge/if_bgereg.h	Fri Mar 27 21:13:14 2009	(r190477)
+++ stable/7/sys/dev/bge/if_bgereg.h	Fri Mar 27 21:21:22 2009	(r190478)
@@ -404,6 +404,9 @@
 #ifndef PCIM_CMD_MWIEN
 #define	PCIM_CMD_MWIEN			0x0010
 #endif
+#ifndef PCIM_CMD_INTxDIS
+#define	PCIM_CMD_INTxDIS		0x0400
+#endif
 
 /*
  * High priority mailbox registers