svn commit: r187099 - in stable/7: share/man/man4 sys
sys/amd64/amd64 sys/amd64/conf sys/amd64/include sys/conf
sys/contrib/pf sys/dev/ath/ath_hal sys/dev/cpuctl
sys/dev/cxgb sys/i386/conf sys/i386...
Stanislav Sedov
stas at FreeBSD.org
Mon Jan 12 07:48:24 PST 2009
Author: stas
Date: Mon Jan 12 15:48:22 2009
New Revision: 187099
URL: http://svn.freebsd.org/changeset/base/187099
Log:
- MFC cpuctl and related commits into RELENG_7.
First revision of usr.sbin/cpucontrol was
merged directly into usr.sbin since there're
no such directory in stable/7 yet. Subsequient
changes went into usr.sbin/cpucontrol.
Approved by: kib (mentor)
Added:
stable/7/share/man/man4/cpuctl.4
- copied, changed from r181430, head/share/man/man4/cpuctl.4
stable/7/sys/dev/cpuctl/
- copied from r181430, head/sys/dev/cpuctl/
stable/7/sys/modules/cpuctl/
- copied from r181430, head/sys/modules/cpuctl/
stable/7/sys/sys/cpuctl.h
- copied unchanged from r181430, head/sys/sys/cpuctl.h
stable/7/usr.sbin/cpucontrol/ (props changed)
- copied from r181430, head/usr.sbin/cpucontrol/
Modified:
stable/7/share/man/man4/ (props changed)
stable/7/share/man/man4/Makefile
stable/7/share/man/man4/igb.4 (props changed)
stable/7/sys/ (props changed)
stable/7/sys/amd64/amd64/support.S
stable/7/sys/amd64/conf/NOTES
stable/7/sys/amd64/include/cpufunc.h
stable/7/sys/amd64/include/specialreg.h
stable/7/sys/conf/files.amd64
stable/7/sys/conf/files.i386
stable/7/sys/contrib/pf/ (props changed)
stable/7/sys/dev/ath/ath_hal/ (props changed)
stable/7/sys/dev/cpuctl/cpuctl.c
stable/7/sys/dev/cxgb/ (props changed)
stable/7/sys/i386/conf/NOTES
stable/7/sys/i386/i386/support.s
stable/7/sys/i386/include/cpufunc.h
stable/7/sys/i386/include/specialreg.h
stable/7/sys/modules/Makefile
stable/7/sys/sys/priv.h
stable/7/usr.sbin/ (props changed)
stable/7/usr.sbin/Makefile
stable/7/usr.sbin/adduser/ (props changed)
stable/7/usr.sbin/bsnmpd/modules/snmp_pf/ (props changed)
stable/7/usr.sbin/cdcontrol/ (props changed)
stable/7/usr.sbin/config/ (props changed)
stable/7/usr.sbin/cpucontrol/cpucontrol.8
stable/7/usr.sbin/cpucontrol/cpucontrol.c
stable/7/usr.sbin/cron/ (props changed)
stable/7/usr.sbin/cron/cron/ (props changed)
stable/7/usr.sbin/extattr/ (props changed)
stable/7/usr.sbin/freebsd-update/ (props changed)
stable/7/usr.sbin/fwcontrol/ (props changed)
stable/7/usr.sbin/iostat/ (props changed)
stable/7/usr.sbin/mergemaster/ (props changed)
stable/7/usr.sbin/mountd/ (props changed)
stable/7/usr.sbin/mtree/ (props changed)
stable/7/usr.sbin/ndiscvt/ (props changed)
stable/7/usr.sbin/newsyslog/newsyslog.conf.5 (props changed)
stable/7/usr.sbin/nscd/ (props changed)
stable/7/usr.sbin/ntp/ (props changed)
stable/7/usr.sbin/pciconf/ (props changed)
stable/7/usr.sbin/pkg_install/ (props changed)
stable/7/usr.sbin/pmcstat/ (props changed)
stable/7/usr.sbin/portsnap/ (props changed)
stable/7/usr.sbin/pw/ (props changed)
stable/7/usr.sbin/rpc.lockd/ (props changed)
stable/7/usr.sbin/rpc.statd/ (props changed)
stable/7/usr.sbin/rpc.yppasswdd/ (props changed)
stable/7/usr.sbin/setfib/ (props changed)
stable/7/usr.sbin/sysinstall/ (props changed)
stable/7/usr.sbin/syslogd/ (props changed)
stable/7/usr.sbin/traceroute/ (props changed)
stable/7/usr.sbin/tzsetup/ (props changed)
stable/7/usr.sbin/wpa/wpa_supplicant/ (props changed)
Modified: stable/7/share/man/man4/Makefile
==============================================================================
--- stable/7/share/man/man4/Makefile Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/share/man/man4/Makefile Mon Jan 12 15:48:22 2009 (r187099)
@@ -55,6 +55,7 @@ MAN= aac.4 \
cnw.4 \
coda.4 \
${_coretemp.4} \
+ ${_cpuctl.4} \
cpufreq.4 \
crypto.4 \
cue.4 \
@@ -554,6 +555,7 @@ MLINKS+=xl.4 if_xl.4
_acpi_dock.4= acpi_dock.4
_amdsmb.4= amdsmb.4
_coretemp.4= coretemp.4
+_cpuctl.4= cpuctl.4
_hptiop.4= hptiop.4
_hptmv.4= hptmv.4
_hptrr.4= hptrr.4
Copied and modified: stable/7/share/man/man4/cpuctl.4 (from r181430, head/share/man/man4/cpuctl.4)
==============================================================================
--- head/share/man/man4/cpuctl.4 Fri Aug 8 16:26:53 2008 (r181430, copy source)
+++ stable/7/share/man/man4/cpuctl.4 Mon Jan 12 15:48:22 2009 (r187099)
@@ -45,30 +45,33 @@ at boot time, place the following in
cpuctl_load="YES"
.Ed
.Sh DESCRIPTION
-The special file
+The special device
.Pa /dev/cpuctl
-presents interace to the system CPU. It provides functionality to retrieve
+presents interface to the system CPU.
+It provides functionality to retrieve
CPUID information, read/write machine specific registers (MSR) and perform
-cpu firmware updates.
+CPU firmware updates.
.Pp
-For each cpu present in the system, special file
+For each CPU present in the system, the special device
.Pa /dev/cpuctl%d
-with the appropriate index will be created. For multicore cpus the
-special file will be created for each core.
+with the appropriate index will be created.
+For multicore CPUs such a
+special device will be created for each core.
.Pp
Currently, only i386 and amd64 processors are
supported.
.Sh IOCTL INTERFACE
All of the supported operations are invoked using the
-.Fr ioctl 2
-system call. Refer to that manpage for further information about
-this interface. Currently, the following ioctls are defined:
+.Xr ioctl 2
+system call.
+Currently, the following ioctls are defined:
.Bl -tag -width CPUCTL_UPDATE
.It Dv CPUCTL_RDMSR Fa cpuctl_msr_args_t *args
.It Dv CPUCTL_WRMSR Fa cpuctl_msr_args_t *args
-Read/write cpu machine specific register. The
+Read/write CPU machine specific register.
+The
.Vt cpuctl_msr_args_t
-structure defined in
+structure is defined in
.In sys/cpuctl.h
as:
.Pp
@@ -79,7 +82,8 @@ typedef struct {
} cpuctl_msr_args_t;
.Ed
.It Dv CPUCTL_CPUID Fa cpuctl_cpuid_args_t *args
-Retrieve CPUID information. Arguments are supplied in
+Retrieve CPUID information.
+Arguments are supplied in
the following struct:
.Pp
.Bd -literal
@@ -93,9 +97,10 @@ The
.Va level
field indicates the CPUID level to retrieve information for, while the
.Va data
-used to store CPUID data received.
+field is used to store the received CPUID data.
.It Dv CPUCTL_UPDATE cpuctl_update_args_t *args
-Update cpu firmware (microcode). The structure defined in
+Update CPU firmware (microcode).
+The structure is defined in
.In sys/cpuctl.h
as:
.Pp
@@ -117,30 +122,31 @@ For additional information refer to
.Sh RETURN VALUES
.Bl -tag -width Er
.It Bq Er ENXIO
-The operation requested is not supported by device (e.g. unsupported
-architecture or cpu was disabled)
+The operation requested is not supported by the device (e.g. unsupported
+architecture or the CPU is disabled)
.It Bq Er EINVAL
Incorrect request was supplied, or microcode image is not correct.
.It Bq Er ENOMEM
No physical memory was available to complete the request.
.It Bq Er EFAULT
-The firmware image address points outside process address space.
+The firmware image address points outside the process address space.
.El
.Sh FILES
.Bl -tag -width /dev/cpuctl -compact
.It Pa /dev/cpuctl
.El
.Sh SEE ALSO
-.Xr hwpmc 4
+.Xr hwpmc 4 ,
+.Xr cpucontrol 8
.Sh HISTORY
The
.Nm
driver first appeared in
-.Fx 8.0
+.Fx 8.0 .
.Sh BUGS
Yes, probably, report if any.
.Sh AUTHORS
The
.Nm
-module and this manual page was written by
+module and this manual page were written by
.An Stanislav Sedov Aq stas at FreeBSD.org .
Modified: stable/7/sys/amd64/amd64/support.S
==============================================================================
--- stable/7/sys/amd64/amd64/support.S Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/sys/amd64/amd64/support.S Mon Jan 12 15:48:22 2009 (r187099)
@@ -716,3 +716,47 @@ NON_GPROF_ENTRY(__bb_init_func)
movq %rax,32(%rdi)
movq %rdi,bbhead
NON_GPROF_RET
+
+/*
+ * Support for reading MSRs in the safe manner.
+ */
+ENTRY(rdmsr_safe)
+/* int rdmsr_safe(u_int msr, uint64_t *data) */
+ movq PCPU(CURPCB),%r8
+ movq $msr_onfault,PCB_ONFAULT(%r8)
+ movl %edi,%ecx
+ rdmsr /* Read MSR pointed by %ecx. Returns
+ hi byte in edx, lo in %eax */
+ salq $32,%rdx /* sign-shift %rdx left */
+ cltq /* sign-extend %eax -> %rax */
+ orq %rdx,%rax
+ movq %rax,(%rsi)
+ xorq %rax,%rax
+ movq %rax,PCB_ONFAULT(%r8)
+ ret
+
+/*
+ * Support for writing MSRs in the safe manner.
+ */
+ENTRY(wrmsr_safe)
+/* int wrmsr_safe(u_int msr, uint64_t data) */
+ movq PCPU(CURPCB),%r8
+ movq $msr_onfault,PCB_ONFAULT(%r8)
+ movl %edi,%ecx
+ movl %esi,%eax
+ sarq $32,%rsi
+ movl %esi,%edx
+ wrmsr /* Write MSR pointed by %ecx. Accepts
+ hi byte in edx, lo in %eax. */
+ xorq %rax,%rax
+ movq %rax,PCB_ONFAULT(%r8)
+ ret
+
+/*
+ * MSR operations fault handler
+ */
+ ALIGN_TEXT
+msr_onfault:
+ movq $0,PCB_ONFAULT(%r8)
+ movl $EFAULT,%eax
+ ret
Modified: stable/7/sys/amd64/conf/NOTES
==============================================================================
--- stable/7/sys/amd64/conf/NOTES Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/sys/amd64/conf/NOTES Mon Jan 12 15:48:22 2009 (r187099)
@@ -575,6 +575,12 @@ options ELSA_QS1PCI
#---------------------------------------------------------------------------
#
+# CPU control pseudo-device. Provides access to MSRs, CPUID info and
+# microcode update feature.
+#
+device cpuctl
+
+#
# System Management Bus (SMB)
#
options ENABLE_ALART # Control alarm on Intel intpm driver
Modified: stable/7/sys/amd64/include/cpufunc.h
==============================================================================
--- stable/7/sys/amd64/include/cpufunc.h Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/sys/amd64/include/cpufunc.h Mon Jan 12 15:48:22 2009 (r187099)
@@ -777,4 +777,9 @@ void wrmsr(u_int msr, u_int64_t newval);
void reset_dbregs(void);
+#ifdef _KERNEL
+int rdmsr_safe(u_int msr, uint64_t *val);
+int wrmsr_safe(u_int msr, uint64_t newval);
+#endif
+
#endif /* !_MACHINE_CPUFUNC_H_ */
Modified: stable/7/sys/amd64/include/specialreg.h
==============================================================================
--- stable/7/sys/amd64/include/specialreg.h Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/sys/amd64/include/specialreg.h Mon Jan 12 15:48:22 2009 (r187099)
@@ -161,6 +161,12 @@
#define AMDID_CMP_CORES 0x000000ff
/*
+ * CPUID manufacturers identifiers
+ */
+#define INTEL_VENDOR_ID "GenuineIntel"
+#define AMD_VENDOR_ID "AuthenticAMD"
+
+/*
* Model-specific registers for the i386 family
*/
#define MSR_P5_MC_ADDR 0x000
@@ -409,5 +415,6 @@
#define MSR_IORRMASK1 0xc0010019
#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
+#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
#endif /* !_MACHINE_SPECIALREG_H_ */
Modified: stable/7/sys/conf/files.amd64
==============================================================================
--- stable/7/sys/conf/files.amd64 Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/sys/conf/files.amd64 Mon Jan 12 15:48:22 2009 (r187099)
@@ -149,6 +149,7 @@ dev/atkbdc/atkbdc_isa.c optional atkbdc
dev/atkbdc/atkbdc_subr.c optional atkbdc
dev/atkbdc/psm.c optional psm atkbdc
dev/coretemp/coretemp.c optional coretemp
+dev/cpuctl/cpuctl.c optional cpuctl
# There are no systems with isa slots, so all ed isa entries should go..
dev/ed/if_ed_3c503.c optional ed isa ed_3c503
dev/ed/if_ed_isa.c optional ed isa
Modified: stable/7/sys/conf/files.i386
==============================================================================
--- stable/7/sys/conf/files.i386 Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/sys/conf/files.i386 Mon Jan 12 15:48:22 2009 (r187099)
@@ -161,6 +161,7 @@ dev/cm/if_cm_isa.c optional cm isa
dev/coretemp/coretemp.c optional coretemp
dev/cp/cpddk.c optional cp
dev/cp/if_cp.c optional cp
+dev/cpuctl/cpuctl.c optional cpuctl
dev/ctau/ctau.c optional ctau
dev/ctau/ctddk.c optional ctau
dev/ctau/if_ct.c optional ctau
Modified: stable/7/sys/dev/cpuctl/cpuctl.c
==============================================================================
--- head/sys/dev/cpuctl/cpuctl.c Fri Aug 8 16:26:53 2008 (r181430)
+++ stable/7/sys/dev/cpuctl/cpuctl.c Mon Jan 12 15:48:22 2009 (r187099)
@@ -80,7 +80,7 @@ static MALLOC_DEFINE(M_CPUCTL, "cpuctl",
static struct cdevsw cpuctl_cdevsw = {
.d_version = D_VERSION,
- .d_flags = D_NEEDMINOR,
+ .d_flags = 0,
.d_open = cpuctl_open,
.d_ioctl = cpuctl_ioctl,
.d_name = "cpuctl",
Modified: stable/7/sys/i386/conf/NOTES
==============================================================================
--- stable/7/sys/i386/conf/NOTES Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/sys/i386/conf/NOTES Mon Jan 12 15:48:22 2009 (r187099)
@@ -1102,6 +1102,12 @@ device i4bcapi
#---------------------------------------------------------------------------
#
+# CPU control pseudo-device. Provides access to MSRs, CPUID info and
+# microcode update feature.
+#
+device cpuctl
+
+#
# System Management Bus (SMB)
#
options ENABLE_ALART # Control alarm on Intel intpm driver
Modified: stable/7/sys/i386/i386/support.s
==============================================================================
--- stable/7/sys/i386/i386/support.s Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/sys/i386/i386/support.s Mon Jan 12 15:48:22 2009 (r187099)
@@ -1568,3 +1568,52 @@ NON_GPROF_ENTRY(__bb_init_func)
movl %edx,16(%eax)
movl %eax,bbhead
NON_GPROF_RET
+
+/*
+ * Support for reading MSRs in the safe manner.
+ */
+ENTRY(rdmsr_safe)
+/* int rdmsr_safe(u_int msr, uint64_t *data) */
+ movl PCPU(CURPCB),%ecx
+ movl $msr_onfault,PCB_ONFAULT(%ecx)
+
+ movl 4(%esp),%ecx
+ rdmsr
+ movl 8(%esp),%ecx
+ movl %eax,(%ecx)
+ movl %edx,4(%ecx)
+ xorl %eax,%eax
+
+ movl PCPU(CURPCB),%ecx
+ movl %eax,PCB_ONFAULT(%ecx)
+
+ ret
+
+/*
+ * Support for writing MSRs in the safe manner.
+ */
+ENTRY(wrmsr_safe)
+/* int wrmsr_safe(u_int msr, uint64_t data) */
+ movl PCPU(CURPCB),%ecx
+ movl $msr_onfault,PCB_ONFAULT(%ecx)
+
+ movl 4(%esp),%ecx
+ movl 8(%esp),%eax
+ movl 12(%esp),%edx
+ wrmsr
+ xorl %eax,%eax
+
+ movl PCPU(CURPCB),%ecx
+ movl %eax,PCB_ONFAULT(%ecx)
+
+ ret
+
+/*
+ * MSR operations fault handler
+ */
+ ALIGN_TEXT
+msr_onfault:
+ movl PCPU(CURPCB),%ecx
+ movl $0,PCB_ONFAULT(%ecx)
+ movl $EFAULT,%eax
+ ret
Modified: stable/7/sys/i386/include/cpufunc.h
==============================================================================
--- stable/7/sys/i386/include/cpufunc.h Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/sys/i386/include/cpufunc.h Mon Jan 12 15:48:22 2009 (r187099)
@@ -735,4 +735,9 @@ void wrmsr(u_int msr, uint64_t newval);
void reset_dbregs(void);
+#ifdef _KERNEL
+int rdmsr_safe(u_int msr, uint64_t *val);
+int wrmsr_safe(u_int msr, uint64_t newval);
+#endif
+
#endif /* !_MACHINE_CPUFUNC_H_ */
Modified: stable/7/sys/i386/include/specialreg.h
==============================================================================
--- stable/7/sys/i386/include/specialreg.h Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/sys/i386/include/specialreg.h Mon Jan 12 15:48:22 2009 (r187099)
@@ -163,6 +163,12 @@
#define AMDID_CMP_CORES 0x000000ff
/*
+ * CPUID manufacturers identifiers
+ */
+#define INTEL_VENDOR_ID "GenuineIntel"
+#define AMD_VENDOR_ID "AuthenticAMD"
+
+/*
* Model-specific registers for the i386 family
*/
#define MSR_P5_MC_ADDR 0x000
@@ -450,6 +456,7 @@
/* AMD64 MSR's */
#define MSR_EFER 0xc0000080 /* extended features */
+#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
/* VIA ACE crypto featureset: for via_feature_rng */
#define VIA_HAS_RNG 1 /* cpu has RNG */
Modified: stable/7/sys/modules/Makefile
==============================================================================
--- stable/7/sys/modules/Makefile Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/sys/modules/Makefile Mon Jan 12 15:48:22 2009 (r187099)
@@ -61,6 +61,7 @@ SUBDIR= ${_3dfx} \
${_coff} \
${_coretemp} \
${_cp} \
+ ${_cpuctl} \
${_cpufreq} \
${_crypto} \
${_cryptodev} \
@@ -390,6 +391,7 @@ _cbb= cbb
_ce= ce
_coff= coff
_cp= cp
+_cpuctl= cpuctl
_cpufreq= cpufreq
_cs= cs
.if ${MK_CDDL} != "no" || defined(ALL_MODULES)
@@ -525,6 +527,7 @@ _cbb= cbb
_cmx= cmx
_ciss= ciss
_coretemp= coretemp
+_cpuctl= cpuctl
_cpufreq= cpufreq
.if ${MK_CDDL} != "no" || defined(ALL_MODULES)
_cyclic= cyclic
Copied: stable/7/sys/sys/cpuctl.h (from r181430, head/sys/sys/cpuctl.h)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ stable/7/sys/sys/cpuctl.h Mon Jan 12 15:48:22 2009 (r187099, copy of r181430, head/sys/sys/cpuctl.h)
@@ -0,0 +1,52 @@
+/*-
+ * Copyright (c) 2006-2008 Stanislav Sedov <stas at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _CPUCTL_H_
+#define _CPUCTL_H_
+
+typedef struct {
+ int msr; /* MSR to read */
+ uint64_t data;
+} cpuctl_msr_args_t;
+
+typedef struct {
+ int level; /* CPUID level */
+ uint32_t data[4];
+} cpuctl_cpuid_args_t;
+
+typedef struct {
+ void *data;
+ size_t size;
+} cpuctl_update_args_t;
+
+#define CPUCTL_RDMSR _IOWR('c', 1, cpuctl_msr_args_t)
+#define CPUCTL_WRMSR _IOWR('c', 2, cpuctl_msr_args_t)
+#define CPUCTL_CPUID _IOWR('c', 3, cpuctl_cpuid_args_t)
+#define CPUCTL_UPDATE _IOWR('c', 4, cpuctl_update_args_t)
+
+#endif /* _CPUCTL_H_ */
Modified: stable/7/sys/sys/priv.h
==============================================================================
--- stable/7/sys/sys/priv.h Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/sys/sys/priv.h Mon Jan 12 15:48:22 2009 (r187099)
@@ -455,9 +455,15 @@
#define PRIV_NNPFS_DEBUG 630 /* Perforn ARLA_VIOC_NNPFSDEBUG. */
/*
+ * cpuctl(4) privileges.
+ */
+#define PRIV_CPUCTL_WRMSR 640 /* Write model-specific register. */
+#define PRIV_CPUCTL_UPDATE 641 /* Update cpu microcode. */
+
+/*
* Track end of privilege list.
*/
-#define _PRIV_HIGHEST 631
+#define _PRIV_HIGHEST 642
/*
* Validate that a named privilege is known by the privilege system. Invalid
Modified: stable/7/usr.sbin/Makefile
==============================================================================
--- stable/7/usr.sbin/Makefile Mon Jan 12 13:12:02 2009 (r187098)
+++ stable/7/usr.sbin/Makefile Mon Jan 12 15:48:22 2009 (r187099)
@@ -34,6 +34,7 @@ SUBDIR= ac \
ckdist \
clear_locks \
config \
+ ${_cpucontrol} \
crashinfo \
cron \
crunch \
@@ -302,6 +303,7 @@ _apm= apm
_apmd= apmd
_asf= asf
_btxld= btxld
+_cpucontrol= cpucontrol
.if ${MK_I4B} != "no"
_i4b= i4b
.endif
@@ -340,6 +342,7 @@ _acpi= acpi
_asf= asf
_boot0cfg= boot0cfg
_btxld= btxld
+_cpucontrol= cpucontrol
_kgmon= kgmon
_lptcontrol= lptcontrol
.if ${MK_NCP} != "no"
Modified: stable/7/usr.sbin/cpucontrol/cpucontrol.8
==============================================================================
--- head/usr.sbin/cpucontrol/cpucontrol.8 Fri Aug 8 16:26:53 2008 (r181430)
+++ stable/7/usr.sbin/cpucontrol/cpucontrol.8 Mon Jan 12 15:48:22 2009 (r187099)
@@ -55,33 +55,36 @@ device.
.Sh DESCRIPTION
The
.Nm
-utility can be used to read and write an arbitrary machine-specific
-CPU registers via
+utility can be used to read and write arbitrary machine-specific
+CPU registers via the
.Xr cpuctl 4
-controlled special device and apply the CPU firmware updates.
+special device.
+It can also be used to apply CPU firmware updates.
.Pp
The following options are available:
.Bl -tag -width indent
.It Fl d Ar datadir
-Where to look for microcode images. The option can be specified multiple times.
+Where to look for microcode images.
+The option can be specified multiple times.
.It Fl m Ar msr Ns Op = Ns Ar value
-Read/write the specified MSR. Both the MSR and the value should be given as a hex number.
+Read/write the specified MSR.
+Both the MSR and the value should be given as a hex number.
.It Fl i Ar level
-Retrieve CPUID info. Level should be given as a hex number.
+Retrieve CPUID info.
+Level should be given as a hex number.
.It Fl u
-Apply CPU firmware updates. The
+Apply CPU firmware updates.
+The
.Nm
utility will walk through the configured data directories
-and will apply all firmware patches available for this CPU.
+and apply all firmware updates available for this CPU.
.It Fl v
Increase the verbosity level.
.It Fl h
Show help message.
.El
.Sh EXIT STATUS
-The
-.Nm
-utility exits 0 on success, and >0 if an error occurs.
+.Ex -std
.Sh EXAMPLES
The command
.Pp
@@ -93,20 +96,24 @@ To set the CPU 0 TSC MSR register value
.Pp
.Dq Li "cpucontrol -m 0x10=0x1 /dev/cpuctl0"
.Pp
-.Pp
The command
.Pp
.Dq Li "cpucontrol -i 0x1 /dev/cpuctl1"
.Pp
will retrieve the CPUID level 0x1 from CPU 1.
.Pp
-To perform firmware updated on CPU 0 from images located at
+To perform firmware updates on CPU 0 from images located at
.Pa /usr/local/share/cpuctl/
use the following command:
.Pp
.Dq Li "cpucontrol -d /usr/local/share/cpuctl/ -u /dev/cpuctl0"
.Sh SEE ALSO
.Xr cpuctl 4
+.Sh HISTORY
+The
+.Nm
+utility first appeared in
+.Fx 8.0 .
.Sh BUGS
Yes, probably, report if any.
.Sh AUTHORS
Modified: stable/7/usr.sbin/cpucontrol/cpucontrol.c
==============================================================================
--- head/usr.sbin/cpucontrol/cpucontrol.c Fri Aug 8 16:26:53 2008 (r181430)
+++ stable/7/usr.sbin/cpucontrol/cpucontrol.c Mon Jan 12 15:48:22 2009 (r187099)
@@ -146,12 +146,12 @@ do_cpuid(const char *cmdarg, const char
args.level = level;
fd = open(dev, O_RDONLY);
if (fd < 0) {
- WARNX(0, "error opening %s for reading", dev);
+ WARN(0, "error opening %s for reading", dev);
return (1);
}
error = ioctl(fd, CPUCTL_CPUID, &args);
if (error < 0) {
- WARNX(0, "ioctl(%s, CPUCTL_CPUID)", dev);
+ WARN(0, "ioctl(%s, CPUCTL_CPUID)", dev);
close(fd);
return (error);
}
@@ -198,13 +198,13 @@ do_msr(const char *cmdarg, const char *d
args.msr = msr;
fd = open(dev, wr == 0 ? O_RDONLY : O_WRONLY);
if (fd < 0) {
- WARNX(0, "error opening %s for %s", dev,
+ WARN(0, "error opening %s for %s", dev,
wr == 0 ? "reading" : "writing");
return (1);
}
error = ioctl(fd, wr == 0 ? CPUCTL_RDMSR : CPUCTL_WRMSR, &args);
if (error < 0) {
- WARNX(0, "ioctl(%s, %s)", dev,
+ WARN(0, "ioctl(%s, %s)", dev,
wr == 0 ? "CPUCTL_RDMSR" : "CPUCTL_WRMSR");
close(fd);
return (1);
@@ -230,7 +230,7 @@ do_update(const char *dev)
fd = open(dev, O_RDONLY);
if (fd < 0) {
- WARNX(0, "error opening %s for reading", dev);
+ WARN(0, "error opening %s for reading", dev);
return (1);
}
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