svn commit: r190663 - in stable/7/sys: . contrib/pf dev/ath/ath_hal
dev/cxgb dev/re
Pyun YongHyeon
yongari at FreeBSD.org
Thu Apr 2 17:12:15 PDT 2009
Author: yongari
Date: Fri Apr 3 00:12:14 2009
New Revision: 190663
URL: http://svn.freebsd.org/changeset/base/190663
Log:
MFC r190587:
It seems that RTL8168D and RTL8102EL requires additional settle
time to complete RL_PHYAR register write. Accessing RL_PHYAR
register right after the write causes errors for subsequent PHY
register accesses.
Tested by: george at luckytele dot com,
Steve Wills < STEVE at stevenwills dot com >
Approved by: re (Kostik Belousov)
Modified:
stable/7/sys/ (props changed)
stable/7/sys/contrib/pf/ (props changed)
stable/7/sys/dev/ath/ath_hal/ (props changed)
stable/7/sys/dev/cxgb/ (props changed)
stable/7/sys/dev/re/if_re.c
Modified: stable/7/sys/dev/re/if_re.c
==============================================================================
--- stable/7/sys/dev/re/if_re.c Fri Apr 3 00:10:19 2009 (r190662)
+++ stable/7/sys/dev/re/if_re.c Fri Apr 3 00:12:14 2009 (r190663)
@@ -420,6 +420,7 @@ re_gmii_readreg(device_t dev, int phy, i
}
CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
+ DELAY(1000);
for (i = 0; i < RL_PHY_TIMEOUT; i++) {
rval = CSR_READ_4(sc, RL_PHYAR);
@@ -447,6 +448,7 @@ re_gmii_writereg(device_t dev, int phy,
CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
(data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
+ DELAY(1000);
for (i = 0; i < RL_PHY_TIMEOUT; i++) {
rval = CSR_READ_4(sc, RL_PHYAR);
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