svn commit: r350266 - stable/12/sys/dev/cxgbe
Navdeep Parhar
np at FreeBSD.org
Tue Jul 23 22:00:20 UTC 2019
Author: np
Date: Tue Jul 23 22:00:19 2019
New Revision: 350266
URL: https://svnweb.freebsd.org/changeset/base/350266
Log:
MFC r349870:
cxgbe(4): Clear the freelist statistics in the clearstats ioctl.
Move all clearstats code into its own function while here.
Sponsored by: Chelsio Communications
Modified:
stable/12/sys/dev/cxgbe/t4_main.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/dev/cxgbe/t4_main.c
==============================================================================
--- stable/12/sys/dev/cxgbe/t4_main.c Tue Jul 23 21:28:20 2019 (r350265)
+++ stable/12/sys/dev/cxgbe/t4_main.c Tue Jul 23 22:00:19 2019 (r350266)
@@ -694,6 +694,7 @@ static void free_offload_policy(struct t4_offload_poli
static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
static int read_i2c(struct adapter *, struct t4_i2c_data *);
+static int clear_stats(struct adapter *, u_int);
#ifdef TCP_OFFLOAD
static int toe_capability(struct vi_info *, int);
#endif
@@ -9837,6 +9838,107 @@ read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
return (rc);
}
+static int
+clear_stats(struct adapter *sc, u_int port_id)
+{
+ int i, v, bg_map;
+ struct port_info *pi;
+ struct vi_info *vi;
+ struct sge_rxq *rxq;
+ struct sge_txq *txq;
+ struct sge_wrq *wrq;
+#ifdef TCP_OFFLOAD
+ struct sge_ofld_rxq *ofld_rxq;
+#endif
+
+ if (port_id >= sc->params.nports)
+ return (EINVAL);
+ pi = sc->port[port_id];
+ if (pi == NULL)
+ return (EIO);
+
+ /* MAC stats */
+ t4_clr_port_stats(sc, pi->tx_chan);
+ pi->tx_parse_error = 0;
+ pi->tnl_cong_drops = 0;
+ mtx_lock(&sc->reg_lock);
+ for_each_vi(pi, v, vi) {
+ if (vi->flags & VI_INIT_DONE)
+ t4_clr_vi_stats(sc, vi->vin);
+ }
+ bg_map = pi->mps_bg_map;
+ v = 0; /* reuse */
+ while (bg_map) {
+ i = ffs(bg_map) - 1;
+ t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
+ 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
+ bg_map &= ~(1 << i);
+ }
+ mtx_unlock(&sc->reg_lock);
+
+ /*
+ * Since this command accepts a port, clear stats for
+ * all VIs on this port.
+ */
+ for_each_vi(pi, v, vi) {
+ if (vi->flags & VI_INIT_DONE) {
+
+ for_each_rxq(vi, i, rxq) {
+#if defined(INET) || defined(INET6)
+ rxq->lro.lro_queued = 0;
+ rxq->lro.lro_flushed = 0;
+#endif
+ rxq->rxcsum = 0;
+ rxq->vlan_extraction = 0;
+
+ rxq->fl.mbuf_allocated = 0;
+ rxq->fl.mbuf_inlined = 0;
+ rxq->fl.cl_allocated = 0;
+ rxq->fl.cl_recycled = 0;
+ rxq->fl.cl_fast_recycled = 0;
+ }
+
+ for_each_txq(vi, i, txq) {
+ txq->txcsum = 0;
+ txq->tso_wrs = 0;
+ txq->vlan_insertion = 0;
+ txq->imm_wrs = 0;
+ txq->sgl_wrs = 0;
+ txq->txpkt_wrs = 0;
+ txq->txpkts0_wrs = 0;
+ txq->txpkts1_wrs = 0;
+ txq->txpkts0_pkts = 0;
+ txq->txpkts1_pkts = 0;
+ mp_ring_reset_stats(txq->r);
+ }
+
+#if defined(TCP_OFFLOAD) || defined(RATELIMIT)
+ for_each_ofld_txq(vi, i, wrq) {
+ wrq->tx_wrs_direct = 0;
+ wrq->tx_wrs_copied = 0;
+ }
+#endif
+#ifdef TCP_OFFLOAD
+ for_each_ofld_rxq(vi, i, ofld_rxq) {
+ ofld_rxq->fl.mbuf_allocated = 0;
+ ofld_rxq->fl.mbuf_inlined = 0;
+ ofld_rxq->fl.cl_allocated = 0;
+ ofld_rxq->fl.cl_recycled = 0;
+ ofld_rxq->fl.cl_fast_recycled = 0;
+ }
+#endif
+
+ if (IS_MAIN_VI(vi)) {
+ wrq = &sc->sge.ctrlq[pi->port_id];
+ wrq->tx_wrs_direct = 0;
+ wrq->tx_wrs_copied = 0;
+ }
+ }
+ }
+
+ return (0);
+}
+
int
t4_os_find_pci_capability(struct adapter *sc, int cap)
{
@@ -10040,88 +10142,9 @@ t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t
case CHELSIO_T4_GET_I2C:
rc = read_i2c(sc, (struct t4_i2c_data *)data);
break;
- case CHELSIO_T4_CLEAR_STATS: {
- int i, v, bg_map;
- u_int port_id = *(uint32_t *)data;
- struct port_info *pi;
- struct vi_info *vi;
-
- if (port_id >= sc->params.nports)
- return (EINVAL);
- pi = sc->port[port_id];
- if (pi == NULL)
- return (EIO);
-
- /* MAC stats */
- t4_clr_port_stats(sc, pi->tx_chan);
- pi->tx_parse_error = 0;
- pi->tnl_cong_drops = 0;
- mtx_lock(&sc->reg_lock);
- for_each_vi(pi, v, vi) {
- if (vi->flags & VI_INIT_DONE)
- t4_clr_vi_stats(sc, vi->vin);
- }
- bg_map = pi->mps_bg_map;
- v = 0; /* reuse */
- while (bg_map) {
- i = ffs(bg_map) - 1;
- t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
- 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
- bg_map &= ~(1 << i);
- }
- mtx_unlock(&sc->reg_lock);
-
- /*
- * Since this command accepts a port, clear stats for
- * all VIs on this port.
- */
- for_each_vi(pi, v, vi) {
- if (vi->flags & VI_INIT_DONE) {
- struct sge_rxq *rxq;
- struct sge_txq *txq;
- struct sge_wrq *wrq;
-
- for_each_rxq(vi, i, rxq) {
-#if defined(INET) || defined(INET6)
- rxq->lro.lro_queued = 0;
- rxq->lro.lro_flushed = 0;
-#endif
- rxq->rxcsum = 0;
- rxq->vlan_extraction = 0;
- }
-
- for_each_txq(vi, i, txq) {
- txq->txcsum = 0;
- txq->tso_wrs = 0;
- txq->vlan_insertion = 0;
- txq->imm_wrs = 0;
- txq->sgl_wrs = 0;
- txq->txpkt_wrs = 0;
- txq->txpkts0_wrs = 0;
- txq->txpkts1_wrs = 0;
- txq->txpkts0_pkts = 0;
- txq->txpkts1_pkts = 0;
- mp_ring_reset_stats(txq->r);
- }
-
-#if defined(TCP_OFFLOAD) || defined(RATELIMIT)
- /* nothing to clear for each ofld_rxq */
-
- for_each_ofld_txq(vi, i, wrq) {
- wrq->tx_wrs_direct = 0;
- wrq->tx_wrs_copied = 0;
- }
-#endif
-
- if (IS_MAIN_VI(vi)) {
- wrq = &sc->sge.ctrlq[pi->port_id];
- wrq->tx_wrs_direct = 0;
- wrq->tx_wrs_copied = 0;
- }
- }
- }
+ case CHELSIO_T4_CLEAR_STATS:
+ rc = clear_stats(sc, *(uint32_t *)data);
break;
- }
case CHELSIO_T4_SCHED_CLASS:
rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
break;
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