svn commit: r267418 - in stable/10/sys: amd64/amd64 x86/include

[John Baldwin]

Author: jhb
Date: Thu Jun 12 17:15:56 2014
New Revision: 267418
URL: http://svnweb.freebsd.org/changeset/base/267418

Log:
  MFC 266263,266551,266552:
  - Add definitions for more structured extended features as well as
    XSAVE Extended Features for AVX512 and MPX (Memory Protection Extensions).
  - Don't permit users to request a subset of the AVX512 or MPX xsave masks.

Modified:
  stable/10/sys/amd64/amd64/fpu.c
  stable/10/sys/amd64/amd64/identcpu.c
  stable/10/sys/x86/include/specialreg.h
Directory Properties:
  stable/10/   (props changed)

Modified: stable/10/sys/amd64/amd64/fpu.c
==============================================================================
--- stable/10/sys/amd64/amd64/fpu.c	Thu Jun 12 17:13:35 2014	(r267417)
+++ stable/10/sys/amd64/amd64/fpu.c	Thu Jun 12 17:15:56 2014	(r267418)
@@ -199,6 +199,10 @@ fpuinit_bsp1(void)
 	TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user);
 	xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
 	xsave_mask &= xsave_mask_user;
+	if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
+		xsave_mask &= ~XFEATURE_AVX512;
+	if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
+		xsave_mask &= ~XFEATURE_MPX;
 
 	cpuid_count(0xd, 0x1, cp);
 	if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) {

Modified: stable/10/sys/amd64/amd64/identcpu.c
==============================================================================
--- stable/10/sys/amd64/amd64/identcpu.c	Thu Jun 12 17:13:35 2014	(r267417)
+++ stable/10/sys/amd64/amd64/identcpu.c	Thu Jun 12 17:15:56 2014	(r267418)
@@ -385,11 +385,11 @@ printcpuinfo(void)
 			}
 
 			if (cpu_stdext_feature != 0) {
-				printf("\n  Standard Extended Features=0x%b",
+				printf("\n  Structured Extended Features=0x%b",
 				    cpu_stdext_feature,
 				       "\020"
 				       /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
-				       "\001GSFSBASE"
+				       "\001FSGSBASE"
 				       "\002TSCADJ"
 				       /* Bit Manipulation Instructions */
 				       "\004BMI1"
@@ -401,17 +401,27 @@ printcpuinfo(void)
 				       "\010SMEP"
 				       /* Bit Manipulation Instructions */
 				       "\011BMI2"
-				       "\012ENHMOVSB"
+				       "\012ERMS"
 				       /* Invalidate Processor Context ID */
 				       "\013INVPCID"
 				       /* Restricted Transactional Memory */
 				       "\014RTM"
+				       /* Intel Memory Protection Extensions */
+				       "\017MPX"
+				       /* AVX512 Foundation */
+				       "\021AVX512F"
 				       /* Enhanced NRBG */
 				       "\023RDSEED"
 				       /* ADCX + ADOX */
 				       "\024ADX"
 				       /* Supervisor Mode Access Prevention */
 				       "\025SMAP"
+				       "\030CLFLUSHOPT"
+				       "\032PROCTRACE"
+				       "\033AVX512PF"
+				       "\034AVX512ER"
+				       "\035AVX512CD"
+				       "\036SHA"
 				       );
 			}
 

Modified: stable/10/sys/x86/include/specialreg.h
==============================================================================
--- stable/10/sys/x86/include/specialreg.h	Thu Jun 12 17:13:35 2014	(r267417)
+++ stable/10/sys/x86/include/specialreg.h	Thu Jun 12 17:15:56 2014	(r267418)
@@ -87,12 +87,23 @@
  */
 #define	XCR0	0		/* XFEATURE_ENABLED_MASK register */
 
-#define	XFEATURE_ENABLED_X87	0x00000001
-#define	XFEATURE_ENABLED_SSE	0x00000002
-#define	XFEATURE_ENABLED_AVX	0x00000004
+#define	XFEATURE_ENABLED_X87		0x00000001
+#define	XFEATURE_ENABLED_SSE		0x00000002
+#define	XFEATURE_ENABLED_YMM_HI128	0x00000004
+#define	XFEATURE_ENABLED_AVX		XFEATURE_ENABLED_YMM_HI128
+#define	XFEATURE_ENABLED_BNDREGS	0x00000008
+#define	XFEATURE_ENABLED_BNDCSR		0x00000010
+#define	XFEATURE_ENABLED_OPMASK		0x00000020
+#define	XFEATURE_ENABLED_ZMM_HI256	0x00000040
+#define	XFEATURE_ENABLED_HI16_ZMM	0x00000080
 
 #define	XFEATURE_AVX					\
     (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
+#define	XFEATURE_AVX512						\
+    (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 |	\
+    XFEATURE_ENABLED_HI16_ZMM)
+#define	XFEATURE_MPX					\
+    (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
 
 /*
  * CPUID instruction features register
@@ -308,7 +319,7 @@
 #define	AMDID_COREID_SIZE_SHIFT	12
 
 /*
- * Structured Extended Features
+ * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
  */
 #define	CPUID_STDEXT_FSGSBASE	0x00000001
 #define	CPUID_STDEXT_TSC_ADJUST	0x00000002
@@ -317,12 +328,20 @@
 #define	CPUID_STDEXT_AVX2	0x00000020
 #define	CPUID_STDEXT_SMEP	0x00000080
 #define	CPUID_STDEXT_BMI2	0x00000100
-#define	CPUID_STDEXT_ENH_MOVSB	0x00000200
-#define	CPUID_STDEXT_RTM	0x00000800
+#define	CPUID_STDEXT_ERMS	0x00000200
 #define	CPUID_STDEXT_INVPCID	0x00000400
+#define	CPUID_STDEXT_RTM	0x00000800
+#define	CPUID_STDEXT_MPX	0x00004000
+#define	CPUID_STDEXT_AVX512F	0x00010000
 #define	CPUID_STDEXT_RDSEED	0x00040000
 #define	CPUID_STDEXT_ADX	0x00080000
 #define	CPUID_STDEXT_SMAP	0x00100000
+#define	CPUID_STDEXT_CLFLUSHOPT	0x00800000
+#define	CPUID_STDEXT_PROCTRACE	0x02000000
+#define	CPUID_STDEXT_AVX512PF	0x04000000
+#define	CPUID_STDEXT_AVX512ER	0x08000000
+#define	CPUID_STDEXT_AVX512CD	0x10000000
+#define	CPUID_STDEXT_SHA	0x20000000
 
 /*
  * CPUID manufacturers identifiers