svn commit: r361045 - releng/11.4/usr.sbin/bhyve
John Baldwin
jhb at FreeBSD.org
Thu May 14 19:09:00 UTC 2020
Author: jhb
Date: Thu May 14 19:09:00 2020
New Revision: 361045
URL: https://svnweb.freebsd.org/changeset/base/361045
Log:
MF11 361041:
Update the cached MSI state when any MSI capability register is written.
bhyve uses cached copies of the MSI capability registers to generate
MSI interrupts for device models. Previously, these cached fields
were only set when the MSI capability control register was updated.
The Linux kernel recently adopted a change to deal with races in MSI
interrupt delivery that writes to the MSI capability address and data
registers to alter the destination of MSI interrupts without writing
to the MSI capability control register. bhyve was not updating its
cached registers for these writes and continued to send interrupts
with the old data value to the old address. Fix this by recomputing
the cached values for every write to any MSI capability register.
Approved by: re (gjb)
Modified:
releng/11.4/usr.sbin/bhyve/pci_emul.c
Directory Properties:
releng/11.4/ (props changed)
Modified: releng/11.4/usr.sbin/bhyve/pci_emul.c
==============================================================================
--- releng/11.4/usr.sbin/bhyve/pci_emul.c Thu May 14 18:59:34 2020 (r361044)
+++ releng/11.4/usr.sbin/bhyve/pci_emul.c Thu May 14 19:09:00 2020 (r361045)
@@ -898,26 +898,26 @@ msicap_cfgwrite(struct pci_devinst *pi, int capoff, in
msgctrl &= ~rwmask;
msgctrl |= val & rwmask;
val = msgctrl;
+ }
+ CFGWRITE(pi, offset, val, bytes);
- addrlo = pci_get_cfgdata32(pi, capoff + 4);
- if (msgctrl & PCIM_MSICTRL_64BIT)
- msgdata = pci_get_cfgdata16(pi, capoff + 12);
- else
- msgdata = pci_get_cfgdata16(pi, capoff + 8);
+ msgctrl = pci_get_cfgdata16(pi, capoff + 2);
+ addrlo = pci_get_cfgdata32(pi, capoff + 4);
+ if (msgctrl & PCIM_MSICTRL_64BIT)
+ msgdata = pci_get_cfgdata16(pi, capoff + 12);
+ else
+ msgdata = pci_get_cfgdata16(pi, capoff + 8);
- mme = msgctrl & PCIM_MSICTRL_MME_MASK;
- pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
- if (pi->pi_msi.enabled) {
- pi->pi_msi.addr = addrlo;
- pi->pi_msi.msg_data = msgdata;
- pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
- } else {
- pi->pi_msi.maxmsgnum = 0;
- }
- pci_lintr_update(pi);
+ mme = msgctrl & PCIM_MSICTRL_MME_MASK;
+ pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
+ if (pi->pi_msi.enabled) {
+ pi->pi_msi.addr = addrlo;
+ pi->pi_msi.msg_data = msgdata;
+ pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
+ } else {
+ pi->pi_msi.maxmsgnum = 0;
}
-
- CFGWRITE(pi, offset, val, bytes);
+ pci_lintr_update(pi);
}
void
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