svn commit: r364264 - in projects/clang1100-import: sbin/fsck_ffs sys/arm64/arm64 sys/arm64/include sys/contrib/pcg-c/include sys/kern sys/net sys/riscv/riscv
Dimitry Andric
dim at FreeBSD.org
Sat Aug 15 22:59:45 UTC 2020
Author: dim
Date: Sat Aug 15 22:59:44 2020
New Revision: 364264
URL: https://svnweb.freebsd.org/changeset/base/364264
Log:
Merge ^/head r364251 through r364263.
Modified:
projects/clang1100-import/sbin/fsck_ffs/main.c
projects/clang1100-import/sys/arm64/arm64/identcpu.c
projects/clang1100-import/sys/arm64/include/armreg.h
projects/clang1100-import/sys/contrib/pcg-c/include/pcg_variants.h
projects/clang1100-import/sys/kern/subr_witness.c
projects/clang1100-import/sys/net/if_vxlan.c
projects/clang1100-import/sys/riscv/riscv/machdep.c
Directory Properties:
projects/clang1100-import/ (props changed)
Modified: projects/clang1100-import/sbin/fsck_ffs/main.c
==============================================================================
--- projects/clang1100-import/sbin/fsck_ffs/main.c Sat Aug 15 22:58:07 2020 (r364263)
+++ projects/clang1100-import/sbin/fsck_ffs/main.c Sat Aug 15 22:59:44 2020 (r364264)
@@ -61,6 +61,7 @@ __FBSDID("$FreeBSD$");
#include <fstab.h>
#include <grp.h>
#include <inttypes.h>
+#include <libufs.h>
#include <mntopts.h>
#include <paths.h>
#include <stdint.h>
@@ -604,10 +605,8 @@ checkfilesys(char *filesys)
/*
* Write out the duplicate super blocks
*/
- for (cylno = 0; cylno < sblock.fs_ncg; cylno++)
- blwrite(fswritefd, (char *)&sblock,
- fsbtodb(&sblock, cgsblock(&sblock, cylno)),
- SBLOCKSIZE);
+ if (sbput(fswritefd, &sblock, sblock.fs_ncg) == 0)
+ fsmodified = 1;
}
if (rerun)
resolved = 0;
Modified: projects/clang1100-import/sys/arm64/arm64/identcpu.c
==============================================================================
--- projects/clang1100-import/sys/arm64/arm64/identcpu.c Sat Aug 15 22:58:07 2020 (r364263)
+++ projects/clang1100-import/sys/arm64/arm64/identcpu.c Sat Aug 15 22:59:44 2020 (r364264)
@@ -47,7 +47,7 @@ __FBSDID("$FreeBSD$");
#include <machine/elf.h>
static void print_cpu_features(u_int cpu);
-static u_long parse_cpu_features_hwcap(u_int cpu);
+static u_long parse_cpu_features_hwcap(void);
char machine[] = "arm64";
@@ -364,6 +364,31 @@ static struct mrs_field id_aa64dfr1_fields[] = {
/* ID_AA64ISAR0_EL1 */
+static struct mrs_field_value id_aa64isar0_rndr[] = {
+ MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_IMPL, "RNG"),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar0_tlb[] = {
+ MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOS, "TLBI-OS"),
+ MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOSR, "TLBI-OSR"),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar0_ts[] = {
+ MRS_FIELD_VALUE(ID_AA64ISAR0_TS_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_4, "CondM-8.4"),
+ MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_5, "CondM-8.5"),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar0_fhm[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, FHM, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
static struct mrs_field_value id_aa64isar0_dp[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, DP, NONE, IMPL),
MRS_FIELD_VALUE_END,
@@ -417,6 +442,10 @@ static struct mrs_field_value id_aa64isar0_aes[] = {
};
static struct mrs_field id_aa64isar0_fields[] = {
+ MRS_FIELD(ID_AA64ISAR0, RNDR, false, MRS_LOWER, id_aa64isar0_rndr),
+ MRS_FIELD(ID_AA64ISAR0, TLB, false, MRS_LOWER, id_aa64isar0_tlb),
+ MRS_FIELD(ID_AA64ISAR0, TS, false, MRS_LOWER, id_aa64isar0_ts),
+ MRS_FIELD(ID_AA64ISAR0, FHM, false, MRS_LOWER, id_aa64isar0_fhm),
MRS_FIELD(ID_AA64ISAR0, DP, false, MRS_LOWER, id_aa64isar0_dp),
MRS_FIELD(ID_AA64ISAR0, SM4, false, MRS_LOWER, id_aa64isar0_sm4),
MRS_FIELD(ID_AA64ISAR0, SM3, false, MRS_LOWER, id_aa64isar0_sm3),
@@ -432,6 +461,37 @@ static struct mrs_field id_aa64isar0_fields[] = {
/* ID_AA64ISAR1_EL1 */
+static struct mrs_field_value id_aa64isar1_i8mm[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar1_dgh[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, DGH, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar1_bf16[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar1_specres[] = {
+ MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_IMPL, "PredInv"),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar1_sb[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, SB, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64isar1_frintts[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FRINTTS, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
static struct mrs_field_value id_aa64isar1_gpi[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPI, NONE, IMPL),
MRS_FIELD_VALUE_END,
@@ -443,7 +503,9 @@ static struct mrs_field_value id_aa64isar1_gpa[] = {
};
static struct mrs_field_value id_aa64isar1_lrcpc[] = {
- MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, LRCPC, NONE, IMPL),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_3, "RCPC-8.3"),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_4, "RCPC-8.4"),
MRS_FIELD_VALUE_END,
};
@@ -463,16 +525,26 @@ static struct mrs_field_value id_aa64isar1_api[] = {
};
static struct mrs_field_value id_aa64isar1_apa[] = {
- MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPA, NONE, IMPL),
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, APA, NONE, IMPL),
MRS_FIELD_VALUE_END,
};
static struct mrs_field_value id_aa64isar1_dpb[] = {
- MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, DPB, NONE, IMPL),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_NONE, ""),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVAP, "DCPoP"),
+ MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVADP, "DCCVADP"),
MRS_FIELD_VALUE_END,
};
static struct mrs_field id_aa64isar1_fields[] = {
+ MRS_FIELD(ID_AA64ISAR1, I8MM, false, MRS_LOWER, id_aa64isar1_i8mm),
+ MRS_FIELD(ID_AA64ISAR1, DGH, false, MRS_LOWER, id_aa64isar1_dgh),
+ MRS_FIELD(ID_AA64ISAR1, BF16, false, MRS_LOWER, id_aa64isar1_bf16),
+ MRS_FIELD(ID_AA64ISAR1, SPECRES, false, MRS_LOWER,
+ id_aa64isar1_specres),
+ MRS_FIELD(ID_AA64ISAR1, SB, false, MRS_LOWER, id_aa64isar1_sb),
+ MRS_FIELD(ID_AA64ISAR1, FRINTTS, false, MRS_LOWER,
+ id_aa64isar1_frintts),
MRS_FIELD(ID_AA64ISAR1, GPI, false, MRS_EXACT, id_aa64isar1_gpi),
MRS_FIELD(ID_AA64ISAR1, GPA, false, MRS_EXACT, id_aa64isar1_gpa),
MRS_FIELD(ID_AA64ISAR1, LRCPC, false, MRS_LOWER, id_aa64isar1_lrcpc),
@@ -1023,7 +1095,7 @@ update_special_regs(u_int cpu)
for (j = 0; fields[j].type != 0; j++) {
switch (fields[j].type & MRS_TYPE_MASK) {
case MRS_EXACT:
- user_reg &= ~(0xfu << fields[j].shift);
+ user_reg &= ~(0xful << fields[j].shift);
user_reg |=
(uint64_t)MRS_EXACT_FIELD(fields[j].type) <<
fields[j].shift;
@@ -1059,7 +1131,6 @@ static void
identify_cpu_sysinit(void *dummy __unused)
{
int cpu;
- u_long hwcap;
bool dic, idc;
dic = (allow_dic != 0);
@@ -1067,11 +1138,6 @@ identify_cpu_sysinit(void *dummy __unused)
CPU_FOREACH(cpu) {
check_cpu_regs(cpu);
- hwcap = parse_cpu_features_hwcap(cpu);
- if (elf_hwcap == 0)
- elf_hwcap = hwcap;
- else
- elf_hwcap &= hwcap;
if (cpu != 0)
update_special_regs(cpu);
@@ -1081,6 +1147,9 @@ identify_cpu_sysinit(void *dummy __unused)
idc = false;
}
+ /* Exposed to userspace as AT_HWCAP */
+ elf_hwcap = parse_cpu_features_hwcap();
+
if (dic && idc) {
arm64_icache_sync_range = &arm64_dic_idc_icache_sync_range;
if (bootverbose)
@@ -1112,43 +1181,49 @@ cpu_features_sysinit(void *dummy __unused)
SYSINIT(cpu_features, SI_SUB_SMP, SI_ORDER_ANY, cpu_features_sysinit, NULL);
static u_long
-parse_cpu_features_hwcap(u_int cpu)
+parse_cpu_features_hwcap(void)
{
u_long hwcap = 0;
- if (ID_AA64ISAR0_DP_VAL(cpu_desc[cpu].id_aa64isar0) == ID_AA64ISAR0_DP_IMPL)
+ if (ID_AA64ISAR0_DP_VAL(user_cpu_desc.id_aa64isar0) ==
+ ID_AA64ISAR0_DP_IMPL)
hwcap |= HWCAP_ASIMDDP;
- if (ID_AA64ISAR0_SM4_VAL(cpu_desc[cpu].id_aa64isar0) == ID_AA64ISAR0_SM4_IMPL)
+ if (ID_AA64ISAR0_SM4_VAL(user_cpu_desc.id_aa64isar0) ==
+ ID_AA64ISAR0_SM4_IMPL)
hwcap |= HWCAP_SM4;
- if (ID_AA64ISAR0_SM3_VAL(cpu_desc[cpu].id_aa64isar0) == ID_AA64ISAR0_SM3_IMPL)
+ if (ID_AA64ISAR0_SM3_VAL(user_cpu_desc.id_aa64isar0) ==
+ ID_AA64ISAR0_SM3_IMPL)
hwcap |= HWCAP_SM3;
- if (ID_AA64ISAR0_RDM_VAL(cpu_desc[cpu].id_aa64isar0) == ID_AA64ISAR0_RDM_IMPL)
+ if (ID_AA64ISAR0_RDM_VAL(user_cpu_desc.id_aa64isar0) ==
+ ID_AA64ISAR0_RDM_IMPL)
hwcap |= HWCAP_ASIMDRDM;
- if (ID_AA64ISAR0_Atomic_VAL(cpu_desc[cpu].id_aa64isar0) == ID_AA64ISAR0_Atomic_IMPL)
+ if (ID_AA64ISAR0_Atomic_VAL(user_cpu_desc.id_aa64isar0) ==
+ ID_AA64ISAR0_Atomic_IMPL)
hwcap |= HWCAP_ATOMICS;
- if (ID_AA64ISAR0_CRC32_VAL(cpu_desc[cpu].id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)
+ if (ID_AA64ISAR0_CRC32_VAL(user_cpu_desc.id_aa64isar0) ==
+ ID_AA64ISAR0_CRC32_BASE)
hwcap |= HWCAP_CRC32;
- switch (ID_AA64ISAR0_SHA2_VAL(cpu_desc[cpu].id_aa64isar0)) {
- case ID_AA64ISAR0_SHA2_BASE:
- hwcap |= HWCAP_SHA2;
- break;
- case ID_AA64ISAR0_SHA2_512:
- hwcap |= HWCAP_SHA2 | HWCAP_SHA512;
- break;
+ switch (ID_AA64ISAR0_SHA2_VAL(user_cpu_desc.id_aa64isar0)) {
+ case ID_AA64ISAR0_SHA2_BASE:
+ hwcap |= HWCAP_SHA2;
+ break;
+ case ID_AA64ISAR0_SHA2_512:
+ hwcap |= HWCAP_SHA2 | HWCAP_SHA512;
+ break;
default:
break;
}
- if (ID_AA64ISAR0_SHA1_VAL(cpu_desc[cpu].id_aa64isar0))
+ if (ID_AA64ISAR0_SHA1_VAL(user_cpu_desc.id_aa64isar0))
hwcap |= HWCAP_SHA1;
- switch (ID_AA64ISAR0_AES_VAL(cpu_desc[cpu].id_aa64isar0)) {
+ switch (ID_AA64ISAR0_AES_VAL(user_cpu_desc.id_aa64isar0)) {
case ID_AA64ISAR0_AES_BASE:
hwcap |= HWCAP_AES;
break;
@@ -1159,22 +1234,27 @@ parse_cpu_features_hwcap(u_int cpu)
break;
}
- if (ID_AA64ISAR1_LRCPC_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_LRCPC_IMPL)
+ if (ID_AA64ISAR1_LRCPC_VAL(user_cpu_desc.id_aa64isar1) ==
+ ID_AA64ISAR1_LRCPC_RCPC_8_3)
hwcap |= HWCAP_LRCPC;
- if (ID_AA64ISAR1_FCMA_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_FCMA_IMPL)
+ if (ID_AA64ISAR1_FCMA_VAL(user_cpu_desc.id_aa64isar1) ==
+ ID_AA64ISAR1_FCMA_IMPL)
hwcap |= HWCAP_FCMA;
- if (ID_AA64ISAR1_JSCVT_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_JSCVT_IMPL)
+ if (ID_AA64ISAR1_JSCVT_VAL(user_cpu_desc.id_aa64isar1) ==
+ ID_AA64ISAR1_JSCVT_IMPL)
hwcap |= HWCAP_JSCVT;
- if (ID_AA64ISAR1_DPB_VAL(cpu_desc[cpu].id_aa64isar1) == ID_AA64ISAR1_DPB_IMPL)
+ if (ID_AA64ISAR1_DPB_VAL(user_cpu_desc.id_aa64isar1) ==
+ ID_AA64ISAR1_DPB_DCCVAP)
hwcap |= HWCAP_DCPOP;
- if (ID_AA64PFR0_SVE_VAL(cpu_desc[cpu].id_aa64pfr0) == ID_AA64PFR0_SVE_IMPL)
+ if (ID_AA64PFR0_SVE_VAL(user_cpu_desc.id_aa64pfr0) ==
+ ID_AA64PFR0_SVE_IMPL)
hwcap |= HWCAP_SVE;
- switch (ID_AA64PFR0_AdvSIMD_VAL(cpu_desc[cpu].id_aa64pfr0)) {
+ switch (ID_AA64PFR0_AdvSIMD_VAL(user_cpu_desc.id_aa64pfr0)) {
case ID_AA64PFR0_AdvSIMD_IMPL:
hwcap |= HWCAP_ASIMD;
break;
@@ -1185,7 +1265,7 @@ parse_cpu_features_hwcap(u_int cpu)
break;
}
- switch (ID_AA64PFR0_FP_VAL(cpu_desc[cpu].id_aa64pfr0)) {
+ switch (ID_AA64PFR0_FP_VAL(user_cpu_desc.id_aa64pfr0)) {
case ID_AA64PFR0_FP_IMPL:
hwcap |= HWCAP_FP;
break;
Modified: projects/clang1100-import/sys/arm64/include/armreg.h
==============================================================================
--- projects/clang1100-import/sys/arm64/include/armreg.h Sat Aug 15 22:58:07 2020 (r364263)
+++ projects/clang1100-import/sys/arm64/include/armreg.h Sat Aug 15 22:59:44 2020 (r364264)
@@ -350,6 +350,28 @@
#define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK)
#define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT)
#define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT)
+#define ID_AA64ISAR0_FHM_SHIFT 48
+#define ID_AA64ISAR0_FHM_MASK (UL(0xf) << ID_AA64ISAR0_FHM_SHIFT)
+#define ID_AA64ISAR0_FHM_VAL(x) ((x) & ID_AA64ISAR0_FHM_MASK)
+#define ID_AA64ISAR0_FHM_NONE (UL(0x0) << ID_AA64ISAR0_FHM_SHIFT)
+#define ID_AA64ISAR0_FHM_IMPL (UL(0x1) << ID_AA64ISAR0_FHM_SHIFT)
+#define ID_AA64ISAR0_TS_SHIFT 52
+#define ID_AA64ISAR0_TS_MASK (UL(0xf) << ID_AA64ISAR0_TS_SHIFT)
+#define ID_AA64ISAR0_TS_VAL(x) ((x) & ID_AA64ISAR0_TS_MASK)
+#define ID_AA64ISAR0_TS_NONE (UL(0x0) << ID_AA64ISAR0_TS_SHIFT)
+#define ID_AA64ISAR0_TS_CondM_8_4 (UL(0x1) << ID_AA64ISAR0_TS_SHIFT)
+#define ID_AA64ISAR0_TS_CondM_8_5 (UL(0x2) << ID_AA64ISAR0_TS_SHIFT)
+#define ID_AA64ISAR0_TLB_SHIFT 56
+#define ID_AA64ISAR0_TLB_MASK (UL(0xf) << ID_AA64ISAR0_TLB_SHIFT)
+#define ID_AA64ISAR0_TLB_VAL(x) ((x) & ID_AA64ISAR0_TLB_MASK)
+#define ID_AA64ISAR0_TLB_NONE (UL(0x0) << ID_AA64ISAR0_TLB_SHIFT)
+#define ID_AA64ISAR0_TLB_TLBIOS (UL(0x1) << ID_AA64ISAR0_TLB_SHIFT)
+#define ID_AA64ISAR0_TLB_TLBIOSR (UL(0x2) << ID_AA64ISAR0_TLB_SHIFT)
+#define ID_AA64ISAR0_RNDR_SHIFT 60
+#define ID_AA64ISAR0_RNDR_MASK (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT)
+#define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK)
+#define ID_AA64ISAR0_RNDR_NONE (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT)
+#define ID_AA64ISAR0_RNDR_IMPL (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT)
/* ID_AA64ISAR1_EL1 */
#define ID_AA64ISAR1_EL1 MRS_REG(3, 0, 0, 6, 1)
@@ -357,7 +379,8 @@
#define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK)
#define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT)
-#define ID_AA64ISAR1_DPB_IMPL (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT)
+#define ID_AA64ISAR1_DPB_DCCVAP (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT)
+#define ID_AA64ISAR1_DPB_DCCVADP (UL(0x2) << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_APA_SHIFT 4
#define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK)
@@ -382,7 +405,8 @@
#define ID_AA64ISAR1_LRCPC_MASK (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK)
#define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT)
-#define ID_AA64ISAR1_LRCPC_IMPL (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT)
+#define ID_AA64ISAR1_LRCPC_RCPC_8_3 (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT)
+#define ID_AA64ISAR1_LRCPC_RCPC_8_4 (UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_GPA_SHIFT 24
#define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT)
#define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK)
@@ -393,6 +417,36 @@
#define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK)
#define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT)
#define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT)
+#define ID_AA64ISAR1_FRINTTS_SHIFT 32
+#define ID_AA64ISAR1_FRINTTS_MASK (UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT)
+#define ID_AA64ISAR1_FRINTTS_VAL(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK)
+#define ID_AA64ISAR1_FRINTTS_NONE (UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT)
+#define ID_AA64ISAR1_FRINTTS_IMPL (UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT)
+#define ID_AA64ISAR1_SB_SHIFT 36
+#define ID_AA64ISAR1_SB_MASK (UL(0xf) << ID_AA64ISAR1_SB_SHIFT)
+#define ID_AA64ISAR1_SB_VAL(x) ((x) & ID_AA64ISAR1_SB_MASK)
+#define ID_AA64ISAR1_SB_NONE (UL(0x0) << ID_AA64ISAR1_SB_SHIFT)
+#define ID_AA64ISAR1_SB_IMPL (UL(0x1) << ID_AA64ISAR1_SB_SHIFT)
+#define ID_AA64ISAR1_SPECRES_SHIFT 40
+#define ID_AA64ISAR1_SPECRES_MASK (UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT)
+#define ID_AA64ISAR1_SPECRES_VAL(x) ((x) & ID_AA64ISAR1_SPECRES_MASK)
+#define ID_AA64ISAR1_SPECRES_NONE (UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT)
+#define ID_AA64ISAR1_SPECRES_IMPL (UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT)
+#define ID_AA64ISAR1_BF16_SHIFT 44
+#define ID_AA64ISAR1_BF16_MASK (UL(0xf) << ID_AA64ISAR1_BF16_SHIFT)
+#define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK)
+#define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT)
+#define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT)
+#define ID_AA64ISAR1_DGH_SHIFT 48
+#define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT)
+#define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK)
+#define ID_AA64ISAR1_DGH_NONE (UL(0x0) << ID_AA64ISAR1_DGH_SHIFT)
+#define ID_AA64ISAR1_DGH_IMPL (UL(0x1) << ID_AA64ISAR1_DGH_SHIFT)
+#define ID_AA64ISAR1_I8MM_SHIFT 52
+#define ID_AA64ISAR1_I8MM_MASK (UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT)
+#define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK)
+#define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT)
+#define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT)
/* ID_AA64MMFR0_EL1 */
#define ID_AA64MMFR0_EL1 MRS_REG(3, 0, 0, 7, 0)
Modified: projects/clang1100-import/sys/contrib/pcg-c/include/pcg_variants.h
==============================================================================
--- projects/clang1100-import/sys/contrib/pcg-c/include/pcg_variants.h Sat Aug 15 22:58:07 2020 (r364263)
+++ projects/clang1100-import/sys/contrib/pcg-c/include/pcg_variants.h Sat Aug 15 22:59:44 2020 (r364264)
@@ -53,7 +53,7 @@ extern "C" {
* Rotate helper functions.
*/
-inline uint8_t pcg_rotr_8(uint8_t value, unsigned int rot)
+static inline uint8_t pcg_rotr_8(uint8_t value, unsigned int rot)
{
/* Unfortunately, clang is kinda pathetic when it comes to properly
* recognizing idiomatic rotate code, so for clang we actually provide
@@ -67,7 +67,7 @@ inline uint8_t pcg_rotr_8(uint8_t value, unsigned int
#endif
}
-inline uint16_t pcg_rotr_16(uint16_t value, unsigned int rot)
+static inline uint16_t pcg_rotr_16(uint16_t value, unsigned int rot)
{
#if PCG_USE_INLINE_ASM && defined(__clang__) && (defined(__x86_64__) || defined(__i386__))
__asm__ ("rorw %%cl, %0" : "=r" (value) : "0" (value), "c" (rot));
@@ -77,7 +77,7 @@ inline uint16_t pcg_rotr_16(uint16_t value, unsigned i
#endif
}
-inline uint32_t pcg_rotr_32(uint32_t value, unsigned int rot)
+static inline uint32_t pcg_rotr_32(uint32_t value, unsigned int rot)
{
#if PCG_USE_INLINE_ASM && defined(__clang__) && (defined(__x86_64__) || defined(__i386__))
__asm__ ("rorl %%cl, %0" : "=r" (value) : "0" (value), "c" (rot));
@@ -87,7 +87,7 @@ inline uint32_t pcg_rotr_32(uint32_t value, unsigned i
#endif
}
-inline uint64_t pcg_rotr_64(uint64_t value, unsigned int rot)
+static inline uint64_t pcg_rotr_64(uint64_t value, unsigned int rot)
{
#if 0 && PCG_USE_INLINE_ASM && defined(__clang__) && (defined(__x86_64__) || defined(__i386__))
/* For whatever reason, clang actually *does* generate rotq by
@@ -100,7 +100,7 @@ inline uint64_t pcg_rotr_64(uint64_t value, unsigned i
}
#if PCG_HAS_128BIT_OPS
-inline pcg128_t pcg_rotr_128(pcg128_t value, unsigned int rot)
+static inline pcg128_t pcg_rotr_128(pcg128_t value, unsigned int rot)
{
return (value >> rot) | (value << ((- rot) & 127));
}
@@ -112,24 +112,24 @@ inline pcg128_t pcg_rotr_128(pcg128_t value, unsigned
/* XSH RS */
-inline uint8_t pcg_output_xsh_rs_16_8(uint16_t state)
+static inline uint8_t pcg_output_xsh_rs_16_8(uint16_t state)
{
return (uint8_t)(((state >> 7u) ^ state) >> ((state >> 14u) + 3u));
}
-inline uint16_t pcg_output_xsh_rs_32_16(uint32_t state)
+static inline uint16_t pcg_output_xsh_rs_32_16(uint32_t state)
{
return (uint16_t)(((state >> 11u) ^ state) >> ((state >> 30u) + 11u));
}
-inline uint32_t pcg_output_xsh_rs_64_32(uint64_t state)
+static inline uint32_t pcg_output_xsh_rs_64_32(uint64_t state)
{
return (uint32_t)(((state >> 22u) ^ state) >> ((state >> 61u) + 22u));
}
#if PCG_HAS_128BIT_OPS
-inline uint64_t pcg_output_xsh_rs_128_64(pcg128_t state)
+static inline uint64_t pcg_output_xsh_rs_128_64(pcg128_t state)
{
return (uint64_t)(((state >> 43u) ^ state) >> ((state >> 124u) + 45u));
}
@@ -137,23 +137,23 @@ inline uint64_t pcg_output_xsh_rs_128_64(pcg128_t stat
/* XSH RR */
-inline uint8_t pcg_output_xsh_rr_16_8(uint16_t state)
+static inline uint8_t pcg_output_xsh_rr_16_8(uint16_t state)
{
return pcg_rotr_8(((state >> 5u) ^ state) >> 5u, state >> 13u);
}
-inline uint16_t pcg_output_xsh_rr_32_16(uint32_t state)
+static inline uint16_t pcg_output_xsh_rr_32_16(uint32_t state)
{
return pcg_rotr_16(((state >> 10u) ^ state) >> 12u, state >> 28u);
}
-inline uint32_t pcg_output_xsh_rr_64_32(uint64_t state)
+static inline uint32_t pcg_output_xsh_rr_64_32(uint64_t state)
{
return pcg_rotr_32(((state >> 18u) ^ state) >> 27u, state >> 59u);
}
#if PCG_HAS_128BIT_OPS
-inline uint64_t pcg_output_xsh_rr_128_64(pcg128_t state)
+static inline uint64_t pcg_output_xsh_rr_128_64(pcg128_t state)
{
return pcg_rotr_64(((state >> 35u) ^ state) >> 58u, state >> 122u);
}
@@ -161,25 +161,25 @@ inline uint64_t pcg_output_xsh_rr_128_64(pcg128_t stat
/* RXS M XS */
-inline uint8_t pcg_output_rxs_m_xs_8_8(uint8_t state)
+static inline uint8_t pcg_output_rxs_m_xs_8_8(uint8_t state)
{
uint8_t word = ((state >> ((state >> 6u) + 2u)) ^ state) * 217u;
return (word >> 6u) ^ word;
}
-inline uint16_t pcg_output_rxs_m_xs_16_16(uint16_t state)
+static inline uint16_t pcg_output_rxs_m_xs_16_16(uint16_t state)
{
uint16_t word = ((state >> ((state >> 13u) + 3u)) ^ state) * 62169u;
return (word >> 11u) ^ word;
}
-inline uint32_t pcg_output_rxs_m_xs_32_32(uint32_t state)
+static inline uint32_t pcg_output_rxs_m_xs_32_32(uint32_t state)
{
uint32_t word = ((state >> ((state >> 28u) + 4u)) ^ state) * 277803737u;
return (word >> 22u) ^ word;
}
-inline uint64_t pcg_output_rxs_m_xs_64_64(uint64_t state)
+static inline uint64_t pcg_output_rxs_m_xs_64_64(uint64_t state)
{
uint64_t word = ((state >> ((state >> 59u) + 5u)) ^ state)
* 12605985483714917081ull;
@@ -187,7 +187,7 @@ inline uint64_t pcg_output_rxs_m_xs_64_64(uint64_t sta
}
#if PCG_HAS_128BIT_OPS
-inline pcg128_t pcg_output_rxs_m_xs_128_128(pcg128_t state)
+static inline pcg128_t pcg_output_rxs_m_xs_128_128(pcg128_t state)
{
pcg128_t word = ((state >> ((state >> 122u) + 6u)) ^ state)
* (PCG_128BIT_CONSTANT(17766728186571221404ULL,
@@ -199,24 +199,24 @@ inline pcg128_t pcg_output_rxs_m_xs_128_128(pcg128_t s
/* RXS M */
-inline uint8_t pcg_output_rxs_m_16_8(uint16_t state)
+static inline uint8_t pcg_output_rxs_m_16_8(uint16_t state)
{
return (((state >> ((state >> 13u) + 3u)) ^ state) * 62169u) >> 8u;
}
-inline uint16_t pcg_output_rxs_m_32_16(uint32_t state)
+static inline uint16_t pcg_output_rxs_m_32_16(uint32_t state)
{
return (((state >> ((state >> 28u) + 4u)) ^ state) * 277803737u) >> 16u;
}
-inline uint32_t pcg_output_rxs_m_64_32(uint64_t state)
+static inline uint32_t pcg_output_rxs_m_64_32(uint64_t state)
{
return (((state >> ((state >> 59u) + 5u)) ^ state)
* 12605985483714917081ull) >> 32u;
}
#if PCG_HAS_128BIT_OPS
-inline uint64_t pcg_output_rxs_m_128_64(pcg128_t state)
+static inline uint64_t pcg_output_rxs_m_128_64(pcg128_t state)
{
return (((state >> ((state >> 122u) + 6u)) ^ state)
* (PCG_128BIT_CONSTANT(17766728186571221404ULL,
@@ -227,14 +227,14 @@ inline uint64_t pcg_output_rxs_m_128_64(pcg128_t state
/* XSL RR (only defined for >= 64 bits) */
-inline uint32_t pcg_output_xsl_rr_64_32(uint64_t state)
+static inline uint32_t pcg_output_xsl_rr_64_32(uint64_t state)
{
return pcg_rotr_32(((uint32_t)(state >> 32u)) ^ (uint32_t)state,
state >> 59u);
}
#if PCG_HAS_128BIT_OPS
-inline uint64_t pcg_output_xsl_rr_128_64(pcg128_t state)
+static inline uint64_t pcg_output_xsl_rr_128_64(pcg128_t state)
{
return pcg_rotr_64(((uint64_t)(state >> 64u)) ^ (uint64_t)state,
state >> 122u);
@@ -243,7 +243,7 @@ inline uint64_t pcg_output_xsl_rr_128_64(pcg128_t stat
/* XSL RR RR (only defined for >= 64 bits) */
-inline uint64_t pcg_output_xsl_rr_rr_64_64(uint64_t state)
+static inline uint64_t pcg_output_xsl_rr_rr_64_64(uint64_t state)
{
uint32_t rot1 = (uint32_t)(state >> 59u);
uint32_t high = (uint32_t)(state >> 32u);
@@ -255,7 +255,7 @@ inline uint64_t pcg_output_xsl_rr_rr_64_64(uint64_t st
}
#if PCG_HAS_128BIT_OPS
-inline pcg128_t pcg_output_xsl_rr_rr_128_128(pcg128_t state)
+static inline pcg128_t pcg_output_xsl_rr_rr_128_128(pcg128_t state)
{
uint32_t rot1 = (uint32_t)(state >> 122u);
uint64_t high = (uint64_t)(state >> 64u);
@@ -400,191 +400,191 @@ extern pcg128_t pcg_advance_lcg_128(pcg128_t state, pc
* a good reason to call them directly.
*/
-inline void pcg_oneseq_8_step_r(struct pcg_state_8* rng)
+static inline void pcg_oneseq_8_step_r(struct pcg_state_8* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_8
+ PCG_DEFAULT_INCREMENT_8;
}
-inline void pcg_oneseq_8_advance_r(struct pcg_state_8* rng, uint8_t delta)
+static inline void pcg_oneseq_8_advance_r(struct pcg_state_8* rng, uint8_t delta)
{
rng->state = pcg_advance_lcg_8(rng->state, delta, PCG_DEFAULT_MULTIPLIER_8,
PCG_DEFAULT_INCREMENT_8);
}
-inline void pcg_mcg_8_step_r(struct pcg_state_8* rng)
+static inline void pcg_mcg_8_step_r(struct pcg_state_8* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_8;
}
-inline void pcg_mcg_8_advance_r(struct pcg_state_8* rng, uint8_t delta)
+static inline void pcg_mcg_8_advance_r(struct pcg_state_8* rng, uint8_t delta)
{
rng->state
= pcg_advance_lcg_8(rng->state, delta, PCG_DEFAULT_MULTIPLIER_8, 0u);
}
-inline void pcg_unique_8_step_r(struct pcg_state_8* rng)
+static inline void pcg_unique_8_step_r(struct pcg_state_8* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_8
+ (uint8_t)(((intptr_t)rng) | 1u);
}
-inline void pcg_unique_8_advance_r(struct pcg_state_8* rng, uint8_t delta)
+static inline void pcg_unique_8_advance_r(struct pcg_state_8* rng, uint8_t delta)
{
rng->state = pcg_advance_lcg_8(rng->state, delta, PCG_DEFAULT_MULTIPLIER_8,
(uint8_t)(((intptr_t)rng) | 1u));
}
-inline void pcg_setseq_8_step_r(struct pcg_state_setseq_8* rng)
+static inline void pcg_setseq_8_step_r(struct pcg_state_setseq_8* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_8 + rng->inc;
}
-inline void pcg_setseq_8_advance_r(struct pcg_state_setseq_8* rng,
+static inline void pcg_setseq_8_advance_r(struct pcg_state_setseq_8* rng,
uint8_t delta)
{
rng->state = pcg_advance_lcg_8(rng->state, delta, PCG_DEFAULT_MULTIPLIER_8,
rng->inc);
}
-inline void pcg_oneseq_16_step_r(struct pcg_state_16* rng)
+static inline void pcg_oneseq_16_step_r(struct pcg_state_16* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_16
+ PCG_DEFAULT_INCREMENT_16;
}
-inline void pcg_oneseq_16_advance_r(struct pcg_state_16* rng, uint16_t delta)
+static inline void pcg_oneseq_16_advance_r(struct pcg_state_16* rng, uint16_t delta)
{
rng->state = pcg_advance_lcg_16(
rng->state, delta, PCG_DEFAULT_MULTIPLIER_16, PCG_DEFAULT_INCREMENT_16);
}
-inline void pcg_mcg_16_step_r(struct pcg_state_16* rng)
+static inline void pcg_mcg_16_step_r(struct pcg_state_16* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_16;
}
-inline void pcg_mcg_16_advance_r(struct pcg_state_16* rng, uint16_t delta)
+static inline void pcg_mcg_16_advance_r(struct pcg_state_16* rng, uint16_t delta)
{
rng->state
= pcg_advance_lcg_16(rng->state, delta, PCG_DEFAULT_MULTIPLIER_16, 0u);
}
-inline void pcg_unique_16_step_r(struct pcg_state_16* rng)
+static inline void pcg_unique_16_step_r(struct pcg_state_16* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_16
+ (uint16_t)(((intptr_t)rng) | 1u);
}
-inline void pcg_unique_16_advance_r(struct pcg_state_16* rng, uint16_t delta)
+static inline void pcg_unique_16_advance_r(struct pcg_state_16* rng, uint16_t delta)
{
rng->state
= pcg_advance_lcg_16(rng->state, delta, PCG_DEFAULT_MULTIPLIER_16,
(uint16_t)(((intptr_t)rng) | 1u));
}
-inline void pcg_setseq_16_step_r(struct pcg_state_setseq_16* rng)
+static inline void pcg_setseq_16_step_r(struct pcg_state_setseq_16* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_16 + rng->inc;
}
-inline void pcg_setseq_16_advance_r(struct pcg_state_setseq_16* rng,
+static inline void pcg_setseq_16_advance_r(struct pcg_state_setseq_16* rng,
uint16_t delta)
{
rng->state = pcg_advance_lcg_16(rng->state, delta,
PCG_DEFAULT_MULTIPLIER_16, rng->inc);
}
-inline void pcg_oneseq_32_step_r(struct pcg_state_32* rng)
+static inline void pcg_oneseq_32_step_r(struct pcg_state_32* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_32
+ PCG_DEFAULT_INCREMENT_32;
}
-inline void pcg_oneseq_32_advance_r(struct pcg_state_32* rng, uint32_t delta)
+static inline void pcg_oneseq_32_advance_r(struct pcg_state_32* rng, uint32_t delta)
{
rng->state = pcg_advance_lcg_32(
rng->state, delta, PCG_DEFAULT_MULTIPLIER_32, PCG_DEFAULT_INCREMENT_32);
}
-inline void pcg_mcg_32_step_r(struct pcg_state_32* rng)
+static inline void pcg_mcg_32_step_r(struct pcg_state_32* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_32;
}
-inline void pcg_mcg_32_advance_r(struct pcg_state_32* rng, uint32_t delta)
+static inline void pcg_mcg_32_advance_r(struct pcg_state_32* rng, uint32_t delta)
{
rng->state
= pcg_advance_lcg_32(rng->state, delta, PCG_DEFAULT_MULTIPLIER_32, 0u);
}
-inline void pcg_unique_32_step_r(struct pcg_state_32* rng)
+static inline void pcg_unique_32_step_r(struct pcg_state_32* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_32
+ (uint32_t)(((intptr_t)rng) | 1u);
}
-inline void pcg_unique_32_advance_r(struct pcg_state_32* rng, uint32_t delta)
+static inline void pcg_unique_32_advance_r(struct pcg_state_32* rng, uint32_t delta)
{
rng->state
= pcg_advance_lcg_32(rng->state, delta, PCG_DEFAULT_MULTIPLIER_32,
(uint32_t)(((intptr_t)rng) | 1u));
}
-inline void pcg_setseq_32_step_r(struct pcg_state_setseq_32* rng)
+static inline void pcg_setseq_32_step_r(struct pcg_state_setseq_32* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_32 + rng->inc;
}
-inline void pcg_setseq_32_advance_r(struct pcg_state_setseq_32* rng,
+static inline void pcg_setseq_32_advance_r(struct pcg_state_setseq_32* rng,
uint32_t delta)
{
rng->state = pcg_advance_lcg_32(rng->state, delta,
PCG_DEFAULT_MULTIPLIER_32, rng->inc);
}
-inline void pcg_oneseq_64_step_r(struct pcg_state_64* rng)
+static inline void pcg_oneseq_64_step_r(struct pcg_state_64* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_64
+ PCG_DEFAULT_INCREMENT_64;
}
-inline void pcg_oneseq_64_advance_r(struct pcg_state_64* rng, uint64_t delta)
+static inline void pcg_oneseq_64_advance_r(struct pcg_state_64* rng, uint64_t delta)
{
rng->state = pcg_advance_lcg_64(
rng->state, delta, PCG_DEFAULT_MULTIPLIER_64, PCG_DEFAULT_INCREMENT_64);
}
-inline void pcg_mcg_64_step_r(struct pcg_state_64* rng)
+static inline void pcg_mcg_64_step_r(struct pcg_state_64* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_64;
}
-inline void pcg_mcg_64_advance_r(struct pcg_state_64* rng, uint64_t delta)
+static inline void pcg_mcg_64_advance_r(struct pcg_state_64* rng, uint64_t delta)
{
rng->state
= pcg_advance_lcg_64(rng->state, delta, PCG_DEFAULT_MULTIPLIER_64, 0u);
}
-inline void pcg_unique_64_step_r(struct pcg_state_64* rng)
+static inline void pcg_unique_64_step_r(struct pcg_state_64* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_64
+ (uint64_t)(((intptr_t)rng) | 1u);
}
-inline void pcg_unique_64_advance_r(struct pcg_state_64* rng, uint64_t delta)
+static inline void pcg_unique_64_advance_r(struct pcg_state_64* rng, uint64_t delta)
{
rng->state
= pcg_advance_lcg_64(rng->state, delta, PCG_DEFAULT_MULTIPLIER_64,
(uint64_t)(((intptr_t)rng) | 1u));
}
-inline void pcg_setseq_64_step_r(struct pcg_state_setseq_64* rng)
+static inline void pcg_setseq_64_step_r(struct pcg_state_setseq_64* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_64 + rng->inc;
}
-inline void pcg_setseq_64_advance_r(struct pcg_state_setseq_64* rng,
+static inline void pcg_setseq_64_advance_r(struct pcg_state_setseq_64* rng,
uint64_t delta)
{
rng->state = pcg_advance_lcg_64(rng->state, delta,
@@ -592,7 +592,7 @@ inline void pcg_setseq_64_advance_r(struct pcg_state_s
}
#if PCG_HAS_128BIT_OPS
-inline void pcg_oneseq_128_step_r(struct pcg_state_128* rng)
+static inline void pcg_oneseq_128_step_r(struct pcg_state_128* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_128
+ PCG_DEFAULT_INCREMENT_128;
@@ -600,7 +600,7 @@ inline void pcg_oneseq_128_step_r(struct pcg_state_128
#endif
#if PCG_HAS_128BIT_OPS
-inline void pcg_oneseq_128_advance_r(struct pcg_state_128* rng, pcg128_t delta)
+static inline void pcg_oneseq_128_advance_r(struct pcg_state_128* rng, pcg128_t delta)
{
rng->state
= pcg_advance_lcg_128(rng->state, delta, PCG_DEFAULT_MULTIPLIER_128,
@@ -609,14 +609,14 @@ inline void pcg_oneseq_128_advance_r(struct pcg_state_
#endif
#if PCG_HAS_128BIT_OPS
-inline void pcg_mcg_128_step_r(struct pcg_state_128* rng)
+static inline void pcg_mcg_128_step_r(struct pcg_state_128* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_128;
}
#endif
#if PCG_HAS_128BIT_OPS
-inline void pcg_mcg_128_advance_r(struct pcg_state_128* rng, pcg128_t delta)
+static inline void pcg_mcg_128_advance_r(struct pcg_state_128* rng, pcg128_t delta)
{
rng->state = pcg_advance_lcg_128(rng->state, delta,
PCG_DEFAULT_MULTIPLIER_128, 0u);
@@ -624,7 +624,7 @@ inline void pcg_mcg_128_advance_r(struct pcg_state_128
#endif
#if PCG_HAS_128BIT_OPS
-inline void pcg_unique_128_step_r(struct pcg_state_128* rng)
+static inline void pcg_unique_128_step_r(struct pcg_state_128* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_128
+ (pcg128_t)(((intptr_t)rng) | 1u);
@@ -632,7 +632,7 @@ inline void pcg_unique_128_step_r(struct pcg_state_128
#endif
#if PCG_HAS_128BIT_OPS
-inline void pcg_unique_128_advance_r(struct pcg_state_128* rng, pcg128_t delta)
+static inline void pcg_unique_128_advance_r(struct pcg_state_128* rng, pcg128_t delta)
{
rng->state
= pcg_advance_lcg_128(rng->state, delta, PCG_DEFAULT_MULTIPLIER_128,
@@ -641,14 +641,14 @@ inline void pcg_unique_128_advance_r(struct pcg_state_
#endif
#if PCG_HAS_128BIT_OPS
-inline void pcg_setseq_128_step_r(struct pcg_state_setseq_128* rng)
+static inline void pcg_setseq_128_step_r(struct pcg_state_setseq_128* rng)
{
rng->state = rng->state * PCG_DEFAULT_MULTIPLIER_128 + rng->inc;
}
#endif
#if PCG_HAS_128BIT_OPS
-inline void pcg_setseq_128_advance_r(struct pcg_state_setseq_128* rng,
+static inline void pcg_setseq_128_advance_r(struct pcg_state_setseq_128* rng,
pcg128_t delta)
{
rng->state = pcg_advance_lcg_128(rng->state, delta,
@@ -661,7 +661,7 @@ inline void pcg_setseq_128_advance_r(struct pcg_state_
* these functions.
*/
-inline void pcg_oneseq_8_srandom_r(struct pcg_state_8* rng, uint8_t initstate)
+static inline void pcg_oneseq_8_srandom_r(struct pcg_state_8* rng, uint8_t initstate)
{
rng->state = 0U;
pcg_oneseq_8_step_r(rng);
@@ -669,12 +669,12 @@ inline void pcg_oneseq_8_srandom_r(struct pcg_state_8*
pcg_oneseq_8_step_r(rng);
}
-inline void pcg_mcg_8_srandom_r(struct pcg_state_8* rng, uint8_t initstate)
+static inline void pcg_mcg_8_srandom_r(struct pcg_state_8* rng, uint8_t initstate)
{
rng->state = initstate | 1u;
}
-inline void pcg_unique_8_srandom_r(struct pcg_state_8* rng, uint8_t initstate)
+static inline void pcg_unique_8_srandom_r(struct pcg_state_8* rng, uint8_t initstate)
{
rng->state = 0U;
pcg_unique_8_step_r(rng);
@@ -682,7 +682,7 @@ inline void pcg_unique_8_srandom_r(struct pcg_state_8*
pcg_unique_8_step_r(rng);
}
-inline void pcg_setseq_8_srandom_r(struct pcg_state_setseq_8* rng,
+static inline void pcg_setseq_8_srandom_r(struct pcg_state_setseq_8* rng,
uint8_t initstate, uint8_t initseq)
{
rng->state = 0U;
@@ -692,7 +692,7 @@ inline void pcg_setseq_8_srandom_r(struct pcg_state_se
pcg_setseq_8_step_r(rng);
}
-inline void pcg_oneseq_16_srandom_r(struct pcg_state_16* rng,
+static inline void pcg_oneseq_16_srandom_r(struct pcg_state_16* rng,
uint16_t initstate)
{
rng->state = 0U;
@@ -701,12 +701,12 @@ inline void pcg_oneseq_16_srandom_r(struct pcg_state_1
pcg_oneseq_16_step_r(rng);
}
-inline void pcg_mcg_16_srandom_r(struct pcg_state_16* rng, uint16_t initstate)
+static inline void pcg_mcg_16_srandom_r(struct pcg_state_16* rng, uint16_t initstate)
{
rng->state = initstate | 1u;
}
-inline void pcg_unique_16_srandom_r(struct pcg_state_16* rng,
+static inline void pcg_unique_16_srandom_r(struct pcg_state_16* rng,
uint16_t initstate)
{
rng->state = 0U;
@@ -715,7 +715,7 @@ inline void pcg_unique_16_srandom_r(struct pcg_state_1
pcg_unique_16_step_r(rng);
}
-inline void pcg_setseq_16_srandom_r(struct pcg_state_setseq_16* rng,
+static inline void pcg_setseq_16_srandom_r(struct pcg_state_setseq_16* rng,
uint16_t initstate, uint16_t initseq)
{
rng->state = 0U;
@@ -725,7 +725,7 @@ inline void pcg_setseq_16_srandom_r(struct pcg_state_s
pcg_setseq_16_step_r(rng);
}
-inline void pcg_oneseq_32_srandom_r(struct pcg_state_32* rng,
+static inline void pcg_oneseq_32_srandom_r(struct pcg_state_32* rng,
uint32_t initstate)
{
rng->state = 0U;
@@ -734,12 +734,12 @@ inline void pcg_oneseq_32_srandom_r(struct pcg_state_3
pcg_oneseq_32_step_r(rng);
}
-inline void pcg_mcg_32_srandom_r(struct pcg_state_32* rng, uint32_t initstate)
+static inline void pcg_mcg_32_srandom_r(struct pcg_state_32* rng, uint32_t initstate)
{
rng->state = initstate | 1u;
}
-inline void pcg_unique_32_srandom_r(struct pcg_state_32* rng,
+static inline void pcg_unique_32_srandom_r(struct pcg_state_32* rng,
uint32_t initstate)
{
rng->state = 0U;
@@ -748,7 +748,7 @@ inline void pcg_unique_32_srandom_r(struct pcg_state_3
pcg_unique_32_step_r(rng);
}
-inline void pcg_setseq_32_srandom_r(struct pcg_state_setseq_32* rng,
+static inline void pcg_setseq_32_srandom_r(struct pcg_state_setseq_32* rng,
uint32_t initstate, uint32_t initseq)
{
rng->state = 0U;
@@ -758,7 +758,7 @@ inline void pcg_setseq_32_srandom_r(struct pcg_state_s
pcg_setseq_32_step_r(rng);
}
-inline void pcg_oneseq_64_srandom_r(struct pcg_state_64* rng,
+static inline void pcg_oneseq_64_srandom_r(struct pcg_state_64* rng,
uint64_t initstate)
{
rng->state = 0U;
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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