svn commit: r325665 - in projects/bsd_rdma_4_9/sys: conf dev/mlx5/mlx5_ib modules/mlx5ib
Hans Petter Selasky
hselasky at FreeBSD.org
Fri Nov 10 15:02:19 UTC 2017
Author: hselasky
Date: Fri Nov 10 15:02:17 2017
New Revision: 325665
URL: https://svnweb.freebsd.org/changeset/base/325665
Log:
Update mlx5ib(4) to match Linux 4.9 and the new ibcore APIs.
Sponsored by: Mellanox Technologies
Added:
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib_gsi.c (contents, props changed)
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib_virt.c (contents, props changed)
Deleted:
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib_roce.c
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/user.h
Modified:
projects/bsd_rdma_4_9/sys/conf/files
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib.h
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib_ah.c
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib_cq.c
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib_doorbell.c
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib_mad.c
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib_mem.c
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib_mr.c
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c
projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib_srq.c
projects/bsd_rdma_4_9/sys/modules/mlx5ib/Makefile
Modified: projects/bsd_rdma_4_9/sys/conf/files
==============================================================================
--- projects/bsd_rdma_4_9/sys/conf/files Fri Nov 10 14:53:16 2017 (r325664)
+++ projects/bsd_rdma_4_9/sys/conf/files Fri Nov 10 15:02:17 2017 (r325665)
@@ -4623,6 +4623,8 @@ dev/mlx5/mlx5_ib/mlx5_ib_cq.c optional mlx5ib pci of
compile-with "${OFED_C}"
dev/mlx5/mlx5_ib/mlx5_ib_doorbell.c optional mlx5ib pci ofed \
compile-with "${OFED_C}"
+dev/mlx5/mlx5_ib/mlx5_ib_gsi.c optional mlx5ib pci ofed \
+ compile-with "${OFED_C}"
dev/mlx5/mlx5_ib/mlx5_ib_mad.c optional mlx5ib pci ofed \
compile-with "${OFED_C}"
dev/mlx5/mlx5_ib/mlx5_ib_main.c optional mlx5ib pci ofed \
@@ -4633,9 +4635,9 @@ dev/mlx5/mlx5_ib/mlx5_ib_mr.c optional mlx5ib pci of
compile-with "${OFED_C}"
dev/mlx5/mlx5_ib/mlx5_ib_qp.c optional mlx5ib pci ofed \
compile-with "${OFED_C}"
-dev/mlx5/mlx5_ib/mlx5_ib_roce.c optional mlx5ib pci ofed \
- compile-with "${OFED_C}"
dev/mlx5/mlx5_ib/mlx5_ib_srq.c optional mlx5ib pci ofed \
+ compile-with "${OFED_C}"
+dev/mlx5/mlx5_ib/mlx5_ib_virt.c optional mlx5ib pci ofed \
compile-with "${OFED_C}"
dev/mlx5/mlx5_core/mlx5_alloc.c optional mlx5 pci \
Modified: projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib.h
==============================================================================
--- projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib.h Fri Nov 10 14:53:16 2017 (r325664)
+++ projects/bsd_rdma_4_9/sys/dev/mlx5/mlx5_ib/mlx5_ib.h Fri Nov 10 15:02:17 2017 (r325665)
@@ -30,31 +30,33 @@
#include <linux/kernel.h>
#include <linux/sched.h>
+#include <linux/printk.h>
#include <rdma/ib_verbs.h>
#include <rdma/ib_smi.h>
-#include <rdma/ib_addr.h>
-#include <dev/mlx5/device.h>
-#include <dev/mlx5/driver.h>
#include <dev/mlx5/cq.h>
#include <dev/mlx5/qp.h>
#include <dev/mlx5/srq.h>
#include <linux/types.h>
#include <dev/mlx5/mlx5_core/transobj.h>
+#include <rdma/ib_user_verbs.h>
+#include <rdma/mlx5-abi.h>
#define mlx5_ib_dbg(dev, format, arg...) \
-pr_debug("mlx5_dbg:%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
- __LINE__, curthread->td_proc->p_pid, ##arg)
+pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
+ __LINE__, current->pid, ##arg)
#define mlx5_ib_err(dev, format, arg...) \
-printf("mlx5_ib: ERR: ""mlx5_err:%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
- __LINE__, curthread->td_proc->p_pid, ##arg)
+pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
+ __LINE__, current->pid, ##arg)
#define mlx5_ib_warn(dev, format, arg...) \
-printf("mlx5_ib: WARN: ""mlx5_warn:%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
- __LINE__, curthread->td_proc->p_pid, ##arg)
-#define BF_ENABLE 0
+pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
+ __LINE__, current->pid, ##arg)
-extern struct workqueue_struct *mlx5_ib_wq;
+#define field_avail(type, fld, sz) (offsetof(type, fld) + \
+ sizeof(((type *)0)->fld) <= (sz))
+#define MLX5_IB_DEFAULT_UIDX 0xffffff
+#define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
enum {
MLX5_IB_MMAP_CMD_SHIFT = 8,
@@ -66,13 +68,8 @@ enum mlx5_ib_mmap_cmd {
MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
MLX5_IB_MMAP_WC_PAGE = 2,
MLX5_IB_MMAP_NC_PAGE = 3,
- MLX5_IB_MMAP_MAP_DC_INFO_PAGE = 4,
-
- /* Use EXP mmap commands until it is pushed to upstream */
- MLX5_IB_EXP_MMAP_CORE_CLOCK = 0xFB,
- MLX5_IB_EXP_MMAP_GET_CONTIGUOUS_PAGES_CPU_NUMA = 0xFC,
- MLX5_IB_EXP_MMAP_GET_CONTIGUOUS_PAGES_DEV_NUMA = 0xFD,
- MLX5_IB_EXP_ALLOC_N_MMAP_WC = 0xFE,
+ /* 5 is chosen in order to be compatible with old versions of libmlx5 */
+ MLX5_IB_MMAP_CORE_CLOCK = 5,
};
enum {
@@ -82,11 +79,6 @@ enum {
MLX5_REQ_SCAT_DATA64_CQE = 0x22,
};
-enum {
- MLX5_DCT_CS_RES_64 = 2,
- MLX5_CNAK_RX_POLL_CQ_QUOTA = 256,
-};
-
enum mlx5_ib_latency_class {
MLX5_IB_LATENCY_CLASS_LOW,
MLX5_IB_LATENCY_CLASS_MEDIUM,
@@ -101,19 +93,17 @@ enum mlx5_ib_mad_ifc_flags {
};
enum {
- MLX5_CROSS_CHANNEL_UUAR = 0,
+ MLX5_CROSS_CHANNEL_UUAR = 0,
};
enum {
- MLX5_IB_MAX_CTX_DYNAMIC_UARS = 256,
- MLX5_IB_INVALID_UAR_INDEX = -1U
+ MLX5_CQE_VERSION_V0,
+ MLX5_CQE_VERSION_V1,
};
-enum {
- MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES = 13,
- MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES = 6,
- MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES = 16,
- MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES = 9,
+struct mlx5_ib_vma_private_data {
+ struct list_head list;
+ struct vm_area_struct *vma;
};
struct mlx5_ib_ucontext {
@@ -124,9 +114,10 @@ struct mlx5_ib_ucontext {
*/
struct mutex db_page_mutex;
struct mlx5_uuar_info uuari;
- u32 dynamic_wc_uar_index[MLX5_IB_MAX_CTX_DYNAMIC_UARS];
+ u8 cqe_version;
/* Transport Domain number */
u32 tdn;
+ struct list_head vma_private_list;
};
static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
@@ -137,32 +128,83 @@ static inline struct mlx5_ib_ucontext *to_mucontext(st
struct mlx5_ib_pd {
struct ib_pd ibpd;
u32 pdn;
- u32 pa_lkey;
};
-struct wr_list {
- u16 opcode;
- u16 next;
+#define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
+#define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
+#if (MLX5_IB_FLOW_LAST_PRIO <= 0)
+#error "Invalid number of bypass priorities"
+#endif
+#define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
+
+#define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
+#define MLX5_IB_NUM_SNIFFER_FTS 2
+struct mlx5_ib_flow_prio {
+ struct mlx5_flow_table *flow_table;
+ unsigned int refcount;
};
-struct mlx5_swr_ctx {
- u64 wrid;
- u32 wr_data;
- struct wr_list w_list;
- u32 wqe_head;
- u8 sig_piped;
- u8 rsvd[11];
+struct mlx5_ib_flow_handler {
+ struct list_head list;
+ struct ib_flow ibflow;
+ struct mlx5_ib_flow_prio *prio;
+ struct mlx5_flow_rule *rule;
};
-struct mlx5_rwr_ctx {
- u64 wrid;
+struct mlx5_ib_flow_db {
+ struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
+ struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
+ struct mlx5_flow_table *lag_demux_ft;
+ /* Protect flow steering bypass flow tables
+ * when add/del flow rules.
+ * only single add/removal of flow steering rule could be done
+ * simultaneously.
+ */
+ struct mutex lock;
};
+/* Use macros here so that don't have to duplicate
+ * enum ib_send_flags and enum ib_qp_type for low-level driver
+ */
+
+#define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START
+#define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1)
+#define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2)
+
+#define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 3)
+#define MLX5_IB_SEND_UMR_UPDATE_PD (IB_SEND_RESERVED_START << 4)
+#define MLX5_IB_SEND_UMR_UPDATE_ACCESS IB_SEND_RESERVED_END
+
+#define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
+/*
+ * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
+ * creates the actual hardware QP.
+ */
+#define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
+#define MLX5_IB_WR_UMR IB_WR_RESERVED1
+
+/* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
+ *
+ * These flags are intended for internal use by the mlx5_ib driver, and they
+ * rely on the range reserved for that use in the ib_qp_create_flags enum.
+ */
+
+/* Create a UD QP whose source QP number is 1 */
+static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void)
+{
+ return IB_QP_CREATE_RESERVED_START;
+}
+
+struct wr_list {
+ u16 opcode;
+ u16 next;
+};
+
struct mlx5_ib_wq {
- union {
- struct mlx5_swr_ctx *swr_ctx;
- struct mlx5_rwr_ctx *rwr_ctx;
- };
+ u64 *wrid;
+ u32 *wr_data;
+ struct wr_list *w_list;
+ unsigned *wqe_head;
u16 unsig_count;
/* serialize post to the work queue
@@ -180,6 +222,25 @@ struct mlx5_ib_wq {
void *qend;
};
+struct mlx5_ib_rwq {
+ struct ib_wq ibwq;
+ struct mlx5_core_qp core_qp;
+ u32 rq_num_pas;
+ u32 log_rq_stride;
+ u32 log_rq_size;
+ u32 rq_page_offset;
+ u32 log_page_size;
+ struct ib_umem *umem;
+ size_t buf_size;
+ unsigned int page_shift;
+ int create_type;
+ struct mlx5_db db;
+ u32 user_index;
+ u32 wqe_count;
+ u32 wqe_shift;
+ int wq_sig;
+};
+
enum {
MLX5_QP_USER,
MLX5_QP_KERNEL,
@@ -191,60 +252,103 @@ enum {
MLX5_WQ_KERNEL
};
-struct mlx5_ib_sqd {
- struct mlx5_ib_qp *qp;
+struct mlx5_ib_rwq_ind_table {
+ struct ib_rwq_ind_table ib_rwq_ind_tbl;
+ u32 rqtn;
+};
+
+/*
+ * Connect-IB can trigger up to four concurrent pagefaults
+ * per-QP.
+ */
+enum mlx5_ib_pagefault_context {
+ MLX5_IB_PAGEFAULT_RESPONDER_READ,
+ MLX5_IB_PAGEFAULT_REQUESTOR_READ,
+ MLX5_IB_PAGEFAULT_RESPONDER_WRITE,
+ MLX5_IB_PAGEFAULT_REQUESTOR_WRITE,
+ MLX5_IB_PAGEFAULT_CONTEXTS
+};
+
+static inline enum mlx5_ib_pagefault_context
+ mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault)
+{
+ return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE);
+}
+
+struct mlx5_ib_pfault {
struct work_struct work;
+ struct mlx5_pagefault mpfault;
};
-struct mlx5_ib_mc_flows_list {
- struct list_head flows_list;
- /*Protect the flows_list*/
- struct mutex lock;
+struct mlx5_ib_ubuffer {
+ struct ib_umem *umem;
+ int buf_size;
+ u64 buf_addr;
};
-struct mlx5_ib_qp {
- struct ib_qp ibqp;
+struct mlx5_ib_qp_base {
+ struct mlx5_ib_qp *container_mibqp;
struct mlx5_core_qp mqp;
- struct mlx5_core_qp mrq;
- struct mlx5_core_qp msq;
- u32 tisn;
+ struct mlx5_ib_ubuffer ubuffer;
+};
+
+struct mlx5_ib_qp_trans {
+ struct mlx5_ib_qp_base base;
+ u16 xrcdn;
+ u8 alt_port;
+ u8 atomic_rd_en;
+ u8 resp_depth;
+};
+
+struct mlx5_ib_rss_qp {
+ u32 tirn;
+};
+
+struct mlx5_ib_rq {
+ struct mlx5_ib_qp_base base;
+ struct mlx5_ib_wq *rq;
+ struct mlx5_ib_ubuffer ubuffer;
+ struct mlx5_db *doorbell;
u32 tirn;
+ u8 state;
+};
+
+struct mlx5_ib_sq {
+ struct mlx5_ib_qp_base base;
+ struct mlx5_ib_wq *sq;
+ struct mlx5_ib_ubuffer ubuffer;
+ struct mlx5_db *doorbell;
+ u32 tisn;
+ u8 state;
+};
+
+struct mlx5_ib_raw_packet_qp {
+ struct mlx5_ib_sq sq;
+ struct mlx5_ib_rq rq;
+};
+
+struct mlx5_ib_qp {
+ struct ib_qp ibqp;
+ union {
+ struct mlx5_ib_qp_trans trans_qp;
+ struct mlx5_ib_raw_packet_qp raw_packet_qp;
+ struct mlx5_ib_rss_qp rss_qp;
+ };
struct mlx5_buf buf;
struct mlx5_db db;
struct mlx5_ib_wq rq;
- u32 doorbell_qpn;
u8 sq_signal_bits;
u8 fm_cache;
- int sq_max_wqes_per_wr;
- int sq_spare_wqes;
struct mlx5_ib_wq sq;
- struct ib_umem *umem;
- int buf_size;
- /* Raw Ethernet QP's SQ is allocated seperately
- * from the RQ's buffer in user-space.
- */
- struct ib_umem *sq_umem;
- int sq_buf_size;
- u64 sq_buf_addr;
- int allow_mp_wqe;
-
/* serialize qp state modifications
*/
struct mutex mutex;
- u16 xrcdn;
u32 flags;
u8 port;
- u8 alt_port;
- u8 atomic_rd_en;
- u8 resp_depth;
u8 state;
- /* Raw Ethernet QP's SQ and RQ states */
- u8 rq_state;
- u8 sq_state;
- int mlx_type;
int wq_sig;
int scat_cqe;
int max_inline_data;
@@ -257,16 +361,27 @@ struct mlx5_ib_qp {
int uuarn;
int create_type;
- u32 pa_lkey;
/* Store signature errors */
bool signature_en;
+#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
+ /*
+ * A flag that is true for QP's that are in a state that doesn't
+ * allow page faults, and shouldn't schedule any more faults.
+ */
+ int disable_page_faults;
+ /*
+ * The disable_page_faults_lock protects a QP's disable_page_faults
+ * field, allowing for a thread to atomically check whether the QP
+ * allows page faults, and if so schedule a page fault.
+ */
+ spinlock_t disable_page_faults_lock;
+ struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS];
+#endif
struct list_head qps_list;
struct list_head cq_recv_list;
struct list_head cq_send_list;
-
- struct mlx5_ib_mc_flows_list mc_flows_list;
};
struct mlx5_ib_cq_buf {
@@ -277,12 +392,20 @@ struct mlx5_ib_cq_buf {
};
enum mlx5_ib_qp_flags {
- MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = 1 << 0,
- MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 1,
- MLX5_IB_QP_CAP_RX_END_PADDING = 1 << 5,
+ MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO,
+ MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
+ MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL,
+ MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND,
+ MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV,
+ MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5,
+ /* QP uses 1 as its source QP number */
+ MLX5_IB_QP_SQPN_QP1 = 1 << 6,
+ MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7,
+ MLX5_IB_QP_RSS = 1 << 8,
};
struct mlx5_umr_wr {
+ struct ib_send_wr wr;
union {
u64 virt_addr;
u64 offset;
@@ -290,11 +413,16 @@ struct mlx5_umr_wr {
struct ib_pd *pd;
unsigned int page_shift;
unsigned int npages;
- u64 length;
+ u32 length;
int access_flags;
u32 mkey;
};
+static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr)
+{
+ return container_of(wr, struct mlx5_umr_wr, wr);
+}
+
struct mlx5_shared_mr_info {
int mr_id;
struct ib_umem *umem;
@@ -316,10 +444,19 @@ struct mlx5_ib_cq {
struct mlx5_ib_cq_buf *resize_buf;
struct ib_umem *resize_umem;
int cqe_size;
- struct list_head list_send_qp;
- struct list_head list_recv_qp;
+ struct list_head list_send_qp;
+ struct list_head list_recv_qp;
+ u32 create_flags;
+ struct list_head wc_list;
+ enum ib_cq_notify_flags notify_flags;
+ struct work_struct notify_work;
};
+struct mlx5_ib_wc {
+ struct ib_wc wc;
+ struct list_head list;
+};
+
struct mlx5_ib_srq {
struct ib_srq ibsrq;
struct mlx5_core_srq msrq;
@@ -353,44 +490,45 @@ enum mlx5_ib_mtt_access_flags {
struct mlx5_ib_mr {
struct ib_mr ibmr;
- struct mlx5_core_mr mmr;
+ void *descs;
+ dma_addr_t desc_map;
+ int ndescs;
+ int max_descs;
+ int desc_size;
+ int access_mode;
+ struct mlx5_core_mr mmkey;
struct ib_umem *umem;
struct mlx5_shared_mr_info *smr_info;
struct list_head list;
int order;
int umred;
- dma_addr_t dma;
int npages;
struct mlx5_ib_dev *dev;
- struct mlx5_create_mkey_mbox_out out;
+ u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
struct mlx5_core_sig_ctx *sig;
- u32 max_reg_descriptors;
- u64 size;
- u64 page_count;
- struct mlx5_ib_mr **children;
- int nchild;
+ int live;
+ void *descs_alloc;
+ int access_flags; /* Needed for rereg MR */
};
-struct mlx5_ib_fast_reg_page_list {
- struct ib_fast_reg_page_list ibfrpl;
- __be64 *mapped_page_list;
- dma_addr_t map;
+struct mlx5_ib_mw {
+ struct ib_mw ibmw;
+ struct mlx5_core_mr mmkey;
};
struct mlx5_ib_umr_context {
+ struct ib_cqe cqe;
enum ib_wc_status status;
struct completion done;
};
-static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context)
-{
- context->status = -1;
- init_completion(&context->done);
-}
-
struct umr_common {
struct ib_pd *pd;
- struct ib_mr *mr;
+ struct ib_cq *cq;
+ struct ib_qp *qp;
+ /* control access to UMR QP
+ */
+ struct semaphore sem;
};
enum {
@@ -399,27 +537,6 @@ enum {
MLX5_FMR_BUSY,
};
-struct mlx5_ib_fmr {
- struct ib_fmr ibfmr;
- struct mlx5_core_mr mr;
- int access_flags;
- int state;
- /* protect fmr state
- */
- spinlock_t lock;
- u64 wrid;
- struct ib_send_wr wr[2];
- u8 page_shift;
- struct ib_fast_reg_page_list page_list;
-};
-
-struct cache_order {
- struct kobject kobj;
- int order;
- int index;
- struct mlx5_ib_dev *dev;
-};
-
struct mlx5_cache_ent {
struct list_head head;
/* sync access to the cahce entry
@@ -427,17 +544,23 @@ struct mlx5_cache_ent {
spinlock_t lock;
+ struct dentry *dir;
+ char name[4];
u32 order;
u32 size;
u32 cur;
u32 miss;
u32 limit;
+ struct dentry *fsize;
+ struct dentry *fcur;
+ struct dentry *fmiss;
+ struct dentry *flimit;
+
struct mlx5_ib_dev *dev;
struct work_struct work;
struct delayed_work dwork;
int pending;
- struct cache_order co;
};
struct mlx5_mr_cache {
@@ -445,11 +568,17 @@ struct mlx5_mr_cache {
struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
int stopped;
struct dentry *root;
- int last_add;
- int rel_timeout;
- int rel_imm;
+ unsigned long last_add;
};
+struct mlx5_ib_gsi_qp;
+
+struct mlx5_ib_port_resources {
+ struct mlx5_ib_resources *devr;
+ struct mlx5_ib_gsi_qp *gsi;
+ struct work_struct pkey_change_work;
+};
+
struct mlx5_ib_resources {
struct ib_cq *c0;
struct ib_xrcd *x0;
@@ -457,106 +586,58 @@ struct mlx5_ib_resources {
struct ib_pd *p0;
struct ib_srq *s0;
struct ib_srq *s1;
+ struct mlx5_ib_port_resources ports[2];
+ /* Protects changes to the port resources */
+ struct mutex mutex;
};
-struct mlx5_dc_tracer {
- struct page *pg;
- dma_addr_t dma;
- int size;
- int order;
-};
-
-struct mlx5_dc_desc {
- dma_addr_t dma;
- void *buf;
-};
-
-enum mlx5_op {
- MLX5_WR_OP_MLX = 1,
-};
-
-struct mlx5_mlx_wr {
- u8 sl;
- u16 dlid;
- int icrc;
-};
-
-struct mlx5_send_wr {
- struct ib_send_wr wr;
- union {
- struct mlx5_mlx_wr mlx;
- } sel;
-};
-
-struct mlx5_dc_data {
- struct ib_mr *mr;
- struct ib_qp *dcqp;
- struct ib_cq *rcq;
- struct ib_cq *scq;
- unsigned int rx_npages;
- unsigned int tx_npages;
- struct mlx5_dc_desc *rxdesc;
- struct mlx5_dc_desc *txdesc;
- unsigned int max_wqes;
- unsigned int cur_send;
- unsigned int last_send_completed;
- int tx_pending;
- struct mlx5_ib_dev *dev;
- int port;
- int initialized;
- struct kobject kobj;
- unsigned long connects;
- unsigned long cnaks;
- unsigned long discards;
- struct ib_wc wc_tbl[MLX5_CNAK_RX_POLL_CQ_QUOTA];
-};
-
-struct mlx5_ib_port_sysfs_group {
- struct kobject kobj;
- bool enabled;
- struct attribute_group counters;
-};
-
-#define MLX5_IB_GID_MAX 16
-
struct mlx5_ib_port {
- struct mlx5_ib_dev *dev;
- u8 port_num; /* 0 based */
- u8 port_gone; /* set when gone */
u16 q_cnt_id;
- struct mlx5_ib_port_sysfs_group group;
- union ib_gid gid_table[MLX5_IB_GID_MAX];
};
+struct mlx5_roce {
+ /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
+ * netdev pointer
+ */
+ rwlock_t netdev_lock;
+ struct net_device *netdev;
+ struct notifier_block nb;
+ atomic_t next_port;
+};
+
struct mlx5_ib_dev {
struct ib_device ib_dev;
struct mlx5_core_dev *mdev;
+ struct mlx5_roce roce;
MLX5_DECLARE_DOORBELL_LOCK(uar_lock);
int num_ports;
/* serialize update of capability mask
*/
struct mutex cap_mask_mutex;
- bool ib_active;
+ bool ib_active;
struct umr_common umrc;
/* sync used page count stats
*/
struct mlx5_ib_resources devr;
- struct mutex slow_path_mutex;
- int enable_atomic_resp;
- enum ib_atomic_cap atomic_cap;
struct mlx5_mr_cache cache;
- struct kobject mr_cache;
- /* protect resources needed as part of reset flow */
- spinlock_t reset_flow_resource_lock;
- struct list_head qp_list;
struct timer_list delay_timer;
+ /* Prevents soft lock on massive reg MRs */
+ struct mutex slow_path_mutex;
int fill_delay;
- struct mlx5_dc_tracer dctr;
- struct mlx5_dc_data dcd[MLX5_MAX_PORTS];
- struct kobject *dc_kobj;
+#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
+ struct ib_odp_caps odp_caps;
+ /*
+ * Sleepable RCU that prevents destruction of MRs while they are still
+ * being used by a page fault handler.
+ */
+ struct srcu_struct mr_srcu;
+#endif
+ struct mlx5_ib_flow_db flow_db;
+ /* protect resources needed as part of reset flow */
+ spinlock_t reset_flow_resource_lock;
+ struct list_head qp_list;
/* Array with num_ports elements */
struct mlx5_ib_port *port;
- struct kobject *ports_parent;
};
static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
@@ -574,11 +655,6 @@ static inline struct mlx5_ib_dev *to_mdev(struct ib_de
return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
}
-static inline struct mlx5_ib_fmr *to_mfmr(struct ib_fmr *ibfmr)
-{
- return container_of(ibfmr, struct mlx5_ib_fmr, ibfmr);
-}
-
static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
{
return container_of(ibcq, struct mlx5_ib_cq, ibcq);
@@ -586,24 +662,19 @@ static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *
static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
{
- return container_of(mqp, struct mlx5_ib_qp, mqp);
+ return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
}
-static inline struct mlx5_ib_qp *sq_to_mibqp(struct mlx5_core_qp *msq)
+static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
{
- return container_of(msq, struct mlx5_ib_qp, msq);
+ return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
}
-static inline struct mlx5_ib_qp *rq_to_mibqp(struct mlx5_core_qp *mrq)
+static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmkey)
{
- return container_of(mrq, struct mlx5_ib_qp, mrq);
+ return container_of(mmkey, struct mlx5_ib_mr, mmkey);
}
-static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmr)
-{
- return container_of(mmr, struct mlx5_ib_mr, mmr);
-}
-
static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
{
return container_of(ibpd, struct mlx5_ib_pd, ibpd);
@@ -619,6 +690,16 @@ static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *
return container_of(ibqp, struct mlx5_ib_qp, ibqp);
}
+static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
+{
+ return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
+}
+
+static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
+{
+ return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
+}
+
static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
{
return container_of(msrq, struct mlx5_ib_srq, msrq);
@@ -629,9 +710,9 @@ static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *
return container_of(ibmr, struct mlx5_ib_mr, ibmr);
}
-static inline struct mlx5_ib_fast_reg_page_list *to_mfrpl(struct ib_fast_reg_page_list *ibfrpl)
+static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
{
- return container_of(ibfrpl, struct mlx5_ib_fast_reg_page_list, ibfrpl);
+ return container_of(ibmw, struct mlx5_ib_mw, ibmw);
}
struct mlx5_ib_ah {
@@ -644,17 +725,15 @@ static inline struct mlx5_ib_ah *to_mah(struct ib_ah *
return container_of(ibah, struct mlx5_ib_ah, ibah);
}
-int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, uintptr_t virt,
+int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
struct mlx5_db *db);
void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
- u8 port, struct ib_wc *in_wc, struct ib_grh *in_grh,
- void *in_mad, void *response_mad);
-struct ib_ah *create_ib_ah(struct mlx5_ib_dev *dev, struct ib_ah_attr *ah_attr,
- struct mlx5_ib_ah *ah, enum rdma_link_layer ll);
+ u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
+ const void *in_mad, void *response_mad);
struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr);
int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
int mlx5_ib_destroy_ah(struct ib_ah *ah);
@@ -680,62 +759,62 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_se
int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
struct ib_recv_wr **bad_wr);
void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
+int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
+ void *buffer, u32 length,
+ struct mlx5_ib_qp_base *base);
struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
- struct ib_cq_init_attr *attr,
+ const struct ib_cq_init_attr *attr,
struct ib_ucontext *context,
struct ib_udata *udata);
int mlx5_ib_destroy_cq(struct ib_cq *cq);
int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
-int mlx5_ib_modify_cq(struct ib_cq *cq, struct ib_cq_attr *attr, int cq_attr_mask);
+int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
u64 virt_addr, int access_flags,
- struct ib_udata *udata, int mr_id);
-struct ib_mr *mlx5_ib_reg_phys_mr(struct ib_pd *pd,
- struct ib_phys_buf *buffer_list,
- int num_phys_buf,
- int access_flags,
- u64 *virt_addr);
+ struct ib_udata *udata);
+struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
+ struct ib_udata *udata);
+int mlx5_ib_dealloc_mw(struct ib_mw *mw);
+int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index,
+ int npages, int zap);
+int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
+ u64 length, u64 virt_addr, int access_flags,
+ struct ib_pd *pd, struct ib_udata *udata);
int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
-int mlx5_ib_destroy_mr(struct ib_mr *ibmr);
-struct ib_mr *mlx5_ib_alloc_fast_reg_mr(struct ib_pd *pd,
- int max_page_list_len);
-struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev,
- int page_list_len);
-void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list);
-
-struct ib_fmr *mlx5_ib_fmr_alloc(struct ib_pd *pd, int acc,
- struct ib_fmr_attr *fmr_attr);
-int mlx5_ib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
- int npages, u64 iova);
-int mlx5_ib_unmap_fmr(struct list_head *fmr_list);
-int mlx5_ib_fmr_dealloc(struct ib_fmr *ibfmr);
+struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
+ enum ib_mr_type mr_type,
+ u32 max_num_sg);
+int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
+ unsigned int *sg_offset);
int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
- struct ib_wc *in_wc, struct ib_grh *in_grh,
- struct ib_mad *in_mad, struct ib_mad *out_mad);
+ const struct ib_wc *in_wc, const struct ib_grh *in_grh,
+ const struct ib_mad_hdr *in, size_t in_mad_size,
+ struct ib_mad_hdr *out, size_t *out_mad_size,
+ u16 *out_mad_pkey_index);
struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
struct ib_ucontext *context,
struct ib_udata *udata);
int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd);
int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
-int mlx5_query_smp_attr_node_info_mad_ifc(struct ib_device *ibdev,
+int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
struct ib_smp *out_mad);
-int mlx5_query_system_image_guid_mad_ifc(struct ib_device *ibdev,
+int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
__be64 *sys_image_guid);
-int mlx5_query_max_pkeys_mad_ifc(struct ib_device *ibdev,
+int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
u16 *max_pkeys);
-int mlx5_query_vendor_id_mad_ifc(struct ib_device *ibdev,
+int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
u32 *vendor_id);
-int mlx5_query_pkey_mad_ifc(struct ib_device *ibdev, u8 port, u16 index,
+int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
+int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
+int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
u16 *pkey);
-int mlx5_query_node_desc_mad_ifc(struct mlx5_ib_dev *dev, char *node_desc);
-int mlx5_query_node_guid_mad_ifc(struct mlx5_ib_dev *dev, u64 *node_guid);
-int mlx5_query_gids_mad_ifc(struct ib_device *ibdev, u8 port, int index,
+int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
union ib_gid *gid);
-int mlx5_query_port_mad_ifc(struct ib_device *ibdev, u8 port,
+int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
struct ib_port_attr *props);
int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
struct ib_port_attr *props);
@@ -743,30 +822,89 @@ int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift,
int *ncont, int *order);
+void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
+ int page_shift, size_t offset, size_t num_pages,
+ __be64 *pas, int access_flags);
void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
- int page_shift, __be64 *pas, int umr);
+ int page_shift, __be64 *pas, int access_flags);
void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift);
-void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context);
-int mlx5_query_port_roce(struct ib_device *ibdev, u8 port,
- struct ib_port_attr *props);
-__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port, int index,
- __be16 ah_udp_s_port);
-int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port,
- int index, int *gid_type);
-struct net_device *mlx5_ib_get_netdev(struct ib_device *ib_dev, u8 port);
-int modify_gid_roce(struct ib_device *ib_dev, u8 port, unsigned int index,
- const union ib_gid *gid, struct net_device *ndev);
-int query_gid_roce(struct ib_device *ib_dev, u8 port, int index,
- union ib_gid *gid);
-int mlx5_process_mad_mad_ifc(struct ib_device *ibdev, int mad_flags,
- u8 port_num, struct ib_wc *in_wc,
- struct ib_grh *in_grh, struct ib_mad *in_mad,
- struct ib_mad *out_mad);
+int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
+ struct ib_mr_status *mr_status);
+struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
+ struct ib_wq_init_attr *init_attr,
+ struct ib_udata *udata);
+int mlx5_ib_destroy_wq(struct ib_wq *wq);
+int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
+ u32 wq_attr_mask, struct ib_udata *udata);
+struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
+ struct ib_rwq_ind_table_init_attr *init_attr,
+ struct ib_udata *udata);
+int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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