svn commit: r233930 - in projects/armv6/sys/arm: conf ti ti/omap4
Damjan Marion
dmarion at FreeBSD.org
Thu Apr 5 22:06:11 UTC 2012
Author: dmarion
Date: Thu Apr 5 22:06:10 2012
New Revision: 233930
URL: http://svn.freebsd.org/changeset/base/233930
Log:
Rename DMA driver to SDMA so we can introduce new
EDMA driver for TI SoCs.
Added:
projects/armv6/sys/arm/ti/ti_sdma.c
- copied, changed from r233929, projects/armv6/sys/arm/ti/omap_dma.c
projects/armv6/sys/arm/ti/ti_sdma.h
- copied, changed from r233929, projects/armv6/sys/arm/ti/omap_dma.h
projects/armv6/sys/arm/ti/ti_sdmareg.h
- copied, changed from r233929, projects/armv6/sys/arm/ti/omap_dmareg.h
Deleted:
projects/armv6/sys/arm/ti/omap_dma.c
projects/armv6/sys/arm/ti/omap_dma.h
projects/armv6/sys/arm/ti/omap_dmareg.h
Modified:
projects/armv6/sys/arm/conf/PANDABOARD
projects/armv6/sys/arm/ti/omap4/files.omap4
projects/armv6/sys/arm/ti/ti_mmchs.c
Modified: projects/armv6/sys/arm/conf/PANDABOARD
==============================================================================
--- projects/armv6/sys/arm/conf/PANDABOARD Thu Apr 5 19:42:20 2012 (r233929)
+++ projects/armv6/sys/arm/conf/PANDABOARD Thu Apr 5 22:06:10 2012 (r233930)
@@ -130,7 +130,7 @@ device smsc # SMSC LAN95xx USB Etherne
# OMAP-specific devices
-device omap_dma
+device ti_sdma
device twl
device twl_vreg
Modified: projects/armv6/sys/arm/ti/omap4/files.omap4
==============================================================================
--- projects/armv6/sys/arm/ti/omap4/files.omap4 Thu Apr 5 19:42:20 2012 (r233929)
+++ projects/armv6/sys/arm/ti/omap4/files.omap4 Thu Apr 5 22:06:10 2012 (r233930)
@@ -5,7 +5,7 @@ arm/ti/mp_timer.c standard
arm/ti/ti_smc.S standard
arm/ti/usb/omap_ehci.c optional usb ehci
-arm/ti/omap_dma.c optional omap_dma
+arm/ti/ti_sdma.c optional ti_sdma
arm/ti/ti_mmchs.c optional mmc
arm/ti/omap4/omap4_l2cache.c optional pl310
Modified: projects/armv6/sys/arm/ti/ti_mmchs.c
==============================================================================
--- projects/armv6/sys/arm/ti/ti_mmchs.c Thu Apr 5 19:42:20 2012 (r233929)
+++ projects/armv6/sys/arm/ti/ti_mmchs.c Thu Apr 5 22:06:10 2012 (r233930)
@@ -82,7 +82,7 @@ __FBSDID("$FreeBSD$");
#include "mmcbr_if.h"
#include "mmcbus_if.h"
-#include <arm/ti/omap_dma.h>
+#include <arm/ti/ti_sdma.h>
#include <arm/ti/ti_mmchs.h>
#include <arm/ti/ti_cpuid.h>
#include <arm/ti/ti_prcm.h>
@@ -152,14 +152,14 @@ struct ti_mmchs_softc {
/**
* Macros for driver mutex locking
*/
-#define OMAP_MMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
-#define OMAP_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
-#define OMAP_MMC_LOCK_INIT(_sc) \
+#define TI_MMCHS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
+#define TI_MMCHS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
+#define TI_MMCHS_LOCK_INIT(_sc) \
mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
"ti_mmchs", MTX_DEF)
-#define OMAP_MMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
-#define OMAP_MMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
-#define OMAP_MMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
+#define TI_MMCHS_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
+#define TI_MMCHS_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
+#define TI_MMCHS_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
static void ti_mmchs_start(struct ti_mmchs_softc *sc);
@@ -389,9 +389,9 @@ ti_mmchs_intr_error(struct ti_mmchs_soft
/* Abort the DMA transfer (DDIR bit tells direction) */
if (ti_mmchs_read_4(sc, MMCHS_CMD) & MMCHS_CMD_DDIR)
- omap_dma_stop_xfer(sc->sc_dmach_rd);
+ ti_sdma_stop_xfer(sc->sc_dmach_rd);
else
- omap_dma_stop_xfer(sc->sc_dmach_wr);
+ ti_sdma_stop_xfer(sc->sc_dmach_wr);
/* If an error occure abort the DMA operation and free the dma map */
if ((sc->sc_dmamapped > 0) && (cmd->error != MMC_ERR_NONE)) {
@@ -434,7 +434,7 @@ ti_mmchs_intr(void *arg)
uint32_t stat_reg;
int done = 0;
- OMAP_MMC_LOCK(sc);
+ TI_MMCHS_LOCK(sc);
stat_reg = ti_mmchs_read_4(sc, MMCHS_STAT)
& (ti_mmchs_read_4(sc, MMCHS_IE) | MMCHS_STAT_ERRI);
@@ -442,7 +442,7 @@ ti_mmchs_intr(void *arg)
if (sc->curcmd == NULL) {
device_printf(sc->sc_dev, "Error: current cmd NULL, already done?\n");
ti_mmchs_write_4(sc, MMCHS_STAT, stat_reg);
- OMAP_MMC_UNLOCK(sc);
+ TI_MMCHS_UNLOCK(sc);
return;
}
@@ -482,7 +482,7 @@ ti_mmchs_intr(void *arg)
ti_mmchs_start(sc);
}
- OMAP_MMC_UNLOCK(sc);
+ TI_MMCHS_UNLOCK(sc);
}
/**
@@ -628,11 +628,11 @@ ti_mmchs_start_cmd(struct ti_mmchs_softc
/* Sync the DMA buffer and setup the DMA controller */
if (data->flags & MMC_DATA_READ) {
bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_PREREAD);
- omap_dma_start_xfer_packet(sc->sc_dmach_rd, sc->sc_data_reg_paddr,
+ ti_sdma_start_xfer_packet(sc->sc_dmach_rd, sc->sc_data_reg_paddr,
paddr, 1, (data->len / 4), pktsize);
} else {
bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_PREWRITE);
- omap_dma_start_xfer_packet(sc->sc_dmach_wr, paddr,
+ ti_sdma_start_xfer_packet(sc->sc_dmach_wr, paddr,
sc->sc_data_reg_paddr, 1, (data->len / 4), pktsize);
}
@@ -713,7 +713,7 @@ ti_mmchs_request(device_t brdev, device_
{
struct ti_mmchs_softc *sc = device_get_softc(brdev);
- OMAP_MMC_LOCK(sc);
+ TI_MMCHS_LOCK(sc);
/*
* XXX do we want to be able to queue up multiple commands?
@@ -721,7 +721,7 @@ ti_mmchs_request(device_t brdev, device_
* XXX maybe the idea is naive...
*/
if (sc->req != NULL) {
- OMAP_MMC_UNLOCK(sc);
+ TI_MMCHS_UNLOCK(sc);
return (EBUSY);
}
@@ -730,7 +730,7 @@ ti_mmchs_request(device_t brdev, device_
sc->flags = 0;
ti_mmchs_start(sc);
- OMAP_MMC_UNLOCK(sc);
+ TI_MMCHS_UNLOCK(sc);
return (0);
}
@@ -757,7 +757,7 @@ ti_mmchs_get_ro(device_t brdev, device_t
struct ti_mmchs_softc *sc = device_get_softc(brdev);
unsigned int readonly = 0;
- OMAP_MMC_LOCK(sc);
+ TI_MMCHS_LOCK(sc);
if ((sc->sc_wp_gpio_pin != -1) && (sc->sc_gpio_dev != NULL)) {
if (GPIO_PIN_GET(sc->sc_gpio_dev, sc->sc_wp_gpio_pin, &readonly) != 0)
@@ -766,7 +766,7 @@ ti_mmchs_get_ro(device_t brdev, device_t
readonly = (readonly == 0) ? 0 : 1;
}
- OMAP_MMC_UNLOCK(sc);
+ TI_MMCHS_UNLOCK(sc);
return (readonly);
}
@@ -1048,7 +1048,7 @@ ti_mmchs_acquire_host(device_t brdev, de
struct ti_mmchs_softc *sc = device_get_softc(brdev);
int err = 0;
- OMAP_MMC_LOCK(sc);
+ TI_MMCHS_LOCK(sc);
while (sc->bus_busy) {
msleep(sc, &sc->sc_mtx, PZERO, "mmc", hz / 5);
@@ -1056,7 +1056,7 @@ ti_mmchs_acquire_host(device_t brdev, de
sc->bus_busy++;
- OMAP_MMC_UNLOCK(sc);
+ TI_MMCHS_UNLOCK(sc);
return (err);
}
@@ -1080,12 +1080,12 @@ ti_mmchs_release_host(device_t brdev, de
{
struct ti_mmchs_softc *sc = device_get_softc(brdev);
- OMAP_MMC_LOCK(sc);
+ TI_MMCHS_LOCK(sc);
sc->bus_busy--;
wakeup(sc);
- OMAP_MMC_UNLOCK(sc);
+ TI_MMCHS_UNLOCK(sc);
return (0);
}
@@ -1392,32 +1392,32 @@ ti_mmchs_init_dma_channels(struct ti_mmc
}
/* Activate a RX channel from the OMAP DMA driver */
- err = omap_dma_activate_channel(&sc->sc_dmach_rd, ti_mmchs_dma_intr, sc);
+ err = ti_sdma_activate_channel(&sc->sc_dmach_rd, ti_mmchs_dma_intr, sc);
if (err != 0)
return(err);
/* Setup the RX channel for MMC data transfers */
- omap_dma_set_xfer_burst(sc->sc_dmach_rd, OMAP_SDMA_BURST_NONE,
- OMAP_SDMA_BURST_64);
- omap_dma_set_xfer_data_type(sc->sc_dmach_rd, OMAP_SDMA_DATA_32BITS_SCALAR);
- omap_dma_sync_params(sc->sc_dmach_rd, dma_rx_trig,
- OMAP_SDMA_SYNC_PACKET | OMAP_SDMA_SYNC_TRIG_ON_SRC);
- omap_dma_set_addr_mode(sc->sc_dmach_rd, OMAP_SDMA_ADDR_CONSTANT,
- OMAP_SDMA_ADDR_POST_INCREMENT);
+ ti_sdma_set_xfer_burst(sc->sc_dmach_rd, TI_SDMA_BURST_NONE,
+ TI_SDMA_BURST_64);
+ ti_sdma_set_xfer_data_type(sc->sc_dmach_rd, TI_SDMA_DATA_32BITS_SCALAR);
+ ti_sdma_sync_params(sc->sc_dmach_rd, dma_rx_trig,
+ TI_SDMA_SYNC_PACKET | TI_SDMA_SYNC_TRIG_ON_SRC);
+ ti_sdma_set_addr_mode(sc->sc_dmach_rd, TI_SDMA_ADDR_CONSTANT,
+ TI_SDMA_ADDR_POST_INCREMENT);
/* Activate and configure the TX DMA channel */
- err = omap_dma_activate_channel(&sc->sc_dmach_wr, ti_mmchs_dma_intr, sc);
+ err = ti_sdma_activate_channel(&sc->sc_dmach_wr, ti_mmchs_dma_intr, sc);
if (err != 0)
return(err);
/* Setup the TX channel for MMC data transfers */
- omap_dma_set_xfer_burst(sc->sc_dmach_wr, OMAP_SDMA_BURST_64,
- OMAP_SDMA_BURST_NONE);
- omap_dma_set_xfer_data_type(sc->sc_dmach_wr, OMAP_SDMA_DATA_32BITS_SCALAR);
- omap_dma_sync_params(sc->sc_dmach_wr, dma_tx_trig,
- OMAP_SDMA_SYNC_PACKET | OMAP_SDMA_SYNC_TRIG_ON_DST);
- omap_dma_set_addr_mode(sc->sc_dmach_wr, OMAP_SDMA_ADDR_POST_INCREMENT,
- OMAP_SDMA_ADDR_CONSTANT);
+ ti_sdma_set_xfer_burst(sc->sc_dmach_wr, TI_SDMA_BURST_64,
+ TI_SDMA_BURST_NONE);
+ ti_sdma_set_xfer_data_type(sc->sc_dmach_wr, TI_SDMA_DATA_32BITS_SCALAR);
+ ti_sdma_sync_params(sc->sc_dmach_wr, dma_tx_trig,
+ TI_SDMA_SYNC_PACKET | TI_SDMA_SYNC_TRIG_ON_DST);
+ ti_sdma_set_addr_mode(sc->sc_dmach_wr, TI_SDMA_ADDR_POST_INCREMENT,
+ TI_SDMA_ADDR_CONSTANT);
return(0);
}
@@ -1449,8 +1449,8 @@ ti_mmchs_deactivate(device_t dev)
bus_generic_detach(sc->sc_dev);
/* Deactivate the DMA channels */
- omap_dma_deactivate_channel(sc->sc_dmach_rd);
- omap_dma_deactivate_channel(sc->sc_dmach_wr);
+ ti_sdma_deactivate_channel(sc->sc_dmach_rd);
+ ti_sdma_deactivate_channel(sc->sc_dmach_wr);
/* Unmap the MMC controller registers */
if (sc->sc_mem_res != 0) {
@@ -1584,7 +1584,7 @@ ti_mmchs_attach(device_t dev)
sc->sc_dev = dev;
/* Initiate the mtex lock */
- OMAP_MMC_LOCK_INIT(sc);
+ TI_MMCHS_LOCK_INIT(sc);
/* Indicate the DMA channels haven't yet been allocated */
sc->sc_dmach_rd = (unsigned int)-1;
@@ -1645,13 +1645,13 @@ ti_mmchs_attach(device_t dev)
out:
if (err) {
- OMAP_MMC_LOCK_DESTROY(sc);
+ TI_MMCHS_LOCK_DESTROY(sc);
ti_mmchs_deactivate(dev);
if (sc->sc_dmach_rd != (unsigned int)-1)
- omap_dma_deactivate_channel(sc->sc_dmach_rd);
+ ti_sdma_deactivate_channel(sc->sc_dmach_rd);
if (sc->sc_dmach_wr != (unsigned int)-1)
- omap_dma_deactivate_channel(sc->sc_dmach_wr);
+ ti_sdma_deactivate_channel(sc->sc_dmach_wr);
}
return (err);
@@ -1674,8 +1674,8 @@ ti_mmchs_detach(device_t dev)
ti_mmchs_hw_fini(dev);
ti_mmchs_deactivate(dev);
- omap_dma_deactivate_channel(sc->sc_dmach_wr);
- omap_dma_deactivate_channel(sc->sc_dmach_rd);
+ ti_sdma_deactivate_channel(sc->sc_dmach_wr);
+ ti_sdma_deactivate_channel(sc->sc_dmach_rd);
return (0);
}
@@ -1709,7 +1709,7 @@ static devclass_t ti_mmchs_devclass;
DRIVER_MODULE(ti_mmchs, simplebus, ti_mmchs_driver, ti_mmchs_devclass, 0, 0);
MODULE_DEPEND(ti_mmchs, ti_prcm, 1, 1, 1);
-MODULE_DEPEND(ti_mmchs, omap_dma, 1, 1, 1);
+MODULE_DEPEND(ti_mmchs, ti_sdma, 1, 1, 1);
MODULE_DEPEND(ti_mmchs, ti_gpio, 1, 1, 1);
/* FIXME: MODULE_DEPEND(ti_mmchs, twl_vreg, 1, 1, 1); */
Copied and modified: projects/armv6/sys/arm/ti/ti_sdma.c (from r233929, projects/armv6/sys/arm/ti/omap_dma.c)
==============================================================================
--- projects/armv6/sys/arm/ti/omap_dma.c Thu Apr 5 19:42:20 2012 (r233929, copy source)
+++ projects/armv6/sys/arm/ti/ti_sdma.c Thu Apr 5 22:06:10 2012 (r233930)
@@ -51,8 +51,8 @@ __FBSDID("$FreeBSD$");
#include <arm/ti/ti_cpuid.h>
#include <arm/ti/ti_prcm.h>
-#include <arm/ti/omap_dma.h>
-#include <arm/ti/omap_dmareg.h>
+#include <arm/ti/ti_sdma.h>
+#include <arm/ti/ti_sdmareg.h>
/**
* Kernel functions for using the DMA controller
@@ -76,7 +76,7 @@ __FBSDID("$FreeBSD$");
*
*
*/
-struct omap_dma_channel {
+struct ti_sdma_channel {
/*
* The configuration registers for the given channel, these are modified
@@ -100,10 +100,10 @@ struct omap_dma_channel {
/**
* DMA driver context, allocated and stored globally, this driver is not
- * intetned to ever be unloaded (see omap_dma_sc).
+ * intetned to ever be unloaded (see ti_sdma_sc).
*
*/
-struct omap_dma_softc {
+struct ti_sdma_softc {
device_t sc_dev;
struct resource* sc_irq_res;
struct resource* sc_mem_res;
@@ -124,32 +124,32 @@ struct omap_dma_softc {
*/
uint32_t sc_active_channels;
- struct omap_dma_channel sc_channel[NUM_DMA_CHANNELS];
+ struct ti_sdma_channel sc_channel[NUM_DMA_CHANNELS];
};
-static struct omap_dma_softc *omap_dma_sc = NULL;
+static struct ti_sdma_softc *ti_sdma_sc = NULL;
/**
* Macros for driver mutex locking
*/
-#define OMAP_DMA_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
-#define OMAP_DMA_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
-#define OMAP_DMA_LOCK_INIT(_sc) \
+#define TI_SDMA_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
+#define TI_SDMA_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
+#define TI_SDMA_LOCK_INIT(_sc) \
mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
- "omap_dma", MTX_SPIN)
-#define OMAP_DMA_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
-#define OMAP_DMA_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
-#define OMAP_DMA_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
+ "ti_sdma", MTX_SPIN)
+#define TI_SDMA_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
+#define TI_SDMA_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
+#define TI_SDMA_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
/**
* Function prototypes
*
*/
-static void omap_dma_intr(void *);
+static void ti_sdma_intr(void *);
/**
- * omap_dma_read_4 - reads a 32-bit value from one of the DMA registers
+ * ti_sdma_read_4 - reads a 32-bit value from one of the DMA registers
* @sc: DMA device context
* @off: The offset of a register from the DMA register address range
*
@@ -158,13 +158,13 @@ static void omap_dma_intr(void *);
* 32-bit value read from the register.
*/
static inline uint32_t
-omap_dma_read_4(struct omap_dma_softc *sc, bus_size_t off)
+ti_sdma_read_4(struct ti_sdma_softc *sc, bus_size_t off)
{
return bus_read_4(sc->sc_mem_res, off);
}
/**
- * omap_dma_write_4 - writes a 32-bit value to one of the DMA registers
+ * ti_sdma_write_4 - writes a 32-bit value to one of the DMA registers
* @sc: DMA device context
* @off: The offset of a register from the DMA register address range
*
@@ -173,35 +173,35 @@ omap_dma_read_4(struct omap_dma_softc *s
* 32-bit value read from the register.
*/
static inline void
-omap_dma_write_4(struct omap_dma_softc *sc, bus_size_t off, uint32_t val)
+ti_sdma_write_4(struct ti_sdma_softc *sc, bus_size_t off, uint32_t val)
{
bus_write_4(sc->sc_mem_res, off, val);
}
/**
- * omap_dma_is_omap3_rev - returns true if H/W is from OMAP3 series
+ * ti_sdma_is_omap3_rev - returns true if H/W is from OMAP3 series
* @sc: DMA device context
*
*/
static inline int
-omap_dma_is_omap3_rev(struct omap_dma_softc *sc)
+ti_sdma_is_omap3_rev(struct ti_sdma_softc *sc)
{
return (sc->sc_hw_rev == DMA4_OMAP3_REV);
}
/**
- * omap_dma_is_omap4_rev - returns true if H/W is from OMAP4 series
+ * ti_sdma_is_omap4_rev - returns true if H/W is from OMAP4 series
* @sc: DMA device context
*
*/
static inline int
-omap_dma_is_omap4_rev(struct omap_dma_softc *sc)
+ti_sdma_is_omap4_rev(struct ti_sdma_softc *sc)
{
return (sc->sc_hw_rev == DMA4_OMAP4_REV);
}
/**
- * omap_dma_intr - interrupt handler for all 4 DMA IRQs
+ * ti_sdma_intr - interrupt handler for all 4 DMA IRQs
* @arg: ignored
*
* Called when any of the four DMA IRQs are triggered.
@@ -213,21 +213,21 @@ omap_dma_is_omap4_rev(struct omap_dma_so
* nothing
*/
static void
-omap_dma_intr(void *arg)
+ti_sdma_intr(void *arg)
{
- struct omap_dma_softc *sc = omap_dma_sc;
+ struct ti_sdma_softc *sc = ti_sdma_sc;
uint32_t intr;
uint32_t csr;
unsigned int ch, j;
- struct omap_dma_channel* channel;
+ struct ti_sdma_channel* channel;
- OMAP_DMA_LOCK(sc);
+ TI_SDMA_LOCK(sc);
for (j = 0; j < NUM_DMA_IRQS; j++) {
/* Get the flag interrupts (enabled) */
- intr = omap_dma_read_4(sc, DMA4_IRQSTATUS_L(j));
- intr &= omap_dma_read_4(sc, DMA4_IRQENABLE_L(j));
+ intr = ti_sdma_read_4(sc, DMA4_IRQSTATUS_L(j));
+ intr &= ti_sdma_read_4(sc, DMA4_IRQENABLE_L(j));
if (intr == 0x00000000)
continue;
@@ -237,7 +237,7 @@ omap_dma_intr(void *arg)
channel = &sc->sc_channel[ch];
/* Read the CSR regsiter and verify we don't have a spurious IRQ */
- csr = omap_dma_read_4(sc, DMA4_CSR(ch));
+ csr = ti_sdma_read_4(sc, DMA4_CSR(ch));
if (csr == 0) {
device_printf(sc->sc_dev, "Spurious DMA IRQ for channel "
"%d\n", ch);
@@ -274,8 +274,8 @@ omap_dma_intr(void *arg)
}
/* Clear the status flags for the IRQ */
- omap_dma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
- omap_dma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));
+ ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
+ ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));
/* Call the callback for the given channel */
if (channel->callback)
@@ -284,13 +284,13 @@ omap_dma_intr(void *arg)
}
}
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return;
}
/**
- * omap_dma_activate_channel - activates a DMA channel
+ * ti_sdma_activate_channel - activates a DMA channel
* @ch: upon return contains the channel allocated
* @callback: a callback function to associate with the channel
* @data: optional data supplied when the callback is called
@@ -300,8 +300,8 @@ omap_dma_intr(void *arg)
* internal data structures and sets defaults.
*
* Note this function doesn't enable interrupts, for that you need to call
- * omap_dma_enable_channel_irq(). If not using IRQ to detect the end of the
- * transfer, you can use omap_dma_status_poll() to detect a change in the
+ * ti_sdma_enable_channel_irq(). If not using IRQ to detect the end of the
+ * transfer, you can use ti_sdma_status_poll() to detect a change in the
* status.
*
* A channel must be activated before any of the other DMA functions can be
@@ -314,12 +314,12 @@ omap_dma_intr(void *arg)
* 0 on success, otherwise an error code
*/
int
-omap_dma_activate_channel(unsigned int *ch,
+ti_sdma_activate_channel(unsigned int *ch,
void (*callback)(unsigned int ch, uint32_t status, void *data),
void *data)
{
- struct omap_dma_softc *sc = omap_dma_sc;
- struct omap_dma_channel *channel = NULL;
+ struct ti_sdma_softc *sc = ti_sdma_sc;
+ struct ti_sdma_channel *channel = NULL;
uint32_t addr;
unsigned int i;
@@ -330,11 +330,11 @@ omap_dma_activate_channel(unsigned int *
if (ch == NULL)
return (EINVAL);
- OMAP_DMA_LOCK(sc);
+ TI_SDMA_LOCK(sc);
/* Check to see if all channels are in use */
if (sc->sc_active_channels == 0xffffffff) {
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return (ENOMEM);
}
@@ -380,15 +380,15 @@ omap_dma_activate_channel(unsigned int *
/* Clear all the channel registers, this should abort any transaction */
for (addr = DMA4_CCR(*ch); addr <= DMA4_COLOR(*ch); addr += 4)
- omap_dma_write_4(sc, addr, 0x00000000);
+ ti_sdma_write_4(sc, addr, 0x00000000);
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return 0;
}
/**
- * omap_dma_deactivate_channel - deactivates a channel
+ * ti_sdma_deactivate_channel - deactivates a channel
* @ch: the channel to deactivate
*
*
@@ -400,9 +400,9 @@ omap_dma_activate_channel(unsigned int *
* EH_HANDLED or EH_NOT_HANDLED
*/
int
-omap_dma_deactivate_channel(unsigned int ch)
+ti_sdma_deactivate_channel(unsigned int ch)
{
- struct omap_dma_softc *sc = omap_dma_sc;
+ struct ti_sdma_softc *sc = ti_sdma_sc;
unsigned int j;
unsigned int addr;
@@ -410,11 +410,11 @@ omap_dma_deactivate_channel(unsigned int
if (sc == NULL)
return (ENOMEM);
- OMAP_DMA_LOCK(sc);
+ TI_SDMA_LOCK(sc);
/* First check if the channel is currently active */
if ((sc->sc_active_channels & (1 << ch)) == 0) {
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return (EBUSY);
}
@@ -422,28 +422,28 @@ omap_dma_deactivate_channel(unsigned int
sc->sc_active_channels &= ~(1 << ch);
/* Disable all DMA interrupts for the channel. */
- omap_dma_write_4(sc, DMA4_CICR(ch), 0);
+ ti_sdma_write_4(sc, DMA4_CICR(ch), 0);
/* Make sure the DMA transfer is stopped. */
- omap_dma_write_4(sc, DMA4_CCR(ch), 0);
+ ti_sdma_write_4(sc, DMA4_CCR(ch), 0);
/* Clear the CSR register and IRQ status register */
- omap_dma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
+ ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);
for (j = 0; j < NUM_DMA_IRQS; j++) {
- omap_dma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));
+ ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));
}
/* Clear all the channel registers, this should abort any transaction */
for (addr = DMA4_CCR(ch); addr <= DMA4_COLOR(ch); addr += 4)
- omap_dma_write_4(sc, addr, 0x00000000);
+ ti_sdma_write_4(sc, addr, 0x00000000);
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return 0;
}
/**
- * omap_dma_disable_channel_irq - disables IRQ's on the given channel
+ * ti_sdma_disable_channel_irq - disables IRQ's on the given channel
* @ch: the channel to disable IRQ's on
*
* Disable interupt generation for the given channel.
@@ -455,9 +455,9 @@ omap_dma_deactivate_channel(unsigned int
* EH_HANDLED or EH_NOT_HANDLED
*/
int
-omap_dma_disable_channel_irq(unsigned int ch)
+ti_sdma_disable_channel_irq(unsigned int ch)
{
- struct omap_dma_softc *sc = omap_dma_sc;
+ struct ti_sdma_softc *sc = ti_sdma_sc;
uint32_t irq_enable;
unsigned int j;
@@ -465,35 +465,35 @@ omap_dma_disable_channel_irq(unsigned in
if (sc == NULL)
return (ENOMEM);
- OMAP_DMA_LOCK(sc);
+ TI_SDMA_LOCK(sc);
if ((sc->sc_active_channels & (1 << ch)) == 0) {
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return (EINVAL);
}
/* Disable all the individual error conditions */
sc->sc_channel[ch].reg_cicr = 0x0000;
- omap_dma_write_4(sc, DMA4_CICR(ch), 0x0000);
+ ti_sdma_write_4(sc, DMA4_CICR(ch), 0x0000);
/* Disable the channel interrupt enable */
for (j = 0; j < NUM_DMA_IRQS; j++) {
- irq_enable = omap_dma_read_4(sc, DMA4_IRQENABLE_L(j));
+ irq_enable = ti_sdma_read_4(sc, DMA4_IRQENABLE_L(j));
irq_enable &= ~(1 << ch);
- omap_dma_write_4(sc, DMA4_IRQENABLE_L(j), irq_enable);
+ ti_sdma_write_4(sc, DMA4_IRQENABLE_L(j), irq_enable);
}
/* Indicate the registers need to be rewritten on the next transaction */
sc->sc_channel[ch].need_reg_write = 1;
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return (0);
}
/**
- * omap_dma_disable_channel_irq - enables IRQ's on the given channel
+ * ti_sdma_disable_channel_irq - enables IRQ's on the given channel
* @ch: the channel to enable IRQ's on
* @flags: bitmask of interrupt types to enable
*
@@ -514,19 +514,19 @@ omap_dma_disable_channel_irq(unsigned in
* EH_HANDLED or EH_NOT_HANDLED
*/
int
-omap_dma_enable_channel_irq(unsigned int ch, uint32_t flags)
+ti_sdma_enable_channel_irq(unsigned int ch, uint32_t flags)
{
- struct omap_dma_softc *sc = omap_dma_sc;
+ struct ti_sdma_softc *sc = ti_sdma_sc;
uint32_t irq_enable;
/* Sanity check */
if (sc == NULL)
return (ENOMEM);
- OMAP_DMA_LOCK(sc);
+ TI_SDMA_LOCK(sc);
if ((sc->sc_active_channels & (1 << ch)) == 0) {
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return (EINVAL);
}
@@ -537,24 +537,24 @@ omap_dma_enable_channel_irq(unsigned int
sc->sc_channel[ch].reg_cicr = flags;
/* Write the values to the register */
- omap_dma_write_4(sc, DMA4_CICR(ch), flags);
+ ti_sdma_write_4(sc, DMA4_CICR(ch), flags);
/* Enable the channel interrupt enable */
- irq_enable = omap_dma_read_4(sc, DMA4_IRQENABLE_L(0));
+ irq_enable = ti_sdma_read_4(sc, DMA4_IRQENABLE_L(0));
irq_enable |= (1 << ch);
- omap_dma_write_4(sc, DMA4_IRQENABLE_L(0), irq_enable);
+ ti_sdma_write_4(sc, DMA4_IRQENABLE_L(0), irq_enable);
/* Indicate the registers need to be rewritten on the next transaction */
sc->sc_channel[ch].need_reg_write = 1;
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return (0);
}
/**
- * omap_dma_get_channel_status - returns the status of a given channel
+ * ti_sdma_get_channel_status - returns the status of a given channel
* @ch: the channel number to get the status of
* @status: upon return will contain the status bitmask, see below for possible
* values.
@@ -580,25 +580,25 @@ omap_dma_enable_channel_irq(unsigned int
* EH_HANDLED or EH_NOT_HANDLED
*/
int
-omap_dma_get_channel_status(unsigned int ch, uint32_t *status)
+ti_sdma_get_channel_status(unsigned int ch, uint32_t *status)
{
- struct omap_dma_softc *sc = omap_dma_sc;
+ struct ti_sdma_softc *sc = ti_sdma_sc;
uint32_t csr;
/* Sanity check */
if (sc == NULL)
return (ENOMEM);
- OMAP_DMA_LOCK(sc);
+ TI_SDMA_LOCK(sc);
if ((sc->sc_active_channels & (1 << ch)) == 0) {
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return (EINVAL);
}
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
- csr = omap_dma_read_4(sc, DMA4_CSR(ch));
+ csr = ti_sdma_read_4(sc, DMA4_CSR(ch));
if (status != NULL)
*status = csr;
@@ -607,13 +607,13 @@ omap_dma_get_channel_status(unsigned int
}
/**
- * omap_dma_start_xfer - starts a DMA transfer
+ * ti_sdma_start_xfer - starts a DMA transfer
* @ch: the channel number to set the endianess of
* @src_paddr: the source phsyical address
* @dst_paddr: the destination phsyical address
* @frmcnt: the number of frames per block
* @elmcnt: the number of elements in a frame, an element is either an 8, 16
- * or 32-bit value as defined by omap_dma_set_xfer_burst()
+ * or 32-bit value as defined by ti_sdma_set_xfer_burst()
*
*
* LOCKING:
@@ -623,80 +623,80 @@ omap_dma_get_channel_status(unsigned int
* EH_HANDLED or EH_NOT_HANDLED
*/
int
-omap_dma_start_xfer(unsigned int ch, unsigned int src_paddr,
+ti_sdma_start_xfer(unsigned int ch, unsigned int src_paddr,
unsigned long dst_paddr,
unsigned int frmcnt, unsigned int elmcnt)
{
- struct omap_dma_softc *sc = omap_dma_sc;
- struct omap_dma_channel *channel;
+ struct ti_sdma_softc *sc = ti_sdma_sc;
+ struct ti_sdma_channel *channel;
uint32_t ccr;
/* Sanity check */
if (sc == NULL)
return (ENOMEM);
- OMAP_DMA_LOCK(sc);
+ TI_SDMA_LOCK(sc);
if ((sc->sc_active_channels & (1 << ch)) == 0) {
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return (EINVAL);
}
channel = &sc->sc_channel[ch];
/* a) Write the CSDP register */
- omap_dma_write_4(sc, DMA4_CSDP(ch),
+ ti_sdma_write_4(sc, DMA4_CSDP(ch),
channel->reg_csdp | DMA4_CSDP_WRITE_MODE(1));
/* b) Set the number of element per frame CEN[23:0] */
- omap_dma_write_4(sc, DMA4_CEN(ch), elmcnt);
+ ti_sdma_write_4(sc, DMA4_CEN(ch), elmcnt);
/* c) Set the number of frame per block CFN[15:0] */
- omap_dma_write_4(sc, DMA4_CFN(ch), frmcnt);
+ ti_sdma_write_4(sc, DMA4_CFN(ch), frmcnt);
/* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0] */
- omap_dma_write_4(sc, DMA4_CSSA(ch), src_paddr);
- omap_dma_write_4(sc, DMA4_CDSA(ch), dst_paddr);
+ ti_sdma_write_4(sc, DMA4_CSSA(ch), src_paddr);
+ ti_sdma_write_4(sc, DMA4_CDSA(ch), dst_paddr);
/* e) Write the CCR register */
- omap_dma_write_4(sc, DMA4_CCR(ch), channel->reg_ccr);
+ ti_sdma_write_4(sc, DMA4_CCR(ch), channel->reg_ccr);
/* f) - Set the source element index increment CSEI[15:0] */
- omap_dma_write_4(sc, DMA4_CSE(ch), 0x0001);
+ ti_sdma_write_4(sc, DMA4_CSE(ch), 0x0001);
/* - Set the source frame index increment CSFI[15:0] */
- omap_dma_write_4(sc, DMA4_CSF(ch), 0x0001);
+ ti_sdma_write_4(sc, DMA4_CSF(ch), 0x0001);
/* - Set the destination element index increment CDEI[15:0]*/
- omap_dma_write_4(sc, DMA4_CDE(ch), 0x0001);
+ ti_sdma_write_4(sc, DMA4_CDE(ch), 0x0001);
/* - Set the destination frame index increment CDFI[31:0] */
- omap_dma_write_4(sc, DMA4_CDF(ch), 0x0001);
+ ti_sdma_write_4(sc, DMA4_CDF(ch), 0x0001);
/* Clear the status register */
- omap_dma_write_4(sc, DMA4_CSR(ch), 0x1FFE);
+ ti_sdma_write_4(sc, DMA4_CSR(ch), 0x1FFE);
/* Write the start-bit and away we go */
- ccr = omap_dma_read_4(sc, DMA4_CCR(ch));
+ ccr = ti_sdma_read_4(sc, DMA4_CCR(ch));
ccr |= (1 << 7);
- omap_dma_write_4(sc, DMA4_CCR(ch), ccr);
+ ti_sdma_write_4(sc, DMA4_CCR(ch), ccr);
/* Clear the reg write flag */
channel->need_reg_write = 0;
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return (0);
}
/**
- * omap_dma_start_xfer_packet - starts a packet DMA transfer
+ * ti_sdma_start_xfer_packet - starts a packet DMA transfer
* @ch: the channel number to use for the transfer
* @src_paddr: the source physical address
* @dst_paddr: the destination physical address
* @frmcnt: the number of frames to transfer
* @elmcnt: the number of elements in a frame, an element is either an 8, 16
- * or 32-bit value as defined by omap_dma_set_xfer_burst()
+ * or 32-bit value as defined by ti_sdma_set_xfer_burst()
* @pktsize: the number of elements in each transfer packet
*
* The @frmcnt and @elmcnt define the overall number of bytes to transfer,
@@ -717,22 +717,22 @@ omap_dma_start_xfer(unsigned int ch, uns
* EH_HANDLED or EH_NOT_HANDLED
*/
int
-omap_dma_start_xfer_packet(unsigned int ch, unsigned int src_paddr,
+ti_sdma_start_xfer_packet(unsigned int ch, unsigned int src_paddr,
unsigned long dst_paddr, unsigned int frmcnt,
unsigned int elmcnt, unsigned int pktsize)
{
- struct omap_dma_softc *sc = omap_dma_sc;
- struct omap_dma_channel *channel;
+ struct ti_sdma_softc *sc = ti_sdma_sc;
+ struct ti_sdma_channel *channel;
uint32_t ccr;
/* Sanity check */
if (sc == NULL)
return (ENOMEM);
- OMAP_DMA_LOCK(sc);
+ TI_SDMA_LOCK(sc);
if ((sc->sc_active_channels & (1 << ch)) == 0) {
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return (EINVAL);
}
@@ -740,53 +740,53 @@ omap_dma_start_xfer_packet(unsigned int
/* a) Write the CSDP register */
if (channel->need_reg_write)
- omap_dma_write_4(sc, DMA4_CSDP(ch),
+ ti_sdma_write_4(sc, DMA4_CSDP(ch),
channel->reg_csdp | DMA4_CSDP_WRITE_MODE(1));
/* b) Set the number of elements to transfer CEN[23:0] */
- omap_dma_write_4(sc, DMA4_CEN(ch), elmcnt);
+ ti_sdma_write_4(sc, DMA4_CEN(ch), elmcnt);
/* c) Set the number of frames to transfer CFN[15:0] */
- omap_dma_write_4(sc, DMA4_CFN(ch), frmcnt);
+ ti_sdma_write_4(sc, DMA4_CFN(ch), frmcnt);
/* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0] */
- omap_dma_write_4(sc, DMA4_CSSA(ch), src_paddr);
- omap_dma_write_4(sc, DMA4_CDSA(ch), dst_paddr);
+ ti_sdma_write_4(sc, DMA4_CSSA(ch), src_paddr);
+ ti_sdma_write_4(sc, DMA4_CDSA(ch), dst_paddr);
/* e) Write the CCR register */
- omap_dma_write_4(sc, DMA4_CCR(ch),
+ ti_sdma_write_4(sc, DMA4_CCR(ch),
channel->reg_ccr | DMA4_CCR_PACKET_TRANS);
/* f) - Set the source element index increment CSEI[15:0] */
- omap_dma_write_4(sc, DMA4_CSE(ch), 0x0001);
+ ti_sdma_write_4(sc, DMA4_CSE(ch), 0x0001);
/* - Set the packet size, this is dependent on the sync source */
if (channel->reg_ccr & DMA4_CCR_SEL_SRC_DST_SYNC(1))
- omap_dma_write_4(sc, DMA4_CSF(ch), pktsize);
+ ti_sdma_write_4(sc, DMA4_CSF(ch), pktsize);
else
- omap_dma_write_4(sc, DMA4_CDE(ch), pktsize);
+ ti_sdma_write_4(sc, DMA4_CDE(ch), pktsize);
/* - Set the destination frame index increment CDFI[31:0] */
- omap_dma_write_4(sc, DMA4_CDF(ch), 0x0001);
+ ti_sdma_write_4(sc, DMA4_CDF(ch), 0x0001);
/* Clear the status register */
- omap_dma_write_4(sc, DMA4_CSR(ch), 0x1FFE);
+ ti_sdma_write_4(sc, DMA4_CSR(ch), 0x1FFE);
/* Write the start-bit and away we go */
- ccr = omap_dma_read_4(sc, DMA4_CCR(ch));
+ ccr = ti_sdma_read_4(sc, DMA4_CCR(ch));
ccr |= (1 << 7);
- omap_dma_write_4(sc, DMA4_CCR(ch), ccr);
+ ti_sdma_write_4(sc, DMA4_CCR(ch), ccr);
/* Clear the reg write flag */
channel->need_reg_write = 0;
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return (0);
}
/**
- * omap_dma_stop_xfer - stops any currently active transfers
+ * ti_sdma_stop_xfer - stops any currently active transfers
* @ch: the channel number to set the endianess of
*
* This function call is effectively a NOP if no transaction is in progress.
@@ -798,44 +798,44 @@ omap_dma_start_xfer_packet(unsigned int
* EH_HANDLED or EH_NOT_HANDLED
*/
int
-omap_dma_stop_xfer(unsigned int ch)
+ti_sdma_stop_xfer(unsigned int ch)
{
- struct omap_dma_softc *sc = omap_dma_sc;
+ struct ti_sdma_softc *sc = ti_sdma_sc;
unsigned int j;
/* Sanity check */
if (sc == NULL)
return (ENOMEM);
- OMAP_DMA_LOCK(sc);
+ TI_SDMA_LOCK(sc);
if ((sc->sc_active_channels & (1 << ch)) == 0) {
- OMAP_DMA_UNLOCK(sc);
+ TI_SDMA_UNLOCK(sc);
return (EINVAL);
}
/* Disable all DMA interrupts for the channel. */
- omap_dma_write_4(sc, DMA4_CICR(ch), 0);
+ ti_sdma_write_4(sc, DMA4_CICR(ch), 0);
/* Make sure the DMA transfer is stopped. */
- omap_dma_write_4(sc, DMA4_CCR(ch), 0);
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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