svn commit: r223357 -
projects/llvm-ia64/contrib/llvm/lib/Target/IA64
Marcel Moolenaar
marcel at FreeBSD.org
Tue Jun 21 05:27:50 UTC 2011
Author: marcel
Date: Tue Jun 21 05:27:49 2011
New Revision: 223357
URL: http://svn.freebsd.org/changeset/base/223357
Log:
o Implement IA64TargetLowering::LowerFormalArguments() for just a single
case.
o Implement IA64TargetLowering::LowerReturn() as empty.
o Give a stab at IA64CallingConv.td
We now reach IA64FrameLowering::emitPrologue()
Added:
projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64CallingConv.td
Modified:
projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64.td
projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64FrameLowering.cpp
projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.cpp
projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.h
Modified: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64.td
==============================================================================
--- projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64.td Tue Jun 21 04:46:00 2011 (r223356)
+++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64.td Tue Jun 21 05:27:49 2011 (r223357)
@@ -35,6 +35,14 @@ def F2 : IA64Register<"f2">;
def F3 : IA64Register<"f3">;
def F4 : IA64Register<"f4">;
def F5 : IA64Register<"f5">;
+def F8 : IA64Register<"f8">;
+def F9 : IA64Register<"f9">;
+def F10 : IA64Register<"f10">;
+def F11 : IA64Register<"f11">;
+def F12 : IA64Register<"f12">;
+def F13 : IA64Register<"f13">;
+def F14 : IA64Register<"f14">;
+def F15 : IA64Register<"f15">;
def F16 : IA64Register<"f16">;
def F17 : IA64Register<"f17">;
def F18 : IA64Register<"f18">;
@@ -115,8 +123,18 @@ def R4 : IA64Register<"r4">;
def R5 : IA64Register<"r5">;
def R6 : IA64Register<"r6">;
def R7 : IA64Register<"r7">;
+def R8 : IA64Register<"r8">;
def R12 : IA64Register<"r12">;
def R13 : IA64Register<"r13">;
+// XXX
+def R32 : IA64Register<"r32">;
+def R33 : IA64Register<"r33">;
+def R34 : IA64Register<"r34">;
+def R35 : IA64Register<"r35">;
+def R36 : IA64Register<"r36">;
+def R37 : IA64Register<"r37">;
+def R38 : IA64Register<"r38">;
+def R39 : IA64Register<"r39">;
// Branch registers
def B1 : IA64Register<"b1">;
@@ -134,10 +152,11 @@ class IA64RegisterClass<list<ValueType>
def Branch : IA64RegisterClass<[i64], 8,
[B1, B2, B3, B4, B5]>;
def FloatingPoint : IA64RegisterClass<[f128], 128,
- [F0, F1, F2, F3, F4, F5, F16, F17, F18, F19, F20, F21, F22, F23,
- F24, F25, F26, F27, F28, F29, F30, F31]>;
+ [F0, F1, F2, F3, F4, F5, F8, F9, F10, F11, F12, F13, F14, F15, F16,
+ F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
+ F30, F31]>;
def General : IA64RegisterClass<[i64], 64,
- [R0, R1, R4, R5, R6, R7, R12, R13]>;
+ [R0, R1, R4, R5, R6, R7, R8, R12, R13]>;
def Predicate : IA64RegisterClass<[i1], 0,
[P0, P1, P2, P3, P4, P5, P16, P17, P18, P19, P20, P21, P22, P23,
P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35, P36,
@@ -146,6 +165,11 @@ def Predicate : IA64RegisterClass<[i1],
P63]>;
//
+// Calling Convention
+//
+include "IA64CallingConv.td"
+
+//
// Instructions
//
class IA64Instruction<dag outs, dag ins> : Instruction {
Added: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64CallingConv.td
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64CallingConv.td Tue Jun 21 05:27:49 2011 (r223357)
@@ -0,0 +1,42 @@
+def RetCC_IA64 : CallingConv<[
+ CCIfType<[i64], CCAssignToReg<[R8]>>,
+
+ // XXX i128 is returned in the pair {r8,r9}. Custom rule needed?
+
+ // FP values are returned in the register format, but rounded to
+ // the appropriate precision.
+ CCIfType<[f32, f64, f80], CCAssignToReg<[F8]>>
+
+ // XXX f128 is returned in the pair {f8,f9}. Custom rule needed?
+
+ // XXX HFAs (Momogeneous FP aggregates) up to 8 elements or fields are
+ // treated specially. Each element or field is assigned to a FP register
+ // (in order) from the set [f8, f9, f10, f11, f12, f13, f14, f15].
+
+ // XXX Aggregates up to 256 bits in size are assigned to registers (in
+ // order) from the set [r8, r9, r10, r11].
+
+ // Aggregates larger than 256 bits are returned in memory.
+]>;
+
+def CC_IA64 : CallingConv<[
+ // XXX There's a 1-to-1 mapping between general registers and slots.
+ // As such, if an argument is to be passed in a FP register, the
+ // general register corresponding to that slot cannot be used anymore.
+ // This isn't handled (yet).
+ CCIfType<[i64], CCAssignToReg<[R32, R33, R34, R35, R36, R37, R38, R39]>>,
+
+ // XXX i128 is assigned 2 consecutive registers/slots, aligned at the
+ // next even slot.
+
+ // FP registers are assigned in sequence. For the vararg case, this
+ // works differently. This isn't handled (yet).
+ CCIfNotVarArg<CCIfType<[f32, f64],
+ CCAssignToReg<[F8, F9, F10, F11, F12, F13, F14, F15]>>>,
+
+ // XXX f80 and f128 occupy 2 consecutive slots, aligned at the
+ // next even slot.
+
+ CCIfType<[i64, f32, f64], CCAssignToStack<8, 8>>,
+ CCIfType<[f80, f128], CCAssignToStack<16, 16>>
+]>;
Modified: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64FrameLowering.cpp
==============================================================================
--- projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64FrameLowering.cpp Tue Jun 21 04:46:00 2011 (r223356)
+++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64FrameLowering.cpp Tue Jun 21 05:27:49 2011 (r223357)
@@ -1,5 +1,6 @@
#include "IA64FrameLowering.h"
#include "IA64InstrInfo.h"
+#include "IA64MachineFunctionInfo.h"
#include "llvm/Function.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -16,6 +17,12 @@ using namespace llvm;
void
IA64FrameLowering::emitPrologue(MachineFunction &MF) const
{
+ IA64MachineFunctionInfo *IA64FI = MF.getInfo<IA64MachineFunctionInfo>();
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ MachineBasicBlock &MBB = MF.front();
+ const IA64InstrInfo &TII =
+ *static_cast<const IA64InstrInfo*>(MF.getTarget().getInstrInfo());
+
llvm_unreachable(__func__);
}
Modified: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.cpp
==============================================================================
--- projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.cpp Tue Jun 21 04:46:00 2011 (r223356)
+++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.cpp Tue Jun 21 05:27:49 2011 (r223357)
@@ -1,3 +1,5 @@
+#define DEBUG_TYPE "ia64-target-lowering"
+
#include "IA64.h"
#include "IA64Subtarget.h"
#include "IA64TargetLowering.h"
@@ -48,3 +50,37 @@ IA64TargetLowering::IA64TargetLowering(I
setJumpBufSize(512);
setJumpBufAlignment(16);
}
+
+SDValue
+IA64TargetLowering::LowerFormalArguments(SDValue Chain,
+ CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const
+{
+ MachineFunction &MF = DAG.getMachineFunction();
+ SDValue Val;
+
+ for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
+ EVT vt = Ins[ArgNo].VT;
+
+ unsigned VReg =
+ MF.getRegInfo().createVirtualRegister(&IA64::GeneralRegClass);
+ MF.getRegInfo().addLiveIn(IA64::R32, VReg);
+ Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
+ InVals.push_back(Val);
+
+ DEBUG(dbgs() << ArgNo << ": " << vt.getSimpleVT().SimpleTy << " -> " <<
+ VReg << "\n:");
+ }
+
+ return Chain;
+}
+
+SDValue
+IA64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
+ bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl,
+ SelectionDAG &DAG) const
+{
+ return Chain;
+}
Modified: projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.h
==============================================================================
--- projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.h Tue Jun 21 04:46:00 2011 (r223356)
+++ projects/llvm-ia64/contrib/llvm/lib/Target/IA64/IA64TargetLowering.h Tue Jun 21 05:27:49 2011 (r223357)
@@ -17,6 +17,16 @@ namespace llvm {
public:
explicit IA64TargetLowering(IA64TargetMachine &TM);
+
+ virtual SDValue LowerFormalArguments(SDValue Chain,
+ CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl,
+ SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
+
+ virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
+ bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl,
+ SelectionDAG &DAG) const;
};
} // namespace llvm
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