svn commit: r194140 - in projects/mips/sys/mips: conf mips4k
mips4k/octeon32
Warner Losh
imp at FreeBSD.org
Sun Jun 14 02:46:08 UTC 2009
Author: imp
Date: Sun Jun 14 02:46:07 2009
New Revision: 194140
URL: http://svn.freebsd.org/changeset/base/194140
Log:
Import Cavium's FreeBSD port, or the Octeon specific pieces, verbatim.
Yes, this puts things in the wrong place, doesn't compile and is
woefully incomplete. However, it will allow us to more easily track
against the upstream sources without needing to import the entire
Cavium tree under vendor.
This port is based on FreeBSD 7.0 as of April 2007 and the pre-import
MIPS tree (aka mips2), so much work is necessary here.
Added:
projects/mips/sys/mips/conf/OCTEON.hints
projects/mips/sys/mips/conf/OCTEON32
projects/mips/sys/mips/mips4k/
projects/mips/sys/mips/mips4k/octeon32/
projects/mips/sys/mips/mips4k/octeon32/asm_octeon.S (contents, props changed)
projects/mips/sys/mips/mips4k/octeon32/files.octeon32
projects/mips/sys/mips/mips4k/octeon32/obio.c (contents, props changed)
projects/mips/sys/mips/mips4k/octeon32/obiovar.h (contents, props changed)
projects/mips/sys/mips/mips4k/octeon32/octeon_machdep.c (contents, props changed)
projects/mips/sys/mips/mips4k/octeon32/octeonreg.h (contents, props changed)
projects/mips/sys/mips/mips4k/octeon32/std.octeon32
projects/mips/sys/mips/mips4k/octeon32/uart_bus_octeonusart.c (contents, props changed)
projects/mips/sys/mips/mips4k/octeon32/uart_cpu_octeonusart.c (contents, props changed)
projects/mips/sys/mips/mips4k/std.mips4k
Added: projects/mips/sys/mips/conf/OCTEON.hints
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/conf/OCTEON.hints Sun Jun 14 02:46:07 2009 (r194140)
@@ -0,0 +1,13 @@
+# /*
+# * This product includes software developed by the University of
+
+# * California, Berkeley and its contributors."
+# */
+# device.hints
+hw.uart.console="io:0x1"
+hint.obio.0.at="nexus"
+hint.obio.0.maddr="0x1"
+hint.obio.0.flags="0x1"
+hint.uart.0.at="obio"
+hint.uart.0.maddr="0x1"
+hint.uart.0.flags="0x1"
Added: projects/mips/sys/mips/conf/OCTEON32
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/conf/OCTEON32 Sun Jun 14 02:46:07 2009 (r194140)
@@ -0,0 +1,83 @@
+# QEMU -- Generic kernel configuration file for FreeBSD/mips
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD$
+
+machine mips
+cpu CPU_MIPS4KC
+ident CAVIUM
+
+#makeoptions ARCH_FLAGS=-march=mips32
+
+# Don't build any modules yet.
+makeoptions MODULES_OVERRIDE=""
+
+options KERNVIRTADDR=0x80100000
+include "../mips4k/octeon32/std.octeon32"
+
+hints "OCTEON.hints" #Default places to look for devices.
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options NFSCLIENT #Network Filesystem Client
+#options NFS_ROOT #NFS usable as /, requires NFSCLIENT
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+#options ROOTDEVNAME=\"ufs:ad0s1a\" # Original
+options NO_SWAPPING
+
+
+options FFS #Berkeley Fast Filesystem
+options SOFTUPDATES #Enable FFS soft updates support
+options UFS_ACL #Support for access control lists
+options UFS_DIRHASH #Improve performance on big directories
+
+
+# Debugging for use in -current
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+
+device genclock
+device loop
+device ether
+device md
+device mem
+device uart
+device uart_oct16550
+device rgmii
+#options VERBOSE_SYSINIT
+
+
+#
+# Use the following for Compact Flash file-system
+device cf
+options ROOTDEVNAME = \"ufs:cf0s2\" # Unmask if compact flash is needed as RFS
+
+#
+# Use the following for RFS in mem-device
+#options MD_ROOT
+#options ROOTDEVNAME = \"ufs:md0\"
+
+#options MD_ROOT_SIZE = 21264
+options SMP
Added: projects/mips/sys/mips/mips4k/octeon32/asm_octeon.S
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/mips4k/octeon32/asm_octeon.S Sun Jun 14 02:46:07 2009 (r194140)
@@ -0,0 +1,143 @@
+
+#include <machine/asm.h>
+#include <machine/cache_r4k.h>
+#include <machine/cpuregs.h>
+#include <machine/param.h>
+#include <machine/pte.h>
+
+#include "assym.s"
+
+
+
+#define CPU_DISABLE_INTERRUPTS(reg, reg2, reg3) \
+ mfc0 reg, MIPS_COP_0_STATUS; \
+ nop; \
+ move reg3, reg; \
+ li reg2, ~MIPS_SR_INT_IE; \
+ and reg, reg2, reg; \
+ mtc0 reg, MIPS_COP_0_STATUS; \
+ COP0_SYNC
+
+
+
+#define CPU_ENABLE_INTERRUPTS(reg, reg3) \
+ mfc0 reg, MIPS_COP_0_STATUS; \
+ nop; \
+ or reg, reg, reg3; \
+ mtc0 reg, MIPS_COP_0_STATUS; \
+ COP0_SYNC
+
+
+#define PUSHR(reg) \
+ addiu sp,sp,-16 ; \
+ sd reg, 8(sp) ; \
+ nop ;
+
+#define POPR(reg) \
+ ld reg, 8(sp) ; \
+ addiu sp,sp,16 ; \
+ nop ;
+
+
+
+
+/*
+ * octeon_ciu_get_interrupt_reg_addr
+ *
+ * Given Int-X, En-X combination, return the CIU Interrupt Enable Register addr
+ * a0 = ciu Int-X: 0/1
+ * a1 = ciu EN-0: 0/1
+ */
+LEAF(octeon_ciu_get_interrupt_reg_addr)
+ .set noreorder
+ .set mips3
+
+ beqz a0, ciu_get_interrupt_reg_addr_Int_0
+ nop
+
+ciu_get_interrupt_reg_addr_Int_1:
+ beqz a1, ciu_get_interrupt_reg_addr_Int_1_En_0
+ nop
+
+ciu_get_interrupt_reg_addr_Int_1_En1:
+ li a0, OCTEON_CIU_ADDR_HI
+ dsll32 a0, a0, 0
+ nop
+ ori a0, OCTEON_CIU_EN1_INT1_LO
+ j ciu_get_interrupt_reg_addr_ret
+ nop
+
+ciu_get_interrupt_reg_addr_Int_1_En_0:
+ li a0, OCTEON_CIU_ADDR_HI
+ dsll32 a0, a0, 0
+ nop
+ ori a0, OCTEON_CIU_EN0_INT1_LO
+ j ciu_get_interrupt_reg_addr_ret
+ nop
+
+ciu_get_interrupt_reg_addr_Int_0:
+ beqz a1, ciu_get_interrupt_reg_addr_Int_0_En_0
+ nop
+
+ciu_get_interrupt_reg_addr_Int_0_En_1:
+ li a0, OCTEON_CIU_ADDR_HI
+ dsll32 a0, a0, 0
+ nop
+ ori a0, OCTEON_CIU_EN1_INT0_LO
+ j ciu_get_interrupt_reg_addr_ret
+ nop
+
+ciu_get_interrupt_reg_addr_Int_0_En_0:
+ li a0, OCTEON_CIU_ADDR_HI
+ dsll32 a0, a0, 0
+ nop
+ ori a0, OCTEON_CIU_EN0_INT0_LO
+
+
+ciu_get_interrupt_reg_addr_ret:
+ j ra
+ nop
+
+ .set mips0
+ .set reorder
+END(octeon_ciu_get_interrupt_reg_addr)
+
+
+
+/*
+ * octeon_ciu_mask_all_interrupts
+ *
+ * a0 = ciu Interrupt-X: 0/1
+ * a1 = ciu Enable-X: 0/1
+ */
+LEAF(octeon_ciu_mask_all_interrupts)
+ .set noreorder
+ .set mips3
+
+ PUSHR(ra)
+ PUSHR(s0)
+
+ move t0, a0
+ move t1, a1
+ li a0, MIPS_SR_INT_IE
+ CPU_DISABLE_INTERRUPTS(a2, a1, s0)
+ move a0, t0
+ move t1, a1
+ jal octeon_ciu_get_interrupt_reg_addr
+ nop
+ ld a2, 0(a0) # Dummy read
+ nop
+ move a2, zero # Clear all
+ sd a2, 0(a0) # Write new Enable bits
+ nop
+ CPU_ENABLE_INTERRUPTS(a2, s0)
+
+ POPR(s0)
+ POPR(ra)
+ j ra # Return
+ nop # (bd slot)
+
+ .set mips0
+ .set reorder
+END(octeon_ciu_mask_all_interrupts)
+
Added: projects/mips/sys/mips/mips4k/octeon32/files.octeon32
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/mips4k/octeon32/files.octeon32 Sun Jun 14 02:46:07 2009 (r194140)
@@ -0,0 +1,21 @@
+# /*
+# * This product includes software developed by the University of
+# * California, Berkeley and its contributors."
+# */
+# $FreeBSD$
+# Octeon Support Files
+#
+mips/mips4k/octeon32/obio.c optional uart
+mips/mips4k/octeon32/uart_cpu_octeonusart.c optional uart
+mips/mips4k/octeon32/uart_bus_octeonusart.c optional uart
+dev/uart/uart_dev_oct16550.c optional uart
+mips/mips/mp_machdep.c optional smp
+mips/mips4k/octeon32/octeon_machdep.c standard
+
+dev/flash/octeon_ebt3000_cf.c optional cf
+
+dev/le/octeon_fau.c optional rgmii
+dev/le/octeon_fpa.c optional rgmii
+dev/le/octeon_ipd.c optional rgmii
+dev/le/octeon_pko.c optional rgmii
+dev/le/octeon_rgmx.c optional rgmii
Added: projects/mips/sys/mips/mips4k/octeon32/obio.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/mips4k/octeon32/obio.c Sun Jun 14 02:46:07 2009 (r194140)
@@ -0,0 +1,185 @@
+/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */
+
+/*-
+ * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * On-board device autoconfiguration support for Intel IQ80321
+ * evaluation boards.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <mips/mips4k/octeon32/octeonreg.h>
+#include <mips/mips4k/octeon32/obiovar.h>
+
+int obio_probe(device_t);
+int obio_attach(device_t);
+
+/*
+ * We need only one obio.
+ * Any other device hanging off of it, shouldn't cause multiple of
+ * these to be found.
+ */
+static int have_one = 0;
+
+int
+obio_probe(device_t dev)
+{
+ if(!have_one)
+ {
+ have_one = 1;
+ return 0;
+ }
+ else
+ return (ENXIO);
+}
+
+int
+obio_attach(device_t dev)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+
+ sc->oba_st = MIPS_BUS_SPACE_IO;
+ sc->oba_addr = OCTEON_UART0ADR;
+ sc->oba_size = 0x10000;
+ sc->oba_rman.rm_type = RMAN_ARRAY;
+ sc->oba_rman.rm_descr = "OBIO I/O";
+ if (rman_init(&sc->oba_rman) != 0 ||
+ rman_manage_region(&sc->oba_rman,
+ sc->oba_addr, sc->oba_addr + sc->oba_size) != 0)
+ panic("obio_attach: failed to set up I/O rman");
+ sc->oba_irq_rman.rm_type = RMAN_ARRAY;
+ sc->oba_irq_rman.rm_descr = "OBIO IRQ";
+
+ /*
+ * This module is intended for UART purposes only and
+ * it's IRQ is 0 corresponding to IP2.
+ */
+ if (rman_init(&sc->oba_irq_rman) != 0 ||
+ rman_manage_region(&sc->oba_irq_rman, 0, 0) != 0)
+ panic("obio_attach: failed to set up IRQ rman");
+
+ device_add_child(dev, "uart", 1); /* Setup Uart-1 first. */
+ device_add_child(dev, "uart", 0); /* Uart-0 next. So it is first in console list */
+ bus_generic_probe(dev);
+ bus_generic_attach(dev);
+ return (0);
+}
+
+static struct resource *
+obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct resource *rv;
+ struct rman *rm;
+ bus_space_tag_t bt = 0;
+ bus_space_handle_t bh = 0;
+ struct obio_softc *sc = device_get_softc(bus);
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &sc->oba_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ return (NULL);
+ case SYS_RES_IOPORT:
+ rm = &sc->oba_rman;
+ bt = sc->oba_st;
+ bh = device_get_unit(child) ? OCTEON_UART1ADR : OCTEON_UART0ADR;
+ start = bh;
+ break;
+ default:
+ return (NULL);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == NULL) {
+ return (NULL);
+ }
+ if (type == SYS_RES_IRQ) {
+ return (rv);
+ }
+ rman_set_rid(rv, *rid);
+ rman_set_bustag(rv, bt);
+ rman_set_bushandle(rv, bh);
+
+ if (0) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ rman_release_resource(rv);
+ return (NULL);
+ }
+ }
+ return (rv);
+
+}
+
+static int
+obio_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ return (0);
+}
+static device_method_t obio_methods[] = {
+ DEVMETHOD(device_probe, obio_probe),
+ DEVMETHOD(device_attach, obio_attach),
+
+ DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
+ DEVMETHOD(bus_activate_resource, obio_activate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ {0, 0},
+};
+
+static driver_t obio_driver = {
+ "obio",
+ obio_methods,
+ sizeof(struct obio_softc),
+};
+static devclass_t obio_devclass;
+
+DRIVER_MODULE(obio, nexus, obio_driver, obio_devclass, 0, 0);
Added: projects/mips/sys/mips/mips4k/octeon32/obiovar.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/mips4k/octeon32/obiovar.h Sun Jun 14 02:46:07 2009 (r194140)
@@ -0,0 +1,58 @@
+/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#ifndef _OCTEON_OBIOVAR_H_
+#define _OCTEON_OBIOVAR_H_
+
+#include <sys/rman.h>
+
+struct obio_softc {
+ bus_space_tag_t oba_st; /* bus space tag */
+ bus_addr_t oba_addr; /* address of device */
+ bus_size_t oba_size; /* size of device */
+ int oba_width; /* bus width */
+ int oba_irq; /* XINT interrupt bit # */
+ struct rman oba_rman;
+ struct rman oba_irq_rman;
+
+};
+extern struct bus_space obio_bs_tag;
+
+#endif /* _OCTEON_OBIOVAR_H_ */
Added: projects/mips/sys/mips/mips4k/octeon32/octeon_machdep.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/mips4k/octeon32/octeon_machdep.c Sun Jun 14 02:46:07 2009 (r194140)
@@ -0,0 +1,914 @@
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <machine/cpuregs.h>
+#include <machine/cpufunc.h>
+#include <mips/mips4k/octeon32/octeonreg.h>
+#include <machine/atomic.h>
+#include <machine/pcpu.h>
+
+#if defined(__mips_n64)
+ #define MAX_APP_DESC_ADDR 0xffffffffafffffff
+#else
+ #define MAX_APP_DESC_ADDR 0xafffffff
+#endif
+
+
+/*
+ * Perform a board-level soft-reset.
+ * Note that this is not emulated by gxemul.
+ */
+void octeon_reset (void)
+{
+ void (*reset_func)(void) = (void (*)(void) )0x1fc00000;
+ reset_func();
+}
+
+
+static inline uint32_t octeon_disable_interrupts (void)
+{
+ uint32_t status_bits;
+
+ status_bits = mips_rd_status();
+ mips_wr_status(status_bits & ~MIPS_SR_INT_IE);
+ return (status_bits);
+}
+
+
+static inline void octeon_set_interrupts (uint32_t status_bits)
+{
+ mips_wr_status(status_bits);
+}
+
+
+void octeon_led_write_char (int char_position, char val)
+{
+ uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
+
+ if (!octeon_board_real()) return;
+
+ char_position &= 0x7; /* only 8 chars */
+ ptr += char_position;
+ oct_write8_x8(ptr, val);
+}
+
+void octeon_led_write_char0 (char val)
+{
+ uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
+
+ if (!octeon_board_real()) return;
+
+ oct_write8_x8(ptr, val);
+}
+
+void octeon_led_write_hexchar (int char_position, char hexval)
+{
+ uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
+ char char1, char2;
+
+ if (!octeon_board_real()) return;
+
+ char1 = (hexval >> 4) & 0x0f; char1 = (char1 < 10)?char1+'0':char1+'7';
+ char2 = (hexval & 0x0f); char2 = (char2 < 10)?char2+'0':char2+'7';
+ char_position &= 0x7; /* only 8 chars */
+ if (char_position > 6) char_position = 6;
+ ptr += char_position;
+ oct_write8_x8(ptr, char1);
+ ptr++;
+ oct_write8_x8(ptr, char2);
+}
+
+void octeon_led_write_string (const char *str)
+{
+ uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
+ int i;
+
+ if (!octeon_board_real()) return;
+
+ for (i=0; i<8; i++, ptr++) {
+ if (str && *str) {
+ oct_write8_x8(ptr, *str++);
+ } else {
+ oct_write8_x8(ptr, ' ');
+ }
+ oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
+ }
+}
+
+static char progress[8] = { '-', '/', '|', '\\', '-', '/', '|', '\\'};
+
+void octeon_led_run_wheel (/*int count, */int *prog_count, int led_position)
+{
+ if (!octeon_board_real()) return;
+
+ octeon_led_write_char(led_position, progress[*prog_count]);
+ *prog_count += 1;
+ *prog_count &= 0x7;
+}
+
+#define LSR_DATAREADY 0x01 /* Data ready */
+#define LSR_THRE 0x20 /* Transmit holding register empty */
+#define LSR_TEMT 0x40 /* Transmitter Empty. THR, TSR & FIFO */
+#define USR_TXFIFO_NOTFULL 0x02 /* Uart TX FIFO Not full */
+
+/*
+ * octeon_uart_write_byte
+ *
+ * Put out a single byte off of uart port.
+ */
+
+void octeon_uart_write_byte (int uart_index, uint8_t ch)
+{
+ uint64_t val, val2;
+ if ((uart_index < 0) || (uart_index > 1)) {
+ return;
+ }
+
+ while (1) {
+ val = oct_read64(OCTEON_MIO_UART0_LSR + (uart_index * 0x400));
+ val2 = oct_read64(OCTEON_MIO_UART0_USR + (uart_index * 0x400));
+ if ((((uint8_t) val) & LSR_THRE) ||
+ (((uint8_t) val2) & USR_TXFIFO_NOTFULL)) {
+ break;
+ }
+ }
+
+ /* Write the byte */
+ oct_write8(OCTEON_MIO_UART0_THR + (uart_index * 0x400), (uint64_t) ch);
+
+ /* Force Flush the IOBus */
+ oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
+}
+
+
+void octeon_uart_write_byte0 (uint8_t ch)
+{
+ uint64_t val, val2;
+
+ while (1) {
+ val = oct_read64(OCTEON_MIO_UART0_LSR);
+ val2 = oct_read64(OCTEON_MIO_UART0_USR);
+ if ((((uint8_t) val) & LSR_THRE) ||
+ (((uint8_t) val2) & USR_TXFIFO_NOTFULL)) {
+ break;
+ }
+ }
+
+ /* Write the byte */
+ oct_write8(OCTEON_MIO_UART0_THR, (uint64_t) ch);
+
+ /* Force Flush the IOBus */
+ oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
+}
+
+/*
+ * octeon_uart_write_string
+ *
+ */
+void octeon_uart_write_string (int uart_index, const char *str)
+{
+ /* Just loop writing one byte at a time */
+
+ while (*str)
+ {
+ octeon_uart_write_byte(uart_index, *str);
+ if (*str == '\n') {
+ octeon_uart_write_byte(uart_index, '\r');
+ }
+ str++;
+ }
+ }
+
+static char wstr[30];
+
+void octeon_led_write_hex (uint32_t wl)
+{
+ char nbuf[80];
+
+ sprintf(nbuf, "%X", wl);
+ octeon_led_write_string(nbuf);
+}
+
+
+void octeon_uart_write_hex2 (uint32_t wl, uint32_t wh)
+{
+ sprintf(wstr, "0x%X-0x%X ", wh, wl);
+ octeon_uart_write_string(0, wstr);
+}
+
+void octeon_uart_write_hex (uint32_t wl)
+{
+ sprintf(wstr, " 0x%X ", wl);
+ octeon_uart_write_string(0, wstr);
+}
+
+
+#define OCT_CONS_BUFLEN 200
+static char console_str_buff0[OCT_CONS_BUFLEN + 1];
+#include <machine/stdarg.h>
+
+
+//#define USE_KERN_SUBR_PRINTF
+
+#ifndef USE_KERN_SUBR_PRINTF
+static int oct_printf (const char *fmt, va_list ap);
+#endif
+
+int kern_cons_printf (const char *fmt, ...)
+{
+ va_list ap;
+
+ va_start(ap, fmt);
+#ifndef USE_KERN_SUBR_PRINTF
+ oct_printf(fmt, ap);
+#else
+ ker_printf(fmt, ap);
+#endif
+ va_end(ap);
+ return (0);
+}
+
+#ifndef USE_KERN_SUBR_PRINTF
+static int oct_printf (const char *fmt, va_list ap)
+{
+ snprintf(console_str_buff0, OCT_CONS_BUFLEN, fmt, ap);
+ octeon_uart_write_string(0, console_str_buff0);
+ return (0);
+}
+#endif
+
+
+int console_printf (const char *fmt, ...)
+{
+ va_list ap;
+
+ va_start(ap, fmt);
+ sprintf(console_str_buff0, fmt, ap);
+ va_end(ap);
+ octeon_uart_write_string(0, console_str_buff0);
+ return (0);
+}
+
+
+
+
+/*
+ * octeon_wait_uart_flush
+ */
+void octeon_wait_uart_flush (int uart_index, uint8_t ch)
+{
+ uint64_t val;
+ int64_t val3;
+ uint32_t cpu_status_bits;
+
+ if ((uart_index < 0) || (uart_index > 1)) {
+ return;
+ }
+
+ cpu_status_bits = octeon_disable_interrupts();
+ /* Force Flush the IOBus */
+ oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
+ for (val3 = 0xfffffffff; val3 > 0; val3--) {
+ val = oct_read64(OCTEON_MIO_UART0_LSR + (uart_index * 0x400));
+ if (((uint8_t) val) & LSR_TEMT) {
+ break;
+ }
+ }
+ octeon_set_interrupts(cpu_status_bits);
+}
+
+
+/*
+ * octeon_debug_symbol
+ *
+ * Does nothing.
+ * Used to mark the point for simulator to begin tracing
+ */
+void octeon_debug_symbol (void)
+{
+}
+
+void octeon_ciu_stop_gtimer (int timer)
+{
+ oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), 0ll);
+}
+
+void octeon_ciu_start_gtimer (int timer, u_int one_shot, uint64_t time_cycles)
+{
+ octeon_ciu_gentimer gentimer;
+
+ gentimer.word64 = 0;
+ gentimer.bits.one_shot = one_shot;
+ gentimer.bits.len = time_cycles - 1;
+ oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), gentimer.word64);
+}
+
+/*
+ * octeon_ciu_reset
+ *
+ * Shutdown all CIU to IP2, IP3 mappings
+ */
+void octeon_ciu_reset (void)
+{
+
+ octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_0);
+ octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_1);
+ octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_2);
+ octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_3);
+
+ ciu_disable_intr(CIU_THIS_CORE, CIU_INT_0, CIU_EN_0);
+ ciu_disable_intr(CIU_THIS_CORE, CIU_INT_0, CIU_EN_1);
+ ciu_disable_intr(CIU_THIS_CORE, CIU_INT_1, CIU_EN_0);
+ ciu_disable_intr(CIU_THIS_CORE, CIU_INT_1, CIU_EN_1);
+
+ ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_0, CIU_EN_0, 0ll);
+ ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_1, CIU_EN_0, 0ll);
+ ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_1, CIU_EN_1, 0ll);
+}
+
+/*
+ * mips_disable_interrupt_controllers
+ *
+ * Disable interrupts in the CPU controller
+ */
+void mips_disable_interrupt_controls (void)
+{
+ /*
+ * Disable interrupts in CIU.
+ */
+ octeon_ciu_reset();
+}
+
+static uint64_t ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx);
+
+/*
+ * ciu_get_intr_sum_reg_addr
+ */
+static uint64_t ciu_get_intr_sum_reg_addr (int core_num, int intx, int enx)
+{
+ uint64_t ciu_intr_sum_reg_addr;
+
+ if (enx == CIU_EN_0) {
+ ciu_intr_sum_reg_addr = OCTEON_CIU_SUMMARY_BASE_ADDR + (core_num * 0x10) +
+ (intx * 0x8);
+ } else {
+ ciu_intr_sum_reg_addr = OCTEON_CIU_SUMMARY_INT1_ADDR;
+ }
+
+ return (ciu_intr_sum_reg_addr);
+}
+
+
+static uint64_t ciu_get_intr_en_reg_addr(int core_num, int intx, int enx);
+
+/*
+ * ciu_get_intr_en_reg_addr
+ */
+static uint64_t ciu_get_intr_en_reg_addr (int core_num, int intx, int enx)
+{
+ uint64_t ciu_intr_reg_addr;
+
+
+ ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR + ((enx == 0) ? 0x0 : 0x8) +
+ (intx * 0x10) + (core_num * 0x20);
+
+ return (ciu_intr_reg_addr);
+}
+
+
+
+
+uint64_t ciu_get_en_reg_addr_new (int corenum, int intx, int enx, int ciu_ip);
+
+/*
+ * ciu_get_intr_reg_addr
+ *
+ * 200 ---int0,en0 ip2
+ * 208 ---int0,en1 ip2 ----> this is wrong... this is watchdog
+ *
+ * 210 ---int0,en0 ip3 --
+ * 218 ---int0,en1 ip3 ----> same here.. .this is watchdog... right?
+ *
+ * 220 ---int1,en0 ip2
+ * 228 ---int1,en1 ip2
+ * 230 ---int1,en0 ip3 --
+ * 238 ---int1,en1 ip3
+ *
+ */
+uint64_t ciu_get_en_reg_addr_new (int corenum, int intx, int enx, int ciu_ip)
+{
+ uint64_t ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR;
+
+ if (enx < CIU_EN_0 || enx > CIU_EN_1) {
+ printf("%s: invalid enx value %d, should be %d or %d\n",
+ __FUNCTION__, enx, CIU_EN_0, CIU_EN_1);
+ return 0;
+ }
+ if (intx < CIU_INT_0 || intx > CIU_INT_1) {
+ printf("%s: invalid intx value %d, should be %d or %d\n",
+ __FUNCTION__, enx, CIU_INT_0, CIU_INT_1);
+ return 0;
+ }
+ if (ciu_ip < CIU_MIPS_IP2 || ciu_ip > CIU_MIPS_IP3) {
+ printf("%s: invalid ciu_ip value %d, should be %d or %d\n",
+ __FUNCTION__, ciu_ip, CIU_MIPS_IP2, CIU_MIPS_IP3);
+ return 0;
+ }
+
+ ciu_intr_reg_addr += (enx * 0x8);
+ ciu_intr_reg_addr += (ciu_ip * 0x10);
+ ciu_intr_reg_addr += (intx * 0x20);
+
+ return (ciu_intr_reg_addr);
+}
+
+/*
+ * ciu_get_int_summary
+ */
+uint64_t ciu_get_int_summary (int core_num, int intx, int enx)
+{
+ uint64_t ciu_intr_sum_reg_addr;
+
+ if (core_num == CIU_THIS_CORE) {
+ core_num = octeon_get_core_num();
+ }
+ ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx);
+ return (oct_read64(ciu_intr_sum_reg_addr));
+}
+
+//#define DEBUG_CIU 1
+
+#ifdef DEBUG_CIU
+#define DEBUG_CIU_SUM 1
+#define DEBUG_CIU_EN 1
+#endif
+
+
+/*
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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