svn commit: r187415 - in projects/mips/sys: conf dev/siba mips/conf
mips/sentry5
Oleksandr Tymoshenko
gonzo at FreeBSD.org
Sun Jan 18 15:49:03 PST 2009
Author: gonzo
Date: Sun Jan 18 23:49:02 2009
New Revision: 187415
URL: http://svn.freebsd.org/changeset/base/187415
Log:
- Move Silicon Backplanes code out to system-wide level (dev/siba) as
it's going to be used not only for siba5 devices.
Added:
projects/mips/sys/dev/siba/siba_cc.c
- copied unchanged from r187114, projects/mips/sys/mips/sentry5/siba_cc.c
projects/mips/sys/dev/siba/siba_mips.c
- copied unchanged from r187114, projects/mips/sys/mips/sentry5/siba_mips.c
projects/mips/sys/dev/siba/siba_sdram.c
- copied unchanged from r187114, projects/mips/sys/mips/sentry5/siba_sdram.c
Deleted:
projects/mips/sys/mips/sentry5/siba_cc.c
projects/mips/sys/mips/sentry5/siba_mips.c
projects/mips/sys/mips/sentry5/siba_sdram.c
Modified:
projects/mips/sys/conf/files.mips
projects/mips/sys/mips/conf/SENTRY5
projects/mips/sys/mips/sentry5/files.sentry5
Modified: projects/mips/sys/conf/files.mips
==============================================================================
--- projects/mips/sys/conf/files.mips Sun Jan 18 23:34:17 2009 (r187414)
+++ projects/mips/sys/conf/files.mips Sun Jan 18 23:49:02 2009 (r187415)
@@ -95,3 +95,7 @@ dev/cfe/cfe_api.c optional cfe
dev/cfe/cfe_console.c optional cfe_console
#dev/cfe/cfe_resource.c optional cfe # not yet needed
+dev/siba/siba.c optional siba
+dev/siba/siba_pcib.c optional siba pci
+dev/siba/siba_cc.c optional siba
+#mips/sentry5/siba_mips.c optional siba # not yet
Copied: projects/mips/sys/dev/siba/siba_cc.c (from r187114, projects/mips/sys/mips/sentry5/siba_cc.c)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/dev/siba/siba_cc.c Sun Jan 18 23:49:02 2009 (r187415, copy of r187114, projects/mips/sys/mips/sentry5/siba_cc.c)
@@ -0,0 +1,154 @@
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Child driver for ChipCommon core.
+ * This is not MI code at the moment.
+ * Two 16C550 compatible UARTs live here. On the WGT634U, uart1 is the
+ * system console, and uart0 is not pinned out.
+ * Because their presence is conditional, they should probably
+ * be attached from here.
+ * GPIO lives here.
+ * The hardware watchdog lives here.
+ * Clock control registers live here.
+ * You don't need to read them to determine the clock speed on the 5365,
+ * which is always 200MHz and thus may be hardcoded (for now).
+ * Flash config registers live here. There may or may not be system flash.
+ * The external interface bus lives here (conditionally).
+ * There is a JTAG interface here which may be used to attach probes to
+ * the SoC for debugging.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <dev/siba/sibavar.h>
+#include <dev/siba/sibareg.h>
+#include <dev/siba/siba_ids.h>
+
+static int siba_cc_attach(device_t);
+static int siba_cc_probe(device_t);
+static void siba_cc_intr(void *v);
+
+static int
+siba_cc_probe(device_t dev)
+{
+
+ if (siba_get_vendor(dev) == SIBA_VID_BROADCOM &&
+ siba_get_device(dev) == SIBA_DEVID_CHIPCOMMON) {
+ device_set_desc(dev, "ChipCommon core");
+ return (BUS_PROBE_DEFAULT);
+ }
+
+ return (ENXIO);
+}
+
+struct siba_cc_softc {
+ void *notused;
+};
+
+static int
+siba_cc_attach(device_t dev)
+{
+ //struct siba_cc_softc *sc = device_get_softc(dev);
+ struct resource *mem;
+ struct resource *irq;
+ int rid;
+
+ /*
+ * Allocate the resources which the parent bus has already
+ * determined for us.
+ * TODO: interrupt routing
+ */
+#define MIPS_MEM_RID 0x20
+ rid = MIPS_MEM_RID;
+ mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+ if (mem == NULL) {
+ device_printf(dev, "unable to allocate memory\n");
+ return (ENXIO);
+ }
+
+ rid = 0;
+ irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
+ if (irq == NULL) {
+ device_printf(dev, "unable to allocate irq\n");
+ return (ENXIO);
+ }
+
+ /* now setup the interrupt */
+ /* may be fast, exclusive or mpsafe at a later date */
+
+ /*
+ * XXX is this interrupt line in ChipCommon used for anything
+ * other than the uart? in that case we shouldn't hog it ourselves
+ * and let uart claim it to avoid polled mode.
+ */
+ int err;
+ void *cookie;
+ err = bus_setup_intr(dev, irq, INTR_TYPE_TTY, NULL, siba_cc_intr, NULL,
+ &cookie);
+ if (err != 0) {
+ device_printf(dev, "unable to setup intr\n");
+ return (ENXIO);
+ }
+
+ /* TODO: attach uart child */
+
+ return (0);
+}
+
+static void
+siba_cc_intr(void *v)
+{
+
+}
+
+static device_method_t siba_cc_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_attach, siba_cc_attach),
+ DEVMETHOD(device_probe, siba_cc_probe),
+
+ {0, 0},
+};
+
+static driver_t siba_cc_driver = {
+ "siba_cc",
+ siba_cc_methods,
+ sizeof(struct siba_softc),
+};
+static devclass_t siba_cc_devclass;
+
+DRIVER_MODULE(siba_cc, siba, siba_cc_driver, siba_cc_devclass, 0, 0);
Copied: projects/mips/sys/dev/siba/siba_mips.c (from r187114, projects/mips/sys/mips/sentry5/siba_mips.c)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/dev/siba/siba_mips.c Sun Jan 18 23:49:02 2009 (r187415, copy of r187114, projects/mips/sys/mips/sentry5/siba_mips.c)
@@ -0,0 +1,113 @@
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Child driver for MIPS 3302 core.
+ * Interrupt controller registers live here. Interrupts may not be routed
+ * to the MIPS core if they are masked out.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <dev/siba/sibavar.h>
+#include <dev/siba/sibareg.h>
+#include <dev/siba/siba_ids.h>
+
+static int siba_mips_attach(device_t);
+static int siba_mips_probe(device_t);
+
+static int
+siba_mips_probe(device_t dev)
+{
+
+ if (siba_get_vendor(dev) == SIBA_VID_BROADCOM &&
+ siba_get_device(dev) == SIBA_DEVID_MIPS_3302) {
+ device_set_desc(dev, "MIPS 3302 processor");
+ return (BUS_PROBE_DEFAULT);
+ }
+
+ return (ENXIO);
+}
+
+struct siba_mips_softc {
+ void *notused;
+};
+
+static int
+siba_mips_attach(device_t dev)
+{
+ //struct siba_mips_softc *sc = device_get_softc(dev);
+ struct resource *mem;
+ int rid;
+
+ /*
+ * Allocate the resources which the parent bus has already
+ * determined for us.
+ * TODO: interrupt routing
+ */
+#define MIPS_MEM_RID 0x20
+ rid = MIPS_MEM_RID;
+ mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (mem == NULL) {
+ device_printf(dev, "unable to allocate memory\n");
+ return (ENXIO);
+ }
+#if 0
+ device_printf(dev, "start %08lx size %04lx\n",
+ rman_get_start(mem), rman_get_size(mem));
+#endif
+
+ return (0);
+}
+
+static device_method_t siba_mips_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_attach, siba_mips_attach),
+ DEVMETHOD(device_probe, siba_mips_probe),
+
+ {0, 0},
+};
+
+static driver_t siba_mips_driver = {
+ "siba_mips",
+ siba_mips_methods,
+ sizeof(struct siba_softc),
+};
+static devclass_t siba_mips_devclass;
+
+DRIVER_MODULE(siba_mips, siba, siba_mips_driver, siba_mips_devclass, 0, 0);
Copied: projects/mips/sys/dev/siba/siba_sdram.c (from r187114, projects/mips/sys/mips/sentry5/siba_sdram.c)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/dev/siba/siba_sdram.c Sun Jan 18 23:49:02 2009 (r187415, copy of r187114, projects/mips/sys/mips/sentry5/siba_sdram.c)
@@ -0,0 +1,114 @@
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Child driver for SDRAM/DDR controller core.
+ * Generally the OS should not need to access this device unless the
+ * firmware has not configured the SDRAM controller.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <dev/siba/sibavar.h>
+#include <dev/siba/sibareg.h>
+#include <dev/siba/siba_ids.h>
+
+static int siba_sdram_attach(device_t);
+static int siba_sdram_probe(device_t);
+
+static int
+siba_sdram_probe(device_t dev)
+{
+
+ if (siba_get_vendor(dev) == SIBA_VID_BROADCOM &&
+ siba_get_device(dev) == SIBA_DEVID_SDRAMDDR) {
+ device_set_desc(dev, "SDRAM/DDR core");
+ return (BUS_PROBE_DEFAULT);
+ }
+
+ return (ENXIO);
+}
+
+struct siba_sdram_softc {
+ void *notused;
+};
+
+static int
+siba_sdram_attach(device_t dev)
+{
+ //struct siba_sdram_softc *sc = device_get_softc(dev);
+ struct resource *mem;
+ int rid;
+
+ /*
+ * Allocate the resources which the parent bus has already
+ * determined for us.
+ * TODO: interrupt routing
+ */
+#define MIPS_MEM_RID 0x20
+ rid = MIPS_MEM_RID;
+ mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (mem == NULL) {
+ device_printf(dev, "unable to allocate memory\n");
+ return (ENXIO);
+ }
+
+#if 0
+ device_printf(dev, "start %08lx size %04lx\n",
+ rman_get_start(mem), rman_get_size(mem));
+#endif
+
+ return (0);
+}
+
+static device_method_t siba_sdram_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_attach, siba_sdram_attach),
+ DEVMETHOD(device_probe, siba_sdram_probe),
+
+ {0, 0},
+};
+
+static driver_t siba_sdram_driver = {
+ "siba_sdram",
+ siba_sdram_methods,
+ sizeof(struct siba_softc),
+};
+static devclass_t siba_sdram_devclass;
+
+DRIVER_MODULE(siba_sdram, siba, siba_sdram_driver, siba_sdram_devclass, 0, 0);
Modified: projects/mips/sys/mips/conf/SENTRY5
==============================================================================
--- projects/mips/sys/mips/conf/SENTRY5 Sun Jan 18 23:34:17 2009 (r187414)
+++ projects/mips/sys/mips/conf/SENTRY5 Sun Jan 18 23:49:02 2009 (r187415)
@@ -73,8 +73,8 @@ options INVARIANT_SUPPORT
device siba # Sonics SiliconBackplane
device pci # siba_pcib
-device bfe # XXX will build both pci and siba
-device miibus # attachments
+# device bfe # XXX will build both pci and siba
+# device miibus # attachments
# pci devices
# notyet:
Modified: projects/mips/sys/mips/sentry5/files.sentry5
==============================================================================
--- projects/mips/sys/mips/sentry5/files.sentry5 Sun Jan 18 23:34:17 2009 (r187414)
+++ projects/mips/sys/mips/sentry5/files.sentry5 Sun Jan 18 23:49:02 2009 (r187415)
@@ -4,11 +4,4 @@
# for USB 1.1 OHCI, Ethernet and IPSEC cores
# which are believed to be devices we have drivers for
# which just need to be tweaked for attachment to an SSB system bus.
-
mips/sentry5/s5_machdep.c standard
-dev/siba/siba.c optional siba
-dev/siba/siba_pcib.c optional siba pci
-mips/sentry5/siba_cc.c optional siba
-
-# notyet
-#mips/sentry5/siba_mips.c optional siba
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