svn commit: r188024 - projects/cambria/sys/arm/xscale/ixp425

[Sam Leffler]

Author: sam
Date: Mon Feb  2 20:42:30 2009
New Revision: 188024
URL: http://svn.freebsd.org/changeset/base/188024

Log:
  map 16M of CS0 so we have access to the flash; need to do this
  dynamically but this works for now and the consensus is it's
  ok as a temporary solution

Modified:
  projects/cambria/sys/arm/xscale/ixp425/avila_machdep.c
  projects/cambria/sys/arm/xscale/ixp425/ixp425reg.h

Modified: projects/cambria/sys/arm/xscale/ixp425/avila_machdep.c
==============================================================================
--- projects/cambria/sys/arm/xscale/ixp425/avila_machdep.c	Mon Feb  2 20:36:20 2009	(r188023)
+++ projects/cambria/sys/arm/xscale/ixp425/avila_machdep.c	Mon Feb  2 20:42:30 2009	(r188024)
@@ -154,6 +154,10 @@ static const struct pmap_devmap ixp425_d
     { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
       VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
 
+	/* CFI Flash on the Expansion Bus */
+    { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
+      IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
 	/* IXP425 PCI Configuration */
     { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
       VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },

Modified: projects/cambria/sys/arm/xscale/ixp425/ixp425reg.h
==============================================================================
--- projects/cambria/sys/arm/xscale/ixp425/ixp425reg.h	Mon Feb  2 20:36:20 2009	(r188023)
+++ projects/cambria/sys/arm/xscale/ixp425/ixp425reg.h	Mon Feb  2 20:42:30 2009	(r188024)
@@ -76,6 +76,10 @@
  *           Global cache clean area
  * FF00 0000 ---------------------------
  *
+ * FE00 0000 ---------------------------
+ *           16M CFI Flash (on ext bus)
+ * FD00 0000 ---------------------------
+ *
  * FC00 0000 ---------------------------
  *           PCI Data (memory space)
  * F800 0000 --------------------------- IXP425_PCI_MEM_VBASE
@@ -348,6 +352,10 @@
 #define IXP425_EXP_SETUP_T(x)		(((x) & 3)  << IXP425_EXP_SETUP_SHIFT)
 #define IXP425_EXP_ADDR_T(x)		(((x) & 3)  << IXP425_EXP_ADDR_SHIFT)
 
+/* EXP_TIMING_* bits */
+#define	EXP_TIMING_MASK		0x3fff0000
+#define	EXP_TIMING_RSVD		0x40000184	/* bits to preserve at boot */
+
 /* EXP_CSn bits */
 #define EXP_BYTE_EN		0x00000001	/* bus uses only 8-bit data */
 #define EXP_WR_EN		0x00000002	/* ena writes to CS region */
@@ -649,6 +657,9 @@
 #define	IXP425_EXP_BUS_CSx_VBASE(i) \
 	(IXP425_MAC_B_VBASE + (i)*IXP425_MAC_B_SIZE)
 
+#define	IXP425_EXP_BUS_CS0_HWBASE	IXP425_EXP_BUS_CSx_HWBASE(0)
+#define IXP425_EXP_BUS_CS0_VBASE	0xFD000000UL
+#define IXP425_EXP_BUS_CS0_SIZE		0x01000000	/* NB: 16M */
 #define	IXP425_EXP_BUS_CS1_HWBASE	IXP425_EXP_BUS_CSx_HWBASE(1)
 #define IXP425_EXP_BUS_CS1_VBASE	IXP425_EXP_BUS_CSx_VBASE(1)
 #define IXP425_EXP_BUS_CS1_SIZE		0x1000
@@ -663,7 +674,6 @@
 #define IXP425_EXP_BUS_CS4_SIZE		0x1000
 
 /* NB: not mapped (yet) */
-#define	IXP425_EXP_BUS_CS0_HWBASE	IXP425_EXP_BUS_CSx_HWBASE(0)
 #define	IXP425_EXP_BUS_CS5_HWBASE	IXP425_EXP_BUS_CSx_HWBASE(5)
 #define	IXP425_EXP_BUS_CS6_HWBASE	IXP425_EXP_BUS_CSx_HWBASE(6)
 #define	IXP425_EXP_BUS_CS7_HWBASE	IXP425_EXP_BUS_CSx_HWBASE(7)