svn commit: r361903 - head/sys/riscv/riscv

[Alex Richardson]

Author: arichardson
Date: Mon Jun  8 08:51:52 2020
New Revision: 361903
URL: https://svnweb.freebsd.org/changeset/base/361903

Log:
  RISC-V: handle DTB aligned to less than 2MB
  
  By default OpenSBI and BBL will pass the DTB at a 2MB-aligned address.
  However, by default there are no 2MB aligned regions between the SBI and
  the kernel, so we have to choose a 2MB aligned region after the kernel.
  OpenSBI defaults to placing the DTB 32MB after the start of the kernel but
  this is not sufficient for a kernel with a large MFS embedded.
  We could increase this offset to a larger number (e.g. 64/128/256) but that
  imposes restrictions on the minimum RAM size.
  Another solution would be to place the DTB between OpenSBI and the kernel
  at 1MB alignment, but current locore.S code assumes 2MB alignment.
  
  With this change I can now boot on QEMU with an OpenSBI configured to
  store the DTB at an offset of 1MB.
  
  See also https://github.com/riscv/opensbi/issues/169
  
  Reviewed By:	mhorne
  Differential Revision: https://reviews.freebsd.org/D25151

Modified:
  head/sys/riscv/riscv/locore.S

Modified: head/sys/riscv/riscv/locore.S
==============================================================================
--- head/sys/riscv/riscv/locore.S	Mon Jun  8 02:42:41 2020	(r361902)
+++ head/sys/riscv/riscv/locore.S	Mon Jun  8 08:51:52 2020	(r361903)
@@ -139,6 +139,8 @@ _start:
 	lla	s1, pagetable_l2_devmap
 	mv	s2, a1
 	srli	s2, s2, PAGE_SHIFT
+	/* Mask off any bits that aren't aligned */
+	andi	s2, s2, ~((1 << (PTE_PPN1_S - PTE_PPN0_S)) - 1)
 
 	li	t0, (PTE_KERN)
 	slli	t2, s2, PTE_PPN0_S	/* << PTE_PPN0_S */
@@ -214,6 +216,10 @@ va:
 	sd	t0, RISCV_BOOTPARAMS_KERN_STACK(sp)
 
 	li	t0, (VM_EARLY_DTB_ADDRESS)
+	/* Add offset of DTB within superpage */
+	li	t1, (L2_OFFSET)
+	and	t1, a1, t1
+	add	t0, t0, t1
 	sd	t0, RISCV_BOOTPARAMS_DTBP_VIRT(sp)
 
 	mv	a0, sp