svn commit: r362977 - head/sys/riscv/riscv

[Kristof Provost]

Author: kp
Date: Mon Jul  6 21:29:50 2020
New Revision: 362977
URL: https://svnweb.freebsd.org/changeset/base/362977

Log:
  riscv plic: Do not complete interrupts until the interrupt handler has run
  
  We cannot complete the interrupt (i.e. write to the claims/complete register
  until the interrupt handler has actually run. We don't run the interrupt
  handler immediately from intr_isrc_dispatch(), we only schedule it for later
  execution.
  
  If we immediately complete it (i.e. before the interrupt handler proper has
  run) the interrupt may be triggered again if the interrupt source remains set.
  From RISC-V Instruction Set Manual: Volume II: Priviliged Architecture, 7.4
  Interrupt Gateways:
  
  "If a level-sensitive interrupt source deasserts the interrupt after the PLIC
  core accepts the request and before the interrupt is serviced, the interrupt
  request remains present in the IP bit of the PLIC core and will be serviced by
  a handler, which will then have to determine that the interrupt device no
  longer requires service."
  
  In other words, we may receive interrupts twice.
  
  Avoid that by postponing the completion until after the interrupt handler has
  run.
  
  If the interrupt is handled by a filter rather than by scheduling an interrupt
  thread we must also complete the interrupt, so set up a post_filter handler
  (which is the same as the post_ithread handler).
  
  Reviewed by:	mhorne
  Sponsored by:	Axiado
  Differential Revision:	https://reviews.freebsd.org/D25531

Modified:
  head/sys/riscv/riscv/plic.c

Modified: head/sys/riscv/riscv/plic.c
==============================================================================
--- head/sys/riscv/riscv/plic.c	Mon Jul  6 21:20:57 2020	(r362976)
+++ head/sys/riscv/riscv/plic.c	Mon Jul  6 21:29:50 2020	(r362977)
@@ -169,11 +169,11 @@ plic_intr(void *arg)
 	sc = arg;
 	cpu = PCPU_GET(cpuid);
 
+	/* Claim any pending interrupt. */
 	pending = RD4(sc, PLIC_CLAIM(sc, cpu));
 	if (pending) {
 		tf = curthread->td_intr_frame;
 		plic_irq_dispatch(sc, pending, tf);
-		WR4(sc, PLIC_CLAIM(sc, cpu), pending);
 	}
 
 	return (FILTER_HANDLED);
@@ -384,7 +384,17 @@ plic_pre_ithread(device_t dev, struct intr_irqsrc *isr
 static void
 plic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
 {
+	struct plic_softc *sc;
+	struct plic_irqsrc *src;
+	uint32_t cpu;
 
+	sc = device_get_softc(dev);
+	src = (struct plic_irqsrc *)isrc;
+
+	cpu = CPU_FFS(&isrc->isrc_cpu) - 1;
+
+	/* Complete the interrupt. */
+	WR4(sc, PLIC_CLAIM(sc, cpu), src->irq);
 	plic_enable_intr(dev, isrc);
 }
 
@@ -451,6 +461,7 @@ static device_method_t plic_methods[] = {
 	DEVMETHOD(pic_map_intr,		plic_map_intr),
 	DEVMETHOD(pic_pre_ithread,	plic_pre_ithread),
 	DEVMETHOD(pic_post_ithread,	plic_post_ithread),
+	DEVMETHOD(pic_post_filter,	plic_post_ithread),
 	DEVMETHOD(pic_setup_intr,	plic_setup_intr),
 	DEVMETHOD(pic_bind_intr,	plic_bind_intr),