svn commit: r356316 - head/sys/arm64/include

[Andrew Turner]

Author: andrew
Date: Fri Jan  3 10:03:36 2020
New Revision: 356316
URL: https://svnweb.freebsd.org/changeset/base/356316

Log:
  Add the 8 and 16 bit atomic load/store functions with a barrier on arm64.
  
  Reviewed by:	cem
  MFC after:	2 weeks
  Sponsored by:	DARPA, AFRL
  Differential Revision:	https://reviews.freebsd.org/D22966

Modified:
  head/sys/arm64/include/atomic.h

Modified: head/sys/arm64/include/atomic.h
==============================================================================
--- head/sys/arm64/include/atomic.h	Fri Jan  3 04:37:47 2020	(r356315)
+++ head/sys/arm64/include/atomic.h	Fri Jan  3 10:03:36 2020	(r356316)
@@ -448,6 +448,34 @@ atomic_swap_64(volatile uint64_t *p, uint64_t val)
 	return (ret);
 }
 
+static __inline uint8_t
+atomic_load_acq_8(volatile uint8_t *p)
+{
+	uint8_t ret;
+
+	__asm __volatile(
+	    "ldarb	%w0, [%1] \n"
+	    : "=&r" (ret)
+	    : "r" (p)
+	    : "memory");
+
+	return (ret);
+}
+
+static __inline uint16_t
+atomic_load_acq_16(volatile uint16_t *p)
+{
+	uint16_t ret;
+
+	__asm __volatile(
+	    "ldarh	%w0, [%1] \n"
+	    : "=&r" (ret)
+	    : "r" (p)
+	    : "memory");
+
+	return (ret);
+}
+
 static __inline uint32_t
 atomic_load_acq_32(volatile uint32_t *p)
 {
@@ -474,6 +502,28 @@ atomic_load_acq_64(volatile uint64_t *p)
 	    : "memory");
 
 	return (ret);
+}
+
+static __inline void
+atomic_store_rel_8(volatile uint8_t *p, uint8_t val)
+{
+
+	__asm __volatile(
+	    "stlrb	%w0, [%1] \n"
+	    :
+	    : "r" (val), "r" (p)
+	    : "memory");
+}
+
+static __inline void
+atomic_store_rel_16(volatile uint16_t *p, uint16_t val)
+{
+
+	__asm __volatile(
+	    "stlrh	%w0, [%1] \n"
+	    :
+	    : "r" (val), "r" (p)
+	    : "memory");
 }
 
 static __inline void