svn commit: r352904 - head/sys/arm64/rockchip/clk

Emmanuel Vadot manu at FreeBSD.org
Mon Sep 30 15:01:10 UTC 2019


Author: manu
Date: Mon Sep 30 15:01:09 2019
New Revision: 352904
URL: https://svnweb.freebsd.org/changeset/base/352904

Log:
  arm64: rockchip: rk_clk_pll: Check mode on recalc
  
  If the pll is in slow or deep slow mode return the correct frequency.

Modified:
  head/sys/arm64/rockchip/clk/rk_clk_pll.c

Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.c
==============================================================================
--- head/sys/arm64/rockchip/clk/rk_clk_pll.c	Mon Sep 30 15:00:22 2019	(r352903)
+++ head/sys/arm64/rockchip/clk/rk_clk_pll.c	Mon Sep 30 15:01:09 2019	(r352904)
@@ -367,7 +367,7 @@ rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *f
 	uint32_t postdiv1, postdiv2, fracdiv;
 	uint32_t con1, con2, con3, con4;
 	uint64_t foutvco;
-
+	uint32_t mode;
 	sc = clknode_get_softc(clk);
 
 	DEVICE_LOCK(clk);
@@ -376,6 +376,21 @@ rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *f
 	READ4(clk, sc->base_offset + 8, &con3);
 	READ4(clk, sc->base_offset + 0xC, &con4);
 	DEVICE_UNLOCK(clk);
+
+	/*
+	 * if we are in slow mode the output freq
+	 * is the parent one, the 24Mhz external oscillator
+	 * if we are in deep mode the output freq is 32.768khz
+	 */
+	mode = (con4 & RK3399_CLK_PLL_MODE_MASK) >> RK3399_CLK_PLL_MODE_SHIFT;
+	if (mode == RK3399_CLK_PLL_MODE_SLOW) {
+		dprintf("pll in slow mode, con4=%x\n", con4);
+		return (0);
+	} else if (mode == RK3399_CLK_PLL_MODE_DEEPSLOW) {
+		dprintf("pll in deep slow, con4=%x\n", con4);
+		*freq = 32768;
+		return (0);
+	}
 
 	dprintf("con0: %x\n", con1);
 	dprintf("con1: %x\n", con2);


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