svn commit: r351918 - head/sys/kern

[Ruslan Bukin]

On Fri, Sep 06, 2019 at 12:15:07PM +0800, Philip Paeps wrote:
> On 2019-09-06 11:15:12 (+0800), Ian Lepore wrote:
> > On Fri, 2019-09-06 at 01:19 +0000, Philip Paeps wrote:
> >> Author: philip
> >> Date: Fri Sep  6 01:19:31 2019
> >> New Revision: 351918
> >> URL: https://svnweb.freebsd.org/changeset/base/351918
> >>
> >> Log:
> >>   riscv: default to HZ=100
> >>
> >>   Most current RISC-V development platforms are not fast enough to
> >> benefit
> >>   from the increased granularity provided by HZ=1000.
> >>
> >>   Sponsored by:	Axiado
> >>
> >> Modified:
> >>   head/sys/kern/subr_param.c
> >>
> >> Modified: head/sys/kern/subr_param.c
> >> =====================================================================
> >> =========
> >> --- head/sys/kern/subr_param.c	Fri Sep  6 00:06:55 2019	(r351
> >> 917)
> >> +++ head/sys/kern/subr_param.c	Fri Sep  6 01:19:31 2019	(r351
> >> 918)
> >> @@ -61,7 +61,7 @@ __FBSDID("$FreeBSD$");
> >>   */
> >>
> >>  #ifndef HZ
> >> -#  if defined(__mips__) || defined(__arm__)
> >> +#  if defined(__mips__) || defined(__arm__) || defined(__riscv)
> >>  #    define	HZ 100
> >>  #  else
> >>  #    define	HZ 1000
> >>
> >
> > This seems like a bad idea.  I've run a 90mhz armv4 chip with HZ=1000 
> > and didn't notice any performance hit from doing so.  Almost all arm 
> > kernel config files set HZ as an option, so that define doesn't do 
> > much for arm these days.  It probably does still set HZ for various 
> > mips platforms.
> >
> > I would think 1000 is appropriate for anything modern running at 
> > 200mhz or more.
> >
> > Setting it to 100 has the bad side effect of making things like 
> > msleep(), tsleep(), and pause() (which show up in plenty of drivers) 
> > all have a minimum timeout of 10ms, which is a long long time on 
> > modern hardware.
> >
> > What benefit do you think you'll get from the lower number?
> 
> On systems running at 10s of MHz (or slower, ick), with HZ=1000 you 
> spend an awful lot of time servicing the timer interrupt and not very 
> much time doing anything else.
> 
> My rationale was that most RISC-V systems (including emulation and FPGA 
> prototypes) I've encountered are running slower than the tipping point 
> where HZ=1000 makes sense.  With the default of HZ=100, faster 
> exceptions can still set HZ=1000 in their individual configs.
> 
> When the RISC-V world evolves to having more actual silicon and fewer 
> slow prototypes, I definitely agree this default should be flipped again 
> for HZ=1000 by default and HZ=100 in the config files for the 
> exceptions.
> 

Hi Philip

I only worry about HiFive Unleashed board, which is the only real hardware available at the moment for community and it does not require this change (it is 1.5 GHz clock).

With an amount of real silicons growing we may want to keep HZ set to 1000 in GENERIC soon-ish so users download/build the GENERIC image and have immediate fun.

For FPGA I usually tune (increase) timer clock frequency locally in the DTS file based on the timing of a synthesized core.

Ruslan