svn commit: r354072 - head/sys/arm64/include

[Andrew Turner]

Author: andrew
Date: Fri Oct 25 14:46:09 2019
New Revision: 354072
URL: https://svnweb.freebsd.org/changeset/base/354072

Log:
  Remove the arm4 ID register masks, they are not needed after r353641.
  
  Sponsored by:	DARPA, AFRL

Modified:
  head/sys/arm64/include/armreg.h

Modified: head/sys/arm64/include/armreg.h
==============================================================================
--- head/sys/arm64/include/armreg.h	Fri Oct 25 14:33:07 2019	(r354071)
+++ head/sys/arm64/include/armreg.h	Fri Oct 25 14:46:09 2019	(r354072)
@@ -176,7 +176,6 @@
 #define	ICC_SRE_EL2_EN		(1U << 3)
 
 /* ID_AA64DFR0_EL1 */
-#define	ID_AA64DFR0_MASK		UL(0x0000000ff0f0ffff)
 #define	ID_AA64DFR0_DebugVer_SHIFT	0
 #define	ID_AA64DFR0_DebugVer_MASK	(UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
 #define	ID_AA64DFR0_DebugVer(x)		((x) & ID_AA64DFR0_DebugVer_MASK)
@@ -214,7 +213,6 @@
 #define	 ID_AA64DFR0_PMSVer_V1		(UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
 
 /* ID_AA64ISAR0_EL1 */
-#define	ID_AA64ISAR0_MASK		UL(0x0000fffff0fffff0)
 #define	ID_AA64ISAR0_AES_SHIFT		4
 #define	ID_AA64ISAR0_AES_MASK		(UL(0xf) << ID_AA64ISAR0_AES_SHIFT)
 #define	ID_AA64ISAR0_AES(x)		((x) & ID_AA64ISAR0_AES_MASK)
@@ -269,7 +267,6 @@
 #define	 ID_AA64ISAR0_DP_IMPL		(UL(0x1) << ID_AA64ISAR0_DP_SHIFT)
 
 /* ID_AA64ISAR1_EL1 */
-#define	ID_AA64ISAR1_MASK		UL(0x00000000ffffffff)
 #define	ID_AA64ISAR1_DPB_SHIFT		0
 #define	ID_AA64ISAR1_DPB_MASK		(UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
 #define	ID_AA64ISAR1_DPB(x)		((x) & ID_AA64ISAR1_DPB_MASK)
@@ -312,7 +309,6 @@
 #define	 ID_AA64ISAR1_GPI_IMPL		(UL(0x1) << ID_AA64ISAR1_GPI_SHIFT)
 
 /* ID_AA64MMFR0_EL1 */
-#define	ID_AA64MMFR0_MASK		UL(0x00000000ffffffff)
 #define	ID_AA64MMFR0_PARange_SHIFT	0
 #define	ID_AA64MMFR0_PARange_MASK	(UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
 #define	ID_AA64MMFR0_PARange(x)		((x) & ID_AA64MMFR0_PARange_MASK)
@@ -360,7 +356,6 @@
 #define	 ID_AA64MMFR0_TGran4_NONE	(UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
 
 /* ID_AA64MMFR1_EL1 */
-#define	ID_AA64MMFR1_MASK		UL(0x00000000ffffffff)
 #define	ID_AA64MMFR1_HAFDBS_SHIFT	0
 #define	ID_AA64MMFR1_HAFDBS_MASK	(UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
 #define	ID_AA64MMFR1_HAFDBS(x)		((x) & ID_AA64MMFR1_HAFDBS_MASK)
@@ -407,7 +402,6 @@
 
 /* ID_AA64MMFR2_EL1 */
 #define	ID_AA64MMFR2_EL1		S3_0_C0_C7_2
-#define	ID_AA64MMFR2_MASK		UL(0x000000000fffffff)
 #define	ID_AA64MMFR2_CnP_SHIFT		0
 #define	ID_AA64MMFR2_CnP_MASK		(UL(0xf) << ID_AA64MMFR2_CnP_SHIFT)
 #define	ID_AA64MMFR2_CnP(x)		((x) & ID_AA64MMFR2_CnP_MASK)
@@ -445,7 +439,6 @@
 #define	 ID_AA64MMFR2_NV_IMPL		(UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
 
 /* ID_AA64PFR0_EL1 */
-#define	ID_AA64PFR0_MASK		UL(0x0000000fffffffff)
 #define	ID_AA64PFR0_EL0_SHIFT		0
 #define	ID_AA64PFR0_EL0_MASK		(UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
 #define	ID_AA64PFR0_EL0(x)		((x) & ID_AA64PFR0_EL0_MASK)