svn commit: r348147 - head/sys/powerpc/mpc85xx

[Justin Hibbits]

Author: jhibbits
Date: Thu May 23 03:47:25 2019
New Revision: 348147
URL: https://svnweb.freebsd.org/changeset/base/348147

Log:
  powerpc/mpc85xx: Use the proper (EREF) form of writing to DBCR0
  
  DBCR0, according to the Freescale EREF, is guaranteed to be updated, and
  changes take effect, after an isync plus change of MSR[DE] from 0 to 1.
  Otherwise it's guaranteed to be updated "eventually".  Use the expected
  synchronization sequence to write it for resetting.
  
  This prevents "Reset failed" from being printed immediately before the CPU
  resets.
  
  MFC after:	2 weeks

Modified:
  head/sys/powerpc/mpc85xx/platform_mpc85xx.c

Modified: head/sys/powerpc/mpc85xx/platform_mpc85xx.c
==============================================================================
--- head/sys/powerpc/mpc85xx/platform_mpc85xx.c	Thu May 23 03:40:48 2019	(r348146)
+++ head/sys/powerpc/mpc85xx/platform_mpc85xx.c	Thu May 23 03:47:25 2019	(r348147)
@@ -517,15 +517,14 @@ mpc85xx_reset(platform_t plat)
 	 */
 	ccsr_write4(OCP85XX_RSTCR, 2);
 
-	/* Clear DBCR0, disables debug interrupts and events. */
-	mtspr(SPR_DBCR0, 0);
+	mtmsr(mfmsr() & ~PSL_DE);
+
+	/* Enable debug interrupts and issue reset. */
+	mtspr(SPR_DBCR0, DBCR0_IDM | DBCR0_RST_SYSTEM);
 	__asm __volatile("isync");
 
 	/* Enable Debug Interrupts in MSR. */
 	mtmsr(mfmsr() | PSL_DE);
-
-	/* Enable debug interrupts and issue reset. */
-	mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
 
 	printf("Reset failed...\n");
 	while (1)