svn commit: r342759 - in head/sys/dev/rtwn: rtl8188e rtl8188e/pci rtl8192c

[Andriy Voskoboinyk]

Author: avos
Date: Fri Jan  4 04:26:39 2019
New Revision: 342759
URL: https://svnweb.freebsd.org/changeset/base/342759

Log:
  rtwn_pci(4): sync r88ee_power_on() with OpenBSD
  
  Tested with RTL8188EE, STA mode
  
  Submitted by:	Farhan Khan <khanzf at gmail.com>
  MFC after:	3 days
  Differential Revision:	https://reviews.freebsd.org/D18727

Modified:
  head/sys/dev/rtwn/rtl8188e/pci/r88ee_init.c
  head/sys/dev/rtwn/rtl8188e/r88e_reg.h
  head/sys/dev/rtwn/rtl8192c/r92c_reg.h

Modified: head/sys/dev/rtwn/rtl8188e/pci/r88ee_init.c
==============================================================================
--- head/sys/dev/rtwn/rtl8188e/pci/r88ee_init.c	Fri Jan  4 04:15:17 2019	(r342758)
+++ head/sys/dev/rtwn/rtl8188e/pci/r88ee_init.c	Fri Jan  4 04:26:39 2019	(r342759)
@@ -84,8 +84,15 @@ r88ee_power_on(struct rtwn_softc *sc)
 {
 	int ntries;
 
-	/* Wait for power ready bit. */
-	for (ntries = 0; ntries < 5000; ntries++) {
+	/* Disable XTAL output for power saving. */
+	rtwn_setbits_1(sc, R88E_XCK_OUT_CTRL, R88E_XCK_OUT_CTRL_EN, 0);
+
+	/* Unlock ISO/CLK/Power control register. */
+	rtwn_setbits_2(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_APDM_HPDN, 0);
+	rtwn_write_1(sc, R92C_RSV_CTRL, 0);
+
+	/* Wait for power ready bit */
+	for(ntries = 0; ntries < 5000; ntries++) {
 		if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
 			break;
 		rtwn_delay(sc, 10);
@@ -96,9 +103,6 @@ r88ee_power_on(struct rtwn_softc *sc)
 		return (ETIMEDOUT);
 	}
 
-	/* Unlock ISO/CLK/Power control register. */
-	rtwn_write_1(sc, R92C_RSV_CTRL, 0);
-
 	/* Reset BB. */
 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
 	    R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
@@ -114,6 +118,7 @@ r88ee_power_on(struct rtwn_softc *sc)
 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
 	    R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1);
 
+	/* Auto-enable WLAN */
 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
 	    0, R92C_APS_FSMCO_APFM_ONMAC, 1);
 	for (ntries = 0; ntries < 5000; ntries++) {
@@ -129,6 +134,12 @@ r88ee_power_on(struct rtwn_softc *sc)
 
 	/* Enable LDO normal mode. */
 	rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 0);
+
+	rtwn_setbits_1(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_PDN_EN);
+	rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
+	rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL_EXT + 1, 0, 0x02);
+	rtwn_setbits_1(sc, R92C_SYS_CLKR, 0, 0x08);
+	rtwn_setbits_2(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_ENSIC, 0);
 
 	/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
 	rtwn_write_2(sc, R92C_CR, 0);

Modified: head/sys/dev/rtwn/rtl8188e/r88e_reg.h
==============================================================================
--- head/sys/dev/rtwn/rtl8188e/r88e_reg.h	Fri Jan  4 04:15:17 2019	(r342758)
+++ head/sys/dev/rtwn/rtl8188e/r88e_reg.h	Fri Jan  4 04:26:39 2019	(r342759)
@@ -32,6 +32,7 @@
 #define R88E_HISR			0x0b4
 #define R88E_HIMRE			0x0b8
 #define R88E_HISRE			0x0bc
+#define R88E_XCK_OUT_CTRL	0x07c
 /* MAC General Configuration. */
 #define R88E_32K_CTRL			0x194
 #define R88E_HMEBOX_EXT(idx)		(0x1f0 + (idx) * 4)
@@ -121,5 +122,8 @@
 #define R88E_RF_T_METER_VAL_M	0x0fc00
 #define R88E_RF_T_METER_VAL_S	10
 #define R88E_RF_T_METER_START	0x30000
+
+/* Bits for R88E_XCK_OUT_CTRL. */
+#define R88E_XCK_OUT_CTRL_EN	1
 
 #endif	/* R88E_REG_H */

Modified: head/sys/dev/rtwn/rtl8192c/r92c_reg.h
==============================================================================
--- head/sys/dev/rtwn/rtl8192c/r92c_reg.h	Fri Jan  4 04:15:17 2019	(r342758)
+++ head/sys/dev/rtwn/rtl8192c/r92c_reg.h	Fri Jan  4 04:26:39 2019	(r342759)
@@ -66,6 +66,7 @@
 #define R92C_HSIMR			0x058
 #define R92C_HSISR			0x05c
 #define R92C_MULTI_FUNC_CTRL		0x068
+#define R92C_AFE_XTAL_CTRL_EXT	0x078
 #define R92C_LDO_SWR_CTRL		0x07c
 #define R92C_MCUFWDL			0x080
 #define R92C_HMEBOX_EXT(idx)		(0x088 + (idx) * 2)
@@ -347,6 +348,7 @@
 
 /* Bits for R92C_GPIO_MUXCFG. */
 #define R92C_GPIO_MUXCFG_ENBT	0x0020
+#define R92C_GPIO_MUXCFG_ENSIC	0x1000
 
 /* Bits for R92C_LEDCFG0. */
 #define R92C_LEDCFG0_DIS	0x08