svn commit: r355659 - in head/sys/arm64: arm64 include

[Andrew Turner]

Author: andrew
Date: Thu Dec 12 18:27:54 2019
New Revision: 355659
URL: https://svnweb.freebsd.org/changeset/base/355659

Log:
  Add comments and macros to the tcr_el1 setting code to help understand it.
  
  This code is non-obvious when reading for the first time. To help with
  understanding of it add comments explaining what it's doing.
  
  While here use macros from armreg.h rather than magic numbers.
  
  Sponsored by:	DARPA, AFRL

Modified:
  head/sys/arm64/arm64/locore.S
  head/sys/arm64/include/armreg.h

Modified: head/sys/arm64/arm64/locore.S
==============================================================================
--- head/sys/arm64/arm64/locore.S	Thu Dec 12 18:16:32 2019	(r355658)
+++ head/sys/arm64/arm64/locore.S	Thu Dec 12 18:27:54 2019	(r355659)
@@ -688,14 +688,23 @@ start_mmu:
 	 */
 	ldr	x2, tcr
 	mrs	x3, id_aa64mmfr0_el1
-	bfi	x2, x3, #32, #3
-	and	x3, x3, #0xF0
-	cmp	x3, #0x20
+
+	/* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */
+	bfi	x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH)
+	and	x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK)
+
+	/* Check if the HW supports 16 bit ASIDS */
+	cmp	x3, #(ID_AA64MMFR0_ASIDBits_16)
+	/* If so x3 == 1, else x3 == 0 */
 	cset	x3, eq
-	bfi	x2, x3, #36, #1
+	/* Set TCR.AS with x3 */
+	bfi	x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH)
+
 	msr	tcr_el1, x2
 
-	/* Setup SCTLR */
+	/*
+	 * Setup SCTLR.
+	 */
 	ldr	x2, sctlr_set
 	ldr	x3, sctlr_clear
 	mrs	x1, sctlr_el1

Modified: head/sys/arm64/include/armreg.h
==============================================================================
--- head/sys/arm64/include/armreg.h	Thu Dec 12 18:16:32 2019	(r355658)
+++ head/sys/arm64/include/armreg.h	Thu Dec 12 18:27:54 2019	(r355659)
@@ -619,9 +619,12 @@
 #define	PSR_FLAGS	0xf0000000
 
 /* TCR_EL1 - Translation Control Register */
-#define	TCR_ASID_16	(0x1UL << 36)
+#define	TCR_ASID_SHIFT	36
+#define	TCR_ASID_WIDTH	1
+#define	TCR_ASID_16	(0x1UL << TCR_ASID_SHIFT)
 
 #define	TCR_IPS_SHIFT	32
+#define	TCR_IPS_WIDTH	3
 #define	TCR_IPS_32BIT	(0 << TCR_IPS_SHIFT)
 #define	TCR_IPS_36BIT	(1 << TCR_IPS_SHIFT)
 #define	TCR_IPS_40BIT	(2 << TCR_IPS_SHIFT)