svn commit: r351187 - head/sys/arm64/rockchip
Michal Meloun
mmel at FreeBSD.org
Sun Aug 18 09:19:33 UTC 2019
Author: mmel
Date: Sun Aug 18 09:19:33 2019
New Revision: 351187
URL: https://svnweb.freebsd.org/changeset/base/351187
Log:
Improve rk_pinctrl driver:
- add support for 'output-low', 'output-high', 'output-low' and
'output-enable' properties. These are use in RK3288 DT files
- add support for RK3288
- to reduce overall file size, use local macros for initialization
of pinctrl description structures.
MFC after: 2 weeks
Modified:
head/sys/arm64/rockchip/rk_pinctrl.c
Modified: head/sys/arm64/rockchip/rk_pinctrl.c
==============================================================================
--- head/sys/arm64/rockchip/rk_pinctrl.c Sun Aug 18 09:11:43 2019 (r351186)
+++ head/sys/arm64/rockchip/rk_pinctrl.c Sun Aug 18 09:19:33 2019 (r351187)
@@ -34,11 +34,12 @@ __FBSDID("$FreeBSD$");
#include <sys/systm.h>
#include <sys/bus.h>
+#include <sys/gpio.h>
#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/rman.h>
#include <sys/lock.h>
+#include <sys/module.h>
#include <sys/mutex.h>
+#include <sys/rman.h>
#include <machine/bus.h>
#include <machine/resource.h>
@@ -53,10 +54,9 @@ __FBSDID("$FreeBSD$");
#include <dev/extres/syscon/syscon.h>
+#include "gpio_if.h"
#include "syscon_if.h"
-#include "opt_soc.h"
-
struct rk_pinctrl_pin_drive {
uint32_t bank;
uint32_t subbank;
@@ -66,8 +66,8 @@ struct rk_pinctrl_pin_drive {
};
struct rk_pinctrl_bank {
- uint32_t bank_num;
- uint32_t subbank_num;
+ uint32_t bank;
+ uint32_t subbank;
uint32_t offset;
uint32_t nbits;
};
@@ -81,6 +81,13 @@ struct rk_pinctrl_pin_fixup {
uint32_t mask;
};
+struct rk_pinctrl_gpio {
+ uint32_t bank;
+ char *gpio_name;
+ device_t gpio_dev;
+};
+
+
struct rk_pinctrl_softc;
struct rk_pinctrl_conf {
@@ -90,8 +97,10 @@ struct rk_pinctrl_conf {
uint32_t npin_fixup;
struct rk_pinctrl_pin_drive *pin_drive;
uint32_t npin_drive;
- uint32_t (*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t);
- struct syscon *(*get_syscon)(struct rk_pinctrl_softc *, uint32_t);
+ struct rk_pinctrl_gpio *gpio_bank;
+ uint32_t ngpio_bank;
+ uint32_t (*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t);
+ struct syscon *(*get_syscon)(struct rk_pinctrl_softc *, uint32_t);
};
struct rk_pinctrl_softc {
@@ -102,218 +111,392 @@ struct rk_pinctrl_softc {
struct rk_pinctrl_conf *conf;
};
+#define RK_IOMUX(_bank, _subbank, _offset, _nbits) \
+{ \
+ .bank = _bank, \
+ .subbank = _subbank, \
+ .offset = _offset, \
+ .nbits = _nbits, \
+}
+
+#define RK_PINFIX(_bank, _pin, _reg, _bit, _mask) \
+{ \
+ .bank = _bank, \
+ .pin = _pin, \
+ .reg = _reg, \
+ .bit = _bit, \
+ .mask = _mask, \
+}
+
+#define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma) \
+{ \
+ .bank = _bank, \
+ .subbank = _subbank, \
+ .offset = _offset, \
+ .value = _value, \
+ .ma = _ma, \
+}
+#define RK_GPIO(_bank, _name) \
+{ \
+ .bank = _bank, \
+ .gpio_name = _name, \
+}
+
+static struct rk_pinctrl_gpio rk3288_gpio_bank[] = {
+ RK_GPIO(0, "gpio0"),
+ RK_GPIO(1, "gpio1"),
+ RK_GPIO(2, "gpio2"),
+ RK_GPIO(3, "gpio3"),
+ RK_GPIO(4, "gpio4"),
+ RK_GPIO(5, "gpio5"),
+ RK_GPIO(6, "gpio6"),
+ RK_GPIO(7, "gpio7"),
+ RK_GPIO(8, "gpio8"),
+};
+
+static struct rk_pinctrl_bank rk3288_iomux_bank[] = {
+ /* bank sub offs nbits */
+ /* PMU */
+ RK_IOMUX(0, 0, 0x0084, 2),
+ RK_IOMUX(0, 1, 0x0088, 2),
+ RK_IOMUX(0, 2, 0x008C, 2),
+ /* GFR */
+ RK_IOMUX(1, 3, 0x000C, 2),
+ RK_IOMUX(2, 0, 0x0010, 2),
+ RK_IOMUX(2, 1, 0x0014, 2),
+ RK_IOMUX(2, 2, 0x0018, 2),
+ RK_IOMUX(2, 3, 0x001C, 2),
+ RK_IOMUX(3, 0, 0x0020, 2),
+ RK_IOMUX(3, 1, 0x0024, 2),
+ RK_IOMUX(3, 2, 0x0028, 2),
+ RK_IOMUX(3, 3, 0x002C, 4),
+ RK_IOMUX(4, 0, 0x0034, 4),
+ RK_IOMUX(4, 1, 0x003C, 4),
+ RK_IOMUX(4, 2, 0x0044, 2),
+ RK_IOMUX(4, 3, 0x0048, 2),
+ /* 5,0 - Empty */
+ RK_IOMUX(5, 1, 0x0050, 2),
+ RK_IOMUX(5, 2, 0x0054, 2),
+ /* 5,3 - Empty */
+ RK_IOMUX(6, 0, 0x005C, 2),
+ RK_IOMUX(6, 1, 0x0060, 2),
+ RK_IOMUX(6, 2, 0x0064, 2),
+ /* 6,3 - Empty */
+ RK_IOMUX(7, 0, 0x006C, 2),
+ RK_IOMUX(7, 1, 0x0070, 2),
+ RK_IOMUX(7, 2, 0x0074, 4),
+ /* 7,3 - Empty */
+ RK_IOMUX(8, 0, 0x0080, 2),
+ RK_IOMUX(8, 1, 0x0084, 2),
+ /* 8,2 - Empty */
+ /* 8,3 - Empty */
+
+};
+
+static struct rk_pinctrl_pin_fixup rk3288_pin_fixup[] = {
+};
+
+static struct rk_pinctrl_pin_drive rk3288_pin_drive[] = {
+ /* bank sub offs val ma */
+ /* GPIO0A (PMU)*/
+ RK_PINDRIVE(0, 0, 0x070, 0, 2),
+ RK_PINDRIVE(0, 0, 0x070, 1, 4),
+ RK_PINDRIVE(0, 0, 0x070, 2, 8),
+ RK_PINDRIVE(0, 0, 0x070, 3, 12),
+
+ /* GPIO0B (PMU)*/
+ RK_PINDRIVE(0, 1, 0x074, 0, 2),
+ RK_PINDRIVE(0, 1, 0x074, 1, 4),
+ RK_PINDRIVE(0, 1, 0x074, 2, 8),
+ RK_PINDRIVE(0, 1, 0x074, 3, 12),
+
+ /* GPIO0C (PMU)*/
+ RK_PINDRIVE(0, 2, 0x078, 0, 2),
+ RK_PINDRIVE(0, 2, 0x078, 1, 4),
+ RK_PINDRIVE(0, 2, 0x078, 2, 8),
+ RK_PINDRIVE(0, 2, 0x078, 3, 12),
+
+ /* GPIO1D */
+ RK_PINDRIVE(1, 3, 0x1CC, 0, 2),
+ RK_PINDRIVE(1, 3, 0x1CC, 1, 4),
+ RK_PINDRIVE(1, 3, 0x1CC, 2, 8),
+ RK_PINDRIVE(1, 3, 0x1CC, 3, 12),
+
+ /* GPIO2A */
+ RK_PINDRIVE(2, 0, 0x1D0, 0, 2),
+ RK_PINDRIVE(2, 0, 0x1D0, 1, 4),
+ RK_PINDRIVE(2, 0, 0x1D0, 2, 8),
+ RK_PINDRIVE(2, 0, 0x1D0, 3, 12),
+
+ /* GPIO2B */
+ RK_PINDRIVE(2, 1, 0x1D4, 0, 2),
+ RK_PINDRIVE(2, 1, 0x1D4, 1, 4),
+ RK_PINDRIVE(2, 1, 0x1D4, 2, 8),
+ RK_PINDRIVE(2, 1, 0x1D4, 3, 12),
+
+ /* GPIO2C */
+ RK_PINDRIVE(2, 2, 0x1D8, 0, 2),
+ RK_PINDRIVE(2, 2, 0x1D8, 1, 4),
+ RK_PINDRIVE(2, 2, 0x1D8, 2, 8),
+ RK_PINDRIVE(2, 2, 0x1D8, 3, 12),
+
+ /* GPIO2D */
+ RK_PINDRIVE(2, 3, 0x1DC, 0, 2),
+ RK_PINDRIVE(2, 3, 0x1DC, 1, 4),
+ RK_PINDRIVE(2, 3, 0x1DC, 2, 8),
+ RK_PINDRIVE(2, 3, 0x1DC, 3, 12),
+
+ /* GPIO3A */
+ RK_PINDRIVE(3, 0, 0x1E0, 0, 2),
+ RK_PINDRIVE(3, 0, 0x1E0, 1, 4),
+ RK_PINDRIVE(3, 0, 0x1E0, 2, 8),
+ RK_PINDRIVE(3, 0, 0x1E0, 3, 12),
+
+ /* GPIO3B */
+ RK_PINDRIVE(3, 1, 0x1E4, 0, 2),
+ RK_PINDRIVE(3, 1, 0x1E4, 1, 4),
+ RK_PINDRIVE(3, 1, 0x1E4, 2, 8),
+ RK_PINDRIVE(3, 1, 0x1E4, 3, 12),
+
+ /* GPIO3C */
+ RK_PINDRIVE(3, 2, 0x1E8, 0, 2),
+ RK_PINDRIVE(3, 2, 0x1E8, 1, 4),
+ RK_PINDRIVE(3, 2, 0x1E8, 2, 8),
+ RK_PINDRIVE(3, 2, 0x1E8, 3, 12),
+
+ /* GPIO3D */
+ RK_PINDRIVE(3, 3, 0x1EC, 0, 2),
+ RK_PINDRIVE(3, 3, 0x1EC, 1, 4),
+ RK_PINDRIVE(3, 3, 0x1EC, 2, 8),
+ RK_PINDRIVE(3, 3, 0x1EC, 3, 12),
+
+ /* GPIO4A */
+ RK_PINDRIVE(4, 0, 0x1F0, 0, 2),
+ RK_PINDRIVE(4, 0, 0x1F0, 1, 4),
+ RK_PINDRIVE(4, 0, 0x1F0, 2, 8),
+ RK_PINDRIVE(4, 0, 0x1F0, 3, 12),
+
+ /* GPIO4B */
+ RK_PINDRIVE(4, 1, 0x1F4, 0, 2),
+ RK_PINDRIVE(4, 1, 0x1F4, 1, 4),
+ RK_PINDRIVE(4, 1, 0x1F4, 2, 8),
+ RK_PINDRIVE(4, 1, 0x1F4, 3, 12),
+
+ /* GPIO4C */
+ RK_PINDRIVE(4, 2, 0x1F8, 0, 2),
+ RK_PINDRIVE(4, 2, 0x1F8, 1, 4),
+ RK_PINDRIVE(4, 2, 0x1F8, 2, 8),
+ RK_PINDRIVE(4, 2, 0x1F8, 3, 12),
+
+ /* GPIO4D */
+ RK_PINDRIVE(4, 3, 0x1FC, 0, 2),
+ RK_PINDRIVE(4, 3, 0x1FC, 1, 4),
+ RK_PINDRIVE(4, 3, 0x1FC, 2, 8),
+ RK_PINDRIVE(4, 3, 0x1FC, 3, 12),
+
+ /* GPIO5B */
+ RK_PINDRIVE(5, 1, 0x204, 0, 2),
+ RK_PINDRIVE(5, 1, 0x204, 1, 4),
+ RK_PINDRIVE(5, 1, 0x204, 2, 8),
+ RK_PINDRIVE(5, 1, 0x204, 3, 12),
+
+ /* GPIO5C */
+ RK_PINDRIVE(5, 2, 0x208, 0, 2),
+ RK_PINDRIVE(5, 2, 0x208, 1, 4),
+ RK_PINDRIVE(5, 2, 0x208, 2, 8),
+ RK_PINDRIVE(5, 2, 0x208, 3, 12),
+
+ /* GPIO6A */
+ RK_PINDRIVE(6, 0, 0x210, 0, 2),
+ RK_PINDRIVE(6, 0, 0x210, 1, 4),
+ RK_PINDRIVE(6, 0, 0x210, 2, 8),
+ RK_PINDRIVE(6, 0, 0x210, 3, 12),
+
+ /* GPIO6B */
+ RK_PINDRIVE(6, 1, 0x214, 0, 2),
+ RK_PINDRIVE(6, 1, 0x214, 1, 4),
+ RK_PINDRIVE(6, 1, 0x214, 2, 8),
+ RK_PINDRIVE(6, 1, 0x214, 3, 12),
+
+ /* GPIO6C */
+ RK_PINDRIVE(6, 2, 0x218, 0, 2),
+ RK_PINDRIVE(6, 2, 0x218, 1, 4),
+ RK_PINDRIVE(6, 2, 0x218, 2, 8),
+ RK_PINDRIVE(6, 2, 0x218, 3, 12),
+
+ /* GPIO7A */
+ RK_PINDRIVE(7, 0, 0x220, 0, 2),
+ RK_PINDRIVE(7, 0, 0x220, 1, 4),
+ RK_PINDRIVE(7, 0, 0x220, 2, 8),
+ RK_PINDRIVE(7, 0, 0x220, 3, 12),
+
+ /* GPIO7B */
+ RK_PINDRIVE(7, 1, 0x224, 0, 2),
+ RK_PINDRIVE(7, 1, 0x224, 1, 4),
+ RK_PINDRIVE(7, 1, 0x224, 2, 8),
+ RK_PINDRIVE(7, 1, 0x224, 3, 12),
+
+ /* GPIO7C */
+ RK_PINDRIVE(7, 2, 0x228, 0, 2),
+ RK_PINDRIVE(7, 2, 0x228, 1, 4),
+ RK_PINDRIVE(7, 2, 0x228, 2, 8),
+ RK_PINDRIVE(7, 2, 0x228, 3, 12),
+
+ /* GPIO8A */
+ RK_PINDRIVE(8, 0, 0x230, 0, 2),
+ RK_PINDRIVE(8, 0, 0x230, 1, 4),
+ RK_PINDRIVE(8, 0, 0x230, 2, 8),
+ RK_PINDRIVE(8, 0, 0x230, 3, 12),
+
+ /* GPIO8B */
+ RK_PINDRIVE(8, 1, 0x234, 0, 2),
+ RK_PINDRIVE(8, 1, 0x234, 1, 4),
+ RK_PINDRIVE(8, 1, 0x234, 2, 8),
+ RK_PINDRIVE(8, 1, 0x234, 3, 12),
+};
+
+static uint32_t
+rk3288_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank)
+{
+ if (bank == 0)
+ return (0x064); /* PMU */
+ return (0x130);
+}
+
+static struct syscon *
+rk3288_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank)
+{
+ if (bank == 0)
+ return (sc->pmu);
+ return (sc->grf);
+}
+
+struct rk_pinctrl_conf rk3288_conf = {
+ .iomux_conf = rk3288_iomux_bank,
+ .iomux_nbanks = nitems(rk3288_iomux_bank),
+ .pin_fixup = rk3288_pin_fixup,
+ .npin_fixup = nitems(rk3288_pin_fixup),
+ .pin_drive = rk3288_pin_drive,
+ .npin_drive = nitems(rk3288_pin_drive),
+ .gpio_bank = rk3288_gpio_bank,
+ .ngpio_bank = nitems(rk3288_gpio_bank),
+ .get_pd_offset = rk3288_get_pd_offset,
+ .get_syscon = rk3288_get_syscon,
+};
+
static struct rk_pinctrl_bank rk3328_iomux_bank[] = {
- {
- .bank_num = 0,
- .subbank_num = 0,
- .offset = 0x00,
- .nbits = 2,
- },
- {
- .bank_num = 0,
- .subbank_num = 1,
- .offset = 0x04,
- .nbits = 2,
- },
- {
- .bank_num = 0,
- .subbank_num = 2,
- .offset = 0x08,
- .nbits = 2,
- },
- {
- .bank_num = 0,
- .subbank_num = 3,
- .offset = 0xc,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 0,
- .offset = 0x10,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 1,
- .offset = 0x14,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 2,
- .offset = 0x18,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 3,
- .offset = 0x1C,
- .nbits = 2,
- },
- {
- .bank_num = 2,
- .subbank_num = 0,
- .offset = 0x20,
- .nbits = 2,
- },
- {
- .bank_num = 2,
- .subbank_num = 1,
- .offset = 0x24,
- .nbits = 3,
- },
- {
- .bank_num = 2,
- .subbank_num = 2,
- .offset = 0x2c,
- .nbits = 3,
- },
- {
- .bank_num = 2,
- .subbank_num = 3,
- .offset = 0x34,
- .nbits = 2,
- },
- {
- .bank_num = 3,
- .subbank_num = 0,
- .offset = 0x38,
- .nbits = 3,
- },
- {
- .bank_num = 3,
- .subbank_num = 1,
- .offset = 0x40,
- .nbits = 3,
- },
- {
- .bank_num = 3,
- .subbank_num = 2,
- .offset = 0x48,
- .nbits = 2,
- },
- {
- .bank_num = 3,
- .subbank_num = 3,
- .offset = 0x4c,
- .nbits = 2,
- },
+ /* bank sub offs nbits */
+ RK_IOMUX(0, 0, 0x0000, 2),
+ RK_IOMUX(0, 1, 0x0004, 2),
+ RK_IOMUX(0, 2, 0x0008, 2),
+ RK_IOMUX(0, 3, 0x000C, 2),
+ RK_IOMUX(1, 0, 0x0010, 2),
+ RK_IOMUX(1, 1, 0x0014, 2),
+ RK_IOMUX(1, 2, 0x0018, 2),
+ RK_IOMUX(1, 3, 0x001C, 2),
+ RK_IOMUX(2, 0, 0xE000, 2),
+ RK_IOMUX(2, 1, 0xE004, 2),
+ RK_IOMUX(2, 2, 0xE008, 2),
+ RK_IOMUX(2, 3, 0xE00C, 2),
+ RK_IOMUX(3, 0, 0xE010, 2),
+ RK_IOMUX(3, 1, 0xE014, 2),
+ RK_IOMUX(3, 2, 0xE018, 2),
+ RK_IOMUX(3, 3, 0xE01C, 2),
+ RK_IOMUX(4, 0, 0xE020, 2),
+ RK_IOMUX(4, 1, 0xE024, 2),
+ RK_IOMUX(4, 2, 0xE028, 2),
+ RK_IOMUX(4, 3, 0xE02C, 2),
};
static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = {
- {
- .bank = 2,
- .pin = 12,
- .reg = 0x24,
- .bit = 8,
- .mask = 0x300,
- },
- {
- .bank = 2,
- .pin = 15,
- .reg = 0x28,
- .bit = 0,
- .mask = 0x7,
- },
- {
- .bank = 2,
- .pin = 23,
- .reg = 0x30,
- .bit = 14,
- .mask = 0x6000,
- },
+ /* bank pin reg bit mask */
+ RK_PINFIX(2, 12, 0x24, 8, 0x300),
+ RK_PINFIX(2, 15, 0x28, 0, 0x7),
+ RK_PINFIX(2, 23, 0x30, 14, 0x6000),
};
-#define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma) \
- { \
- .bank = _bank, \
- .subbank = _subbank, \
- .offset = _offset, \
- .value = _value, \
- .ma = _ma, \
- },
static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = {
- RK_PINDRIVE(0, 0, 0x200, 0, 2)
- RK_PINDRIVE(0, 0, 0x200, 1, 4)
- RK_PINDRIVE(0, 0, 0x200, 2, 8)
- RK_PINDRIVE(0, 0, 0x200, 3, 12)
+ /* bank sub offs val ma */
+ RK_PINDRIVE(0, 0, 0x200, 0, 2),
+ RK_PINDRIVE(0, 0, 0x200, 1, 4),
+ RK_PINDRIVE(0, 0, 0x200, 2, 8),
+ RK_PINDRIVE(0, 0, 0x200, 3, 12),
- RK_PINDRIVE(0, 1, 0x204, 0, 2)
- RK_PINDRIVE(0, 1, 0x204, 1, 4)
- RK_PINDRIVE(0, 1, 0x204, 2, 8)
- RK_PINDRIVE(0, 1, 0x204, 3, 12)
+ RK_PINDRIVE(0, 1, 0x204, 0, 2),
+ RK_PINDRIVE(0, 1, 0x204, 1, 4),
+ RK_PINDRIVE(0, 1, 0x204, 2, 8),
+ RK_PINDRIVE(0, 1, 0x204, 3, 12),
- RK_PINDRIVE(0, 2, 0x208, 0, 2)
- RK_PINDRIVE(0, 2, 0x208, 1, 4)
- RK_PINDRIVE(0, 2, 0x208, 2, 8)
- RK_PINDRIVE(0, 2, 0x208, 3, 12)
+ RK_PINDRIVE(0, 2, 0x208, 0, 2),
+ RK_PINDRIVE(0, 2, 0x208, 1, 4),
+ RK_PINDRIVE(0, 2, 0x208, 2, 8),
+ RK_PINDRIVE(0, 2, 0x208, 3, 12),
- RK_PINDRIVE(0, 3, 0x20C, 0, 2)
- RK_PINDRIVE(0, 3, 0x20C, 1, 4)
- RK_PINDRIVE(0, 3, 0x20C, 2, 8)
- RK_PINDRIVE(0, 3, 0x20C, 3, 12)
+ RK_PINDRIVE(0, 3, 0x20C, 0, 2),
+ RK_PINDRIVE(0, 3, 0x20C, 1, 4),
+ RK_PINDRIVE(0, 3, 0x20C, 2, 8),
+ RK_PINDRIVE(0, 3, 0x20C, 3, 12),
- RK_PINDRIVE(1, 0, 0x210, 0, 2)
- RK_PINDRIVE(1, 0, 0x210, 1, 4)
- RK_PINDRIVE(1, 0, 0x210, 2, 8)
- RK_PINDRIVE(1, 0, 0x210, 3, 12)
+ RK_PINDRIVE(1, 0, 0x210, 0, 2),
+ RK_PINDRIVE(1, 0, 0x210, 1, 4),
+ RK_PINDRIVE(1, 0, 0x210, 2, 8),
+ RK_PINDRIVE(1, 0, 0x210, 3, 12),
- RK_PINDRIVE(1, 1, 0x214, 0, 2)
- RK_PINDRIVE(1, 1, 0x214, 1, 4)
- RK_PINDRIVE(1, 1, 0x214, 2, 8)
- RK_PINDRIVE(1, 1, 0x214, 3, 12)
+ RK_PINDRIVE(1, 1, 0x214, 0, 2),
+ RK_PINDRIVE(1, 1, 0x214, 1, 4),
+ RK_PINDRIVE(1, 1, 0x214, 2, 8),
+ RK_PINDRIVE(1, 1, 0x214, 3, 12),
- RK_PINDRIVE(1, 2, 0x218, 0, 2)
- RK_PINDRIVE(1, 2, 0x218, 1, 4)
- RK_PINDRIVE(1, 2, 0x218, 2, 8)
- RK_PINDRIVE(1, 2, 0x218, 3, 12)
+ RK_PINDRIVE(1, 2, 0x218, 0, 2),
+ RK_PINDRIVE(1, 2, 0x218, 1, 4),
+ RK_PINDRIVE(1, 2, 0x218, 2, 8),
+ RK_PINDRIVE(1, 2, 0x218, 3, 12),
- RK_PINDRIVE(1, 3, 0x21C, 0, 2)
- RK_PINDRIVE(1, 3, 0x21C, 1, 4)
- RK_PINDRIVE(1, 3, 0x21C, 2, 8)
- RK_PINDRIVE(1, 3, 0x21C, 3, 12)
+ RK_PINDRIVE(1, 3, 0x21C, 0, 2),
+ RK_PINDRIVE(1, 3, 0x21C, 1, 4),
+ RK_PINDRIVE(1, 3, 0x21C, 2, 8),
+ RK_PINDRIVE(1, 3, 0x21C, 3, 12),
- RK_PINDRIVE(2, 0, 0x220, 0, 2)
- RK_PINDRIVE(2, 0, 0x220, 1, 4)
- RK_PINDRIVE(2, 0, 0x220, 2, 8)
- RK_PINDRIVE(2, 0, 0x220, 3, 12)
+ RK_PINDRIVE(2, 0, 0x220, 0, 2),
+ RK_PINDRIVE(2, 0, 0x220, 1, 4),
+ RK_PINDRIVE(2, 0, 0x220, 2, 8),
+ RK_PINDRIVE(2, 0, 0x220, 3, 12),
- RK_PINDRIVE(2, 1, 0x224, 0, 2)
- RK_PINDRIVE(2, 1, 0x224, 1, 4)
- RK_PINDRIVE(2, 1, 0x224, 2, 8)
- RK_PINDRIVE(2, 1, 0x224, 3, 12)
+ RK_PINDRIVE(2, 1, 0x224, 0, 2),
+ RK_PINDRIVE(2, 1, 0x224, 1, 4),
+ RK_PINDRIVE(2, 1, 0x224, 2, 8),
+ RK_PINDRIVE(2, 1, 0x224, 3, 12),
- RK_PINDRIVE(2, 2, 0x228, 0, 2)
- RK_PINDRIVE(2, 2, 0x228, 1, 4)
- RK_PINDRIVE(2, 2, 0x228, 2, 8)
- RK_PINDRIVE(2, 2, 0x228, 3, 12)
+ RK_PINDRIVE(2, 2, 0x228, 0, 2),
+ RK_PINDRIVE(2, 2, 0x228, 1, 4),
+ RK_PINDRIVE(2, 2, 0x228, 2, 8),
+ RK_PINDRIVE(2, 2, 0x228, 3, 12),
- RK_PINDRIVE(2, 3, 0x22C, 0, 2)
- RK_PINDRIVE(2, 3, 0x22C, 1, 4)
- RK_PINDRIVE(2, 3, 0x22C, 2, 8)
- RK_PINDRIVE(2, 3, 0x22C, 3, 12)
+ RK_PINDRIVE(2, 3, 0x22C, 0, 2),
+ RK_PINDRIVE(2, 3, 0x22C, 1, 4),
+ RK_PINDRIVE(2, 3, 0x22C, 2, 8),
+ RK_PINDRIVE(2, 3, 0x22C, 3, 12),
- RK_PINDRIVE(3, 0, 0x230, 0, 2)
- RK_PINDRIVE(3, 0, 0x230, 1, 4)
- RK_PINDRIVE(3, 0, 0x230, 2, 8)
- RK_PINDRIVE(3, 0, 0x230, 3, 12)
+ RK_PINDRIVE(3, 0, 0x230, 0, 2),
+ RK_PINDRIVE(3, 0, 0x230, 1, 4),
+ RK_PINDRIVE(3, 0, 0x230, 2, 8),
+ RK_PINDRIVE(3, 0, 0x230, 3, 12),
- RK_PINDRIVE(3, 1, 0x234, 0, 2)
- RK_PINDRIVE(3, 1, 0x234, 1, 4)
- RK_PINDRIVE(3, 1, 0x234, 2, 8)
- RK_PINDRIVE(3, 1, 0x234, 3, 12)
+ RK_PINDRIVE(3, 1, 0x234, 0, 2),
+ RK_PINDRIVE(3, 1, 0x234, 1, 4),
+ RK_PINDRIVE(3, 1, 0x234, 2, 8),
+ RK_PINDRIVE(3, 1, 0x234, 3, 12),
- RK_PINDRIVE(3, 2, 0x238, 0, 2)
- RK_PINDRIVE(3, 2, 0x238, 1, 4)
- RK_PINDRIVE(3, 2, 0x238, 2, 8)
- RK_PINDRIVE(3, 2, 0x238, 3, 12)
+ RK_PINDRIVE(3, 2, 0x238, 0, 2),
+ RK_PINDRIVE(3, 2, 0x238, 1, 4),
+ RK_PINDRIVE(3, 2, 0x238, 2, 8),
+ RK_PINDRIVE(3, 2, 0x238, 3, 12),
- RK_PINDRIVE(3, 3, 0x23C, 0, 2)
- RK_PINDRIVE(3, 3, 0x23C, 1, 4)
- RK_PINDRIVE(3, 3, 0x23C, 2, 8)
- RK_PINDRIVE(3, 3, 0x23C, 3, 12)
+ RK_PINDRIVE(3, 3, 0x23C, 0, 2),
+ RK_PINDRIVE(3, 3, 0x23C, 1, 4),
+ RK_PINDRIVE(3, 3, 0x23C, 2, 8),
+ RK_PINDRIVE(3, 3, 0x23C, 3, 12),
};
static uint32_t
@@ -340,166 +523,68 @@ struct rk_pinctrl_conf rk3328_conf = {
};
static struct rk_pinctrl_bank rk3399_iomux_bank[] = {
- {
- .bank_num = 0,
- .subbank_num = 0,
- .offset = 0x00,
- .nbits = 2,
- },
- {
- .bank_num = 0,
- .subbank_num = 1,
- .offset = 0x04,
- .nbits = 2,
- },
- {
- .bank_num = 0,
- .subbank_num = 2,
- .offset = 0x08,
- .nbits = 2,
- },
- {
- .bank_num = 0,
- .subbank_num = 3,
- .offset = 0x0c,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 0,
- .offset = 0x10,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 1,
- .offset = 0x14,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 2,
- .offset = 0x18,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 3,
- .offset = 0x1c,
- .nbits = 2,
- },
- {
- .bank_num = 2,
- .subbank_num = 0,
- .offset = 0xe000,
- .nbits = 2,
- },
- {
- .bank_num = 2,
- .subbank_num = 1,
- .offset = 0xe004,
- .nbits = 2,
- },
- {
- .bank_num = 2,
- .subbank_num = 2,
- .offset = 0xe008,
- .nbits = 2,
- },
- {
- .bank_num = 2,
- .subbank_num = 3,
- .offset = 0xe00c,
- .nbits = 2,
- },
- {
- .bank_num = 3,
- .subbank_num = 0,
- .offset = 0xe010,
- .nbits = 2,
- },
- {
- .bank_num = 3,
- .subbank_num = 1,
- .offset = 0xe014,
- .nbits = 2,
- },
- {
- .bank_num = 3,
- .subbank_num = 2,
- .offset = 0xe018,
- .nbits = 2,
- },
- {
- .bank_num = 3,
- .subbank_num = 3,
- .offset = 0xe01c,
- .nbits = 2,
- },
- {
- .bank_num = 4,
- .subbank_num = 0,
- .offset = 0xe020,
- .nbits = 2,
- },
- {
- .bank_num = 4,
- .subbank_num = 1,
- .offset = 0xe024,
- .nbits = 2,
- },
- {
- .bank_num = 4,
- .subbank_num = 2,
- .offset = 0xe028,
- .nbits = 2,
- },
- {
- .bank_num = 4,
- .subbank_num = 3,
- .offset = 0xe02c,
- .nbits = 2,
- },
+ /* bank sub offs nbits */
+ RK_IOMUX(0, 0, 0x0000, 2),
+ RK_IOMUX(0, 1, 0x0004, 2),
+ RK_IOMUX(0, 2, 0x0008, 2),
+ RK_IOMUX(0, 3, 0x000C, 2),
+ RK_IOMUX(1, 0, 0x0010, 2),
+ RK_IOMUX(1, 1, 0x0014, 2),
+ RK_IOMUX(1, 2, 0x0018, 2),
+ RK_IOMUX(1, 3, 0x000C, 2),
+ RK_IOMUX(2, 0, 0xE000, 2),
+ RK_IOMUX(2, 1, 0xE004, 2),
+ RK_IOMUX(2, 2, 0xE008, 2),
+ RK_IOMUX(2, 3, 0xE00C, 2),
+ RK_IOMUX(3, 0, 0xE010, 2),
+ RK_IOMUX(3, 1, 0xE014, 2),
+ RK_IOMUX(3, 2, 0xE018, 2),
+ RK_IOMUX(3, 3, 0xE01C, 2),
+ RK_IOMUX(4, 0, 0xE020, 2),
+ RK_IOMUX(4, 1, 0xE024, 2),
+ RK_IOMUX(4, 2, 0xE028, 2),
+ RK_IOMUX(4, 3, 0xE02C, 2),
};
static struct rk_pinctrl_pin_fixup rk3399_pin_fixup[] = {};
static struct rk_pinctrl_pin_drive rk3399_pin_drive[] = {
+ /* bank sub offs val ma */
/* GPIO0A */
- RK_PINDRIVE(0, 0, 0x80, 0, 5)
- RK_PINDRIVE(0, 0, 0x80, 1, 10)
- RK_PINDRIVE(0, 0, 0x80, 2, 15)
- RK_PINDRIVE(0, 0, 0x80, 3, 20)
+ RK_PINDRIVE(0, 0, 0x80, 0, 5),
+ RK_PINDRIVE(0, 0, 0x80, 1, 10),
+ RK_PINDRIVE(0, 0, 0x80, 2, 15),
+ RK_PINDRIVE(0, 0, 0x80, 3, 20),
/* GPIOB */
- RK_PINDRIVE(0, 1, 0x88, 0, 5)
- RK_PINDRIVE(0, 1, 0x88, 1, 10)
- RK_PINDRIVE(0, 1, 0x88, 2, 15)
- RK_PINDRIVE(0, 1, 0x88, 3, 20)
+ RK_PINDRIVE(0, 1, 0x88, 0, 5),
+ RK_PINDRIVE(0, 1, 0x88, 1, 10),
+ RK_PINDRIVE(0, 1, 0x88, 2, 15),
+ RK_PINDRIVE(0, 1, 0x88, 3, 20),
/* GPIO1A */
- RK_PINDRIVE(1, 0, 0xA0, 0, 3)
- RK_PINDRIVE(1, 0, 0xA0, 1, 6)
- RK_PINDRIVE(1, 0, 0xA0, 2, 9)
- RK_PINDRIVE(1, 0, 0xA0, 3, 12)
+ RK_PINDRIVE(1, 0, 0xA0, 0, 3),
+ RK_PINDRIVE(1, 0, 0xA0, 1, 6),
+ RK_PINDRIVE(1, 0, 0xA0, 2, 9),
+ RK_PINDRIVE(1, 0, 0xA0, 3, 12),
/* GPIO1B */
- RK_PINDRIVE(1, 1, 0xA8, 0, 3)
- RK_PINDRIVE(1, 1, 0xA8, 1, 6)
- RK_PINDRIVE(1, 1, 0xA8, 2, 9)
- RK_PINDRIVE(1, 1, 0xA8, 3, 12)
+ RK_PINDRIVE(1, 1, 0xA8, 0, 3),
+ RK_PINDRIVE(1, 1, 0xA8, 1, 6),
+ RK_PINDRIVE(1, 1, 0xA8, 2, 9),
+ RK_PINDRIVE(1, 1, 0xA8, 3, 12),
/* GPIO1C */
- RK_PINDRIVE(1, 2, 0xB0, 0, 3)
- RK_PINDRIVE(1, 2, 0xB0, 1, 6)
- RK_PINDRIVE(1, 2, 0xB0, 2, 9)
- RK_PINDRIVE(1, 2, 0xB0, 3, 12)
+ RK_PINDRIVE(1, 2, 0xB0, 0, 3),
+ RK_PINDRIVE(1, 2, 0xB0, 1, 6),
+ RK_PINDRIVE(1, 2, 0xB0, 2, 9),
+ RK_PINDRIVE(1, 2, 0xB0, 3, 12),
/* GPIO1D */
- RK_PINDRIVE(1, 3, 0xB8, 0, 3)
- RK_PINDRIVE(1, 3, 0xB8, 1, 6)
- RK_PINDRIVE(1, 3, 0xB8, 2, 9)
- RK_PINDRIVE(1, 3, 0xB8, 3, 12)
+ RK_PINDRIVE(1, 3, 0xB8, 0, 3),
+ RK_PINDRIVE(1, 3, 0xB8, 1, 6),
+ RK_PINDRIVE(1, 3, 0xB8, 2, 9),
+ RK_PINDRIVE(1, 3, 0xB8, 3, 12),
};
static uint32_t
@@ -508,7 +593,7 @@ rk3399_get_pd_offset(struct rk_pinctrl_softc *sc, uint
if (bank < 2)
return (0x40);
- return (0xe040);
+ return (0xE040);
}
static struct syscon *
@@ -532,12 +617,9 @@ struct rk_pinctrl_conf rk3399_conf = {
};
static struct ofw_compat_data compat_data[] = {
-#ifdef SOC_ROCKCHIP_RK3328
+ {"rockchip,rk3288-pinctrl", (uintptr_t)&rk3288_conf},
{"rockchip,rk3328-pinctrl", (uintptr_t)&rk3328_conf},
-#endif
-#ifdef SOC_ROCKCHIP_RK3399
{"rockchip,rk3399-pinctrl", (uintptr_t)&rk3399_conf},
-#endif
{NULL, 0}
};
@@ -554,7 +636,8 @@ rk_pinctrl_parse_bias(phandle_t node)
return (-1);
}
-static int rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node,
+static int
+rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node,
uint32_t bank, uint32_t subbank, uint32_t *drive, uint32_t *offset)
{
uint32_t value;
@@ -595,6 +678,91 @@ rk_pinctrl_get_fixup(struct rk_pinctrl_softc *sc, uint
}
}
+static int
+rk_pinctrl_handle_io(struct rk_pinctrl_softc *sc, phandle_t node, uint32_t bank,
+uint32_t pin)
+{
+ bool have_cfg, have_direction, have_value;
+ uint32_t direction_value, pin_value;
+ struct rk_pinctrl_gpio *gpio;
+ int i, rv;
+
+ have_cfg = false;
+ have_direction = false;
+ have_value = false;
+
+ /* Get (subset of) GPIO pin properties. */
+ if (OF_hasprop(node, "output-disable")) {
+ have_cfg = true;
+ have_direction = true;
+ direction_value = GPIO_PIN_INPUT;
+ }
+
+ if (OF_hasprop(node, "output-enable")) {
+ have_cfg = true;
+ have_direction = true;
+ direction_value = GPIO_PIN_OUTPUT;
+ }
+
+ if (OF_hasprop(node, "output-low")) {
+ have_cfg = true;
+ have_direction = true;
+ direction_value = GPIO_PIN_OUTPUT;
+ have_value = true;
+ pin_value = 0;
+ }
+
+ if (OF_hasprop(node, "output-high")) {
+ have_cfg = true;
+ have_direction = true;
+ direction_value = GPIO_PIN_OUTPUT;
+ have_value = true;
+ pin_value = 1;
+ }
+
+ if (!have_cfg)
+ return (0);
+
+ /* Find gpio */
+ gpio = NULL;
+ for(i = 0; i < sc->conf->ngpio_bank; i++) {
+ if (bank == sc->conf->gpio_bank[i].bank) {
+ gpio = sc->conf->gpio_bank + i;
+ break;
+ }
+ }
+ if (gpio == NULL) {
+ device_printf(sc->dev, "Cannot find GPIO bank %d\n", bank);
+ return (ENXIO);
+ }
+ if (gpio->gpio_dev == NULL) {
+ device_printf(sc->dev,
+ "No GPIO subdevice found for bank %d\n", bank);
+ return (ENXIO);
+ }
+
+ rv = 0;
+ if (have_value) {
+ rv = GPIO_PIN_SET(gpio->gpio_dev, pin, pin_value);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot set GPIO value: %d\n",
+ rv);
+ return (rv);
+ }
+ }
+
+ if (have_direction) {
+ rv = GPIO_PIN_SETFLAGS(gpio->gpio_dev, pin, direction_value);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot set GPIO direction: %d\n", rv);
+ return (rv);
+ }
+ }
+
+ return (0);
+}
+
static void
rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, uint32_t *pindata)
{
@@ -602,7 +770,7 @@ rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc,
struct syscon *syscon;
uint32_t bank, subbank, pin, function, bias;
uint32_t bit, mask, reg, drive;
- int i;
+ int i, rv;
bank = pindata[0];
pin = pindata[1];
@@ -611,8 +779,8 @@ rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc,
subbank = pin / 8;
for (i = 0; i < sc->conf->iomux_nbanks; i++)
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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