svn commit: r334456 - in head: lib/libpmc sys/amd64/include sys/conf sys/dev/hwpmc sys/i386/include sys/modules/hwpmc
Matt Macy
mmacy at FreeBSD.org
Thu May 31 22:41:08 UTC 2018
Author: mmacy
Date: Thu May 31 22:41:07 2018
New Revision: 334456
URL: https://svnweb.freebsd.org/changeset/base/334456
Log:
hwpmc: remove unused pre-table driven bits for intel
Intel now provides comprehensive tables for all performance counters
and the various valid configuration permutations as text .json files.
Libpmc has been converted to use these and hwpmc_core has been greatly
simplified by moving to passthrough of the table values.
The one gotcha is that said tables don't support pentium pro and and pentium
IV. There's very few users of hwpmc on _amd64_ kernels on new hardware. It is
unlikely that anyone is doing low level optimization on 15 year old Intel
hardware. Nonetheless, if someone feels strongly enough to populate the
corresponding tables for p4 and ppro I will reinstate the files in to the
build.
Code for the K8 counters and !x86 architectures remains unchanged.
Deleted:
head/sys/dev/hwpmc/hwpmc_pentium.c
head/sys/dev/hwpmc/hwpmc_pentium.h
head/sys/dev/hwpmc/hwpmc_piv.c
head/sys/dev/hwpmc/hwpmc_piv.h
head/sys/dev/hwpmc/hwpmc_ppro.c
head/sys/dev/hwpmc/hwpmc_ppro.h
Modified:
head/lib/libpmc/libpmc.c
head/sys/amd64/include/pmc_mdep.h
head/sys/conf/files.amd64
head/sys/conf/files.i386
head/sys/dev/hwpmc/hwpmc_core.c
head/sys/dev/hwpmc/hwpmc_intel.c
head/sys/dev/hwpmc/hwpmc_uncore.c
head/sys/dev/hwpmc/hwpmc_uncore.h
head/sys/dev/hwpmc/pmc_events.h
head/sys/i386/include/pmc_mdep.h
head/sys/modules/hwpmc/Makefile
Modified: head/lib/libpmc/libpmc.c
==============================================================================
--- head/lib/libpmc/libpmc.c Thu May 31 22:26:55 2018 (r334455)
+++ head/lib/libpmc/libpmc.c Thu May 31 22:41:07 2018 (r334456)
@@ -48,30 +48,10 @@ __FBSDID("$FreeBSD$");
#include "libpmcinternal.h"
/* Function prototypes */
-#if defined(__i386__)
-static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
- struct pmc_op_pmcallocate *_pmc_config);
-#endif
#if defined(__amd64__) || defined(__i386__)
-static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
- struct pmc_op_pmcallocate *_pmc_config);
-static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
- struct pmc_op_pmcallocate *_pmc_config);
-static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
- struct pmc_op_pmcallocate *_pmc_config);
-static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
- struct pmc_op_pmcallocate *_pmc_config);
static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
struct pmc_op_pmcallocate *_pmc_config);
-static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
- struct pmc_op_pmcallocate *_pmc_config);
#endif
-#if defined(__i386__)
-static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
- struct pmc_op_pmcallocate *_pmc_config);
-static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
- struct pmc_op_pmcallocate *_pmc_config);
-#endif
#if defined(__amd64__) || defined(__i386__)
static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
struct pmc_op_pmcallocate *_pmc_config);
@@ -157,18 +137,13 @@ struct pmc_class_descr {
}
PMC_CLASSDEP_TABLE(iaf, IAF);
-PMC_CLASSDEP_TABLE(k7, K7);
PMC_CLASSDEP_TABLE(k8, K8);
-PMC_CLASSDEP_TABLE(p4, P4);
-PMC_CLASSDEP_TABLE(p5, P5);
-PMC_CLASSDEP_TABLE(p6, P6);
PMC_CLASSDEP_TABLE(xscale, XSCALE);
PMC_CLASSDEP_TABLE(armv7, ARMV7);
PMC_CLASSDEP_TABLE(armv8, ARMV8);
PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
PMC_CLASSDEP_TABLE(mips74k, MIPS74K);
PMC_CLASSDEP_TABLE(octeon, OCTEON);
-PMC_CLASSDEP_TABLE(ucf, UCF);
PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
PMC_CLASSDEP_TABLE(ppc970, PPC970);
PMC_CLASSDEP_TABLE(e500, E500);
@@ -178,122 +153,6 @@ static struct pmc_event_descr soft_event_table[PMC_EV_
#undef __PMC_EV_ALIAS
#define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE },
-static const struct pmc_event_descr atom_event_table[] =
-{
- __PMC_EV_ALIAS_ATOM()
-};
-
-static const struct pmc_event_descr atom_silvermont_event_table[] =
-{
- __PMC_EV_ALIAS_ATOM_SILVERMONT()
-};
-
-static const struct pmc_event_descr core_event_table[] =
-{
- __PMC_EV_ALIAS_CORE()
-};
-
-
-static const struct pmc_event_descr core2_event_table[] =
-{
- __PMC_EV_ALIAS_CORE2()
-};
-
-static const struct pmc_event_descr corei7_event_table[] =
-{
- __PMC_EV_ALIAS_COREI7()
-};
-
-static const struct pmc_event_descr nehalem_ex_event_table[] =
-{
- __PMC_EV_ALIAS_COREI7()
-};
-
-static const struct pmc_event_descr haswell_event_table[] =
-{
- __PMC_EV_ALIAS_HASWELL()
-};
-
-static const struct pmc_event_descr haswell_xeon_event_table[] =
-{
- __PMC_EV_ALIAS_HASWELL_XEON()
-};
-
-static const struct pmc_event_descr broadwell_event_table[] =
-{
- __PMC_EV_ALIAS_BROADWELL()
-};
-
-static const struct pmc_event_descr broadwell_xeon_event_table[] =
-{
- __PMC_EV_ALIAS_BROADWELL_XEON()
-};
-
-static const struct pmc_event_descr skylake_event_table[] =
-{
- __PMC_EV_ALIAS_SKYLAKE()
-};
-
-static const struct pmc_event_descr skylake_xeon_event_table[] =
-{
- __PMC_EV_ALIAS_SKYLAKE_XEON()
-};
-
-static const struct pmc_event_descr ivybridge_event_table[] =
-{
- __PMC_EV_ALIAS_IVYBRIDGE()
-};
-
-static const struct pmc_event_descr ivybridge_xeon_event_table[] =
-{
- __PMC_EV_ALIAS_IVYBRIDGE_XEON()
-};
-
-static const struct pmc_event_descr sandybridge_event_table[] =
-{
- __PMC_EV_ALIAS_SANDYBRIDGE()
-};
-
-static const struct pmc_event_descr sandybridge_xeon_event_table[] =
-{
- __PMC_EV_ALIAS_SANDYBRIDGE_XEON()
-};
-
-static const struct pmc_event_descr westmere_event_table[] =
-{
- __PMC_EV_ALIAS_WESTMERE()
-};
-
-static const struct pmc_event_descr westmere_ex_event_table[] =
-{
- __PMC_EV_ALIAS_WESTMERE()
-};
-
-static const struct pmc_event_descr corei7uc_event_table[] =
-{
- __PMC_EV_ALIAS_COREI7UC()
-};
-
-static const struct pmc_event_descr haswelluc_event_table[] =
-{
- __PMC_EV_ALIAS_HASWELLUC()
-};
-
-static const struct pmc_event_descr broadwelluc_event_table[] =
-{
- __PMC_EV_ALIAS_BROADWELLUC()
-};
-
-static const struct pmc_event_descr sandybridgeuc_event_table[] =
-{
- __PMC_EV_ALIAS_SANDYBRIDGEUC()
-};
-
-static const struct pmc_event_descr westmereuc_event_table[] =
-{
- __PMC_EV_ALIAS_WESTMEREUC()
-};
-
static const struct pmc_event_descr cortex_a8_event_table[] =
{
__PMC_EV_ALIAS_ARMV7_CORTEX_A8()
@@ -324,29 +183,7 @@ static const struct pmc_event_descr cortex_a57_event_t
PMC_CLASS_##C, __VA_ARGS__ \
}
-PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
-PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
-PMC_MDEP_TABLE(haswell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
-PMC_MDEP_TABLE(broadwell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
-PMC_MDEP_TABLE(broadwell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
-PMC_MDEP_TABLE(skylake, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
-PMC_MDEP_TABLE(skylake_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
-PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
-PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC);
-PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC);
PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE);
PMC_MDEP_TABLE(cortex_a8, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
@@ -379,43 +216,8 @@ static const struct pmc_class_descr NAME##_class_table
}
#if defined(__i386__) || defined(__amd64__)
-PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf);
-PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
-PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap);
-PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
-PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
-PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
-PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap);
-PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap);
-PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell_xeon, iap);
-PMC_CLASS_TABLE_DESC(broadwell, IAP, broadwell, iap);
-PMC_CLASS_TABLE_DESC(broadwell_xeon, IAP, broadwell_xeon, iap);
-PMC_CLASS_TABLE_DESC(skylake, IAP, skylake, iap);
-PMC_CLASS_TABLE_DESC(skylake_xeon, IAP, skylake_xeon, iap);
-PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
-PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap);
-PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
-PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap);
-PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
-PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap);
-PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
-PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
-PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp);
-PMC_CLASS_TABLE_DESC(broadwelluc, UCP, broadwelluc, ucp);
-PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
-PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
-#endif
-#if defined(__i386__)
-PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
-#endif
-#if defined(__i386__) || defined(__amd64__)
PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
-PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
#endif
-#if defined(__i386__)
-PMC_CLASS_TABLE_DESC(p5, P5, p5, p5);
-PMC_CLASS_TABLE_DESC(p6, P6, p6, p6);
-#endif
#if defined(__i386__) || defined(__amd64__)
PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
#endif
@@ -556,616 +358,10 @@ pmc_parse_mask(const struct pmc_masks *pmask, char *p,
#define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
#define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S }
-#if defined(__i386__)
-
-/*
- * AMD K7 (Athlon) CPUs.
- */
-
-static struct pmc_event_alias k7_aliases[] = {
- EV_ALIAS("branches", "k7-retired-branches"),
- EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"),
- EV_ALIAS("cycles", "tsc"),
- EV_ALIAS("dc-misses", "k7-dc-misses"),
- EV_ALIAS("ic-misses", "k7-ic-misses"),
- EV_ALIAS("instructions", "k7-retired-instructions"),
- EV_ALIAS("interrupts", "k7-hardware-interrupts"),
- EV_ALIAS(NULL, NULL)
-};
-
-#define K7_KW_COUNT "count"
-#define K7_KW_EDGE "edge"
-#define K7_KW_INV "inv"
-#define K7_KW_OS "os"
-#define K7_KW_UNITMASK "unitmask"
-#define K7_KW_USR "usr"
-
-static int
-k7_allocate_pmc(enum pmc_event pe, char *ctrspec,
- struct pmc_op_pmcallocate *pmc_config)
-{
- char *e, *p, *q;
- int c, has_unitmask;
- uint32_t count, unitmask;
-
- pmc_config->pm_md.pm_amd.pm_amd_config = 0;
- pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
-
- if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 ||
- pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM ||
- pe == PMC_EV_K7_DC_WRITEBACKS) {
- has_unitmask = 1;
- unitmask = AMD_PMC_UNITMASK_MOESI;
- } else
- unitmask = has_unitmask = 0;
-
- while ((p = strsep(&ctrspec, ",")) != NULL) {
- if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) {
- q = strchr(p, '=');
- if (*++q == '\0') /* skip '=' */
- return (-1);
-
- count = strtol(q, &e, 0);
- if (e == q || *e != '\0')
- return (-1);
-
- pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
- pmc_config->pm_md.pm_amd.pm_amd_config |=
- AMD_PMC_TO_COUNTER(count);
-
- } else if (KWMATCH(p, K7_KW_EDGE)) {
- pmc_config->pm_caps |= PMC_CAP_EDGE;
- } else if (KWMATCH(p, K7_KW_INV)) {
- pmc_config->pm_caps |= PMC_CAP_INVERT;
- } else if (KWMATCH(p, K7_KW_OS)) {
- pmc_config->pm_caps |= PMC_CAP_SYSTEM;
- } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) {
- if (has_unitmask == 0)
- return (-1);
- unitmask = 0;
- q = strchr(p, '=');
- if (*++q == '\0') /* skip '=' */
- return (-1);
-
- while ((c = tolower(*q++)) != 0)
- if (c == 'm')
- unitmask |= AMD_PMC_UNITMASK_M;
- else if (c == 'o')
- unitmask |= AMD_PMC_UNITMASK_O;
- else if (c == 'e')
- unitmask |= AMD_PMC_UNITMASK_E;
- else if (c == 's')
- unitmask |= AMD_PMC_UNITMASK_S;
- else if (c == 'i')
- unitmask |= AMD_PMC_UNITMASK_I;
- else if (c == '+')
- continue;
- else
- return (-1);
-
- if (unitmask == 0)
- return (-1);
-
- } else if (KWMATCH(p, K7_KW_USR)) {
- pmc_config->pm_caps |= PMC_CAP_USER;
- } else
- return (-1);
- }
-
- if (has_unitmask) {
- pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
- pmc_config->pm_md.pm_amd.pm_amd_config |=
- AMD_PMC_TO_UNITMASK(unitmask);
- }
-
- return (0);
-
-}
-
-#endif
-
#if defined(__amd64__) || defined(__i386__)
-
/*
- * Intel Core (Family 6, Model E) PMCs.
- */
-
-static struct pmc_event_alias core_aliases[] = {
- EV_ALIAS("branches", "iap-br-instr-ret"),
- EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"),
- EV_ALIAS("cycles", "tsc-tsc"),
- EV_ALIAS("ic-misses", "iap-icache-misses"),
- EV_ALIAS("instructions", "iap-instr-ret"),
- EV_ALIAS("interrupts", "iap-core-hw-int-rx"),
- EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"),
- EV_ALIAS(NULL, NULL)
-};
-
-/*
- * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H)
- * and Atom (Family 6, model 1CH) PMCs.
- *
- * We map aliases to events on the fixed-function counters if these
- * are present. Note that not all CPUs in this family contain fixed-function
- * counters.
- */
-
-static struct pmc_event_alias core2_aliases[] = {
- EV_ALIAS("branches", "iap-br-inst-retired.any"),
- EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"),
- EV_ALIAS("cycles", "tsc-tsc"),
- EV_ALIAS("ic-misses", "iap-l1i-misses"),
- EV_ALIAS("instructions", "iaf-instr-retired.any"),
- EV_ALIAS("interrupts", "iap-hw-int-rcv"),
- EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"),
- EV_ALIAS(NULL, NULL)
-};
-
-static struct pmc_event_alias core2_aliases_without_iaf[] = {
- EV_ALIAS("branches", "iap-br-inst-retired.any"),
- EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"),
- EV_ALIAS("cycles", "tsc-tsc"),
- EV_ALIAS("ic-misses", "iap-l1i-misses"),
- EV_ALIAS("instructions", "iap-inst-retired.any_p"),
- EV_ALIAS("interrupts", "iap-hw-int-rcv"),
- EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"),
- EV_ALIAS(NULL, NULL)
-};
-
-#define atom_aliases core2_aliases
-#define atom_aliases_without_iaf core2_aliases_without_iaf
-#define atom_silvermont_aliases core2_aliases
-#define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf
-#define corei7_aliases core2_aliases
-#define corei7_aliases_without_iaf core2_aliases_without_iaf
-#define nehalem_ex_aliases core2_aliases
-#define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf
-#define haswell_aliases core2_aliases
-#define haswell_aliases_without_iaf core2_aliases_without_iaf
-#define haswell_xeon_aliases core2_aliases
-#define haswell_xeon_aliases_without_iaf core2_aliases_without_iaf
-#define broadwell_aliases core2_aliases
-#define broadwell_aliases_without_iaf core2_aliases_without_iaf
-#define broadwell_xeon_aliases core2_aliases
-#define broadwell_xeon_aliases_without_iaf core2_aliases_without_iaf
-#define skylake_aliases core2_aliases
-#define skylake_aliases_without_iaf core2_aliases_without_iaf
-#define skylake_xeon_aliases core2_aliases
-#define skylake_xeon_aliases_without_iaf core2_aliases_without_iaf
-#define ivybridge_aliases core2_aliases
-#define ivybridge_aliases_without_iaf core2_aliases_without_iaf
-#define ivybridge_xeon_aliases core2_aliases
-#define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf
-#define sandybridge_aliases core2_aliases
-#define sandybridge_aliases_without_iaf core2_aliases_without_iaf
-#define sandybridge_xeon_aliases core2_aliases
-#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf
-#define westmere_aliases core2_aliases
-#define westmere_aliases_without_iaf core2_aliases_without_iaf
-#define westmere_ex_aliases core2_aliases
-#define westmere_ex_aliases_without_iaf core2_aliases_without_iaf
-
-#define IAF_KW_OS "os"
-#define IAF_KW_USR "usr"
-#define IAF_KW_ANYTHREAD "anythread"
-
-/*
- * Parse an event specifier for Intel fixed function counters.
- */
-static int
-iaf_allocate_pmc(enum pmc_event pe, char *ctrspec,
- struct pmc_op_pmcallocate *pmc_config)
-{
- char *p;
-
- (void) pe;
-
- pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
- pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0;
-
- while ((p = strsep(&ctrspec, ",")) != NULL) {
- if (KWMATCH(p, IAF_KW_OS))
- pmc_config->pm_caps |= PMC_CAP_SYSTEM;
- else if (KWMATCH(p, IAF_KW_USR))
- pmc_config->pm_caps |= PMC_CAP_USER;
- else if (KWMATCH(p, IAF_KW_ANYTHREAD))
- pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY;
- else
- return (-1);
- }
-
- return (0);
-}
-
-/*
- * Core/Core2 support.
- */
-
-#define IAP_KW_AGENT "agent"
-#define IAP_KW_ANYTHREAD "anythread"
-#define IAP_KW_CACHESTATE "cachestate"
-#define IAP_KW_CMASK "cmask"
-#define IAP_KW_CORE "core"
-#define IAP_KW_EDGE "edge"
-#define IAP_KW_INV "inv"
-#define IAP_KW_OS "os"
-#define IAP_KW_PREFETCH "prefetch"
-#define IAP_KW_SNOOPRESPONSE "snoopresponse"
-#define IAP_KW_SNOOPTYPE "snooptype"
-#define IAP_KW_TRANSITION "trans"
-#define IAP_KW_USR "usr"
-#define IAP_KW_RSP "rsp"
-
-static struct pmc_masks iap_core_mask[] = {
- PMCMASK(all, (0x3 << 14)),
- PMCMASK(this, (0x1 << 14)),
- NULLMASK
-};
-
-static struct pmc_masks iap_agent_mask[] = {
- PMCMASK(this, 0),
- PMCMASK(any, (0x1 << 13)),
- NULLMASK
-};
-
-static struct pmc_masks iap_prefetch_mask[] = {
- PMCMASK(both, (0x3 << 12)),
- PMCMASK(only, (0x1 << 12)),
- PMCMASK(exclude, 0),
- NULLMASK
-};
-
-static struct pmc_masks iap_cachestate_mask[] = {
- PMCMASK(i, (1 << 8)),
- PMCMASK(s, (1 << 9)),
- PMCMASK(e, (1 << 10)),
- PMCMASK(m, (1 << 11)),
- NULLMASK
-};
-
-static struct pmc_masks iap_snoopresponse_mask[] = {
- PMCMASK(clean, (1 << 8)),
- PMCMASK(hit, (1 << 9)),
- PMCMASK(hitm, (1 << 11)),
- NULLMASK
-};
-
-static struct pmc_masks iap_snooptype_mask[] = {
- PMCMASK(cmp2s, (1 << 8)),
- PMCMASK(cmp2i, (1 << 9)),
- NULLMASK
-};
-
-static struct pmc_masks iap_transition_mask[] = {
- PMCMASK(any, 0x00),
- PMCMASK(frequency, 0x10),
- NULLMASK
-};
-
-static struct pmc_masks iap_rsp_mask_i7_wm[] = {
- PMCMASK(DMND_DATA_RD, (1 << 0)),
- PMCMASK(DMND_RFO, (1 << 1)),
- PMCMASK(DMND_IFETCH, (1 << 2)),
- PMCMASK(WB, (1 << 3)),
- PMCMASK(PF_DATA_RD, (1 << 4)),
- PMCMASK(PF_RFO, (1 << 5)),
- PMCMASK(PF_IFETCH, (1 << 6)),
- PMCMASK(OTHER, (1 << 7)),
- PMCMASK(UNCORE_HIT, (1 << 8)),
- PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)),
- PMCMASK(OTHER_CORE_HITM, (1 << 10)),
- PMCMASK(REMOTE_CACHE_FWD, (1 << 12)),
- PMCMASK(REMOTE_DRAM, (1 << 13)),
- PMCMASK(LOCAL_DRAM, (1 << 14)),
- PMCMASK(NON_DRAM, (1 << 15)),
- NULLMASK
-};
-
-static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = {
- PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
- PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
- PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)),
- PMCMASK(REQ_WB, (1ULL << 3)),
- PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)),
- PMCMASK(REQ_PF_RFO, (1ULL << 5)),
- PMCMASK(REQ_PF_IFETCH, (1ULL << 6)),
- PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)),
- PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)),
- PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)),
- PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)),
- PMCMASK(REQ_STRM_ST, (1ULL << 11)),
- PMCMASK(REQ_OTHER, (1ULL << 15)),
- PMCMASK(RES_ANY, (1ULL << 16)),
- PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)),
- PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)),
- PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)),
- PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
- PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)),
- PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)),
- PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)),
- PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
- PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
- PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
- PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
- PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
- PMCMASK(RES_NON_DRAM, (1ULL << 37)),
- NULLMASK
-};
-
-/* Broadwell is defined to use the same mask as Haswell */
-static struct pmc_masks iap_rsp_mask_haswell[] = {
- PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
- PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
- PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)),
- PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)),
- PMCMASK(REQ_PF_RFO, (1ULL << 5)),
- PMCMASK(REQ_PF_IFETCH, (1ULL << 6)),
- PMCMASK(REQ_OTHER, (1ULL << 15)),
- PMCMASK(RES_ANY, (1ULL << 16)),
- PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)),
- PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)),
- PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)),
- PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
- PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)),
- PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)),
- /*
- * For processor type 06_45H 22 is L4_HIT_LOCAL_L4
- * and 23, 24 and 25 are also defined.
- */
- PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)),
- PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
- PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
- PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
- PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
- PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
- PMCMASK(RES_NON_DRAM, (1ULL << 37)),
- NULLMASK
-};
-
-static struct pmc_masks iap_rsp_mask_skylake[] = {
- PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
- PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
- PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)),
- PMCMASK(REQ_PF_DATA_RD, (1ULL << 7)),
- PMCMASK(REQ_PF_RFO, (1ULL << 8)),
- PMCMASK(REQ_STRM_ST, (1ULL << 11)),
- PMCMASK(REQ_OTHER, (1ULL << 15)),
- PMCMASK(RES_ANY, (1ULL << 16)),
- PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)),
- PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)),
- PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)),
- PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
- PMCMASK(RES_SUPPLIER_L4_HIT, (1ULL << 22)),
- PMCMASK(RES_SUPPLIER_DRAM, (1ULL << 26)),
- PMCMASK(RES_SUPPLIER_SPL_HIT, (1ULL << 30)),
- PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)),
- PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
- PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
- PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
- PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
- PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
- PMCMASK(RES_NON_DRAM, (1ULL << 37)),
- NULLMASK
-};
-
-
-static int
-iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
- struct pmc_op_pmcallocate *pmc_config)
-{
- char *e, *p, *q;
- uint64_t cachestate, evmask, rsp;
- int count, n;
-
- pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
- PMC_CAP_QUALIFIER);
- pmc_config->pm_md.pm_iap.pm_iap_config = 0;
-
- cachestate = evmask = rsp = 0;
-
- /* Parse additional modifiers if present */
- while ((p = strsep(&ctrspec, ",")) != NULL) {
-
- n = 0;
- if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) {
- q = strchr(p, '=');
- if (*++q == '\0') /* skip '=' */
- return (-1);
- count = strtol(q, &e, 0);
- if (e == q || *e != '\0')
- return (-1);
- pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
- pmc_config->pm_md.pm_iap.pm_iap_config |=
- IAP_CMASK(count);
- } else if (KWMATCH(p, IAP_KW_EDGE)) {
- pmc_config->pm_caps |= PMC_CAP_EDGE;
- } else if (KWMATCH(p, IAP_KW_INV)) {
- pmc_config->pm_caps |= PMC_CAP_INVERT;
- } else if (KWMATCH(p, IAP_KW_OS)) {
- pmc_config->pm_caps |= PMC_CAP_SYSTEM;
- } else if (KWMATCH(p, IAP_KW_USR)) {
- pmc_config->pm_caps |= PMC_CAP_USER;
- } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) {
- pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY;
- } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) {
- n = pmc_parse_mask(iap_core_mask, p, &evmask);
- if (n != 1)
- return (-1);
- } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) {
- n = pmc_parse_mask(iap_agent_mask, p, &evmask);
- if (n != 1)
- return (-1);
- } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) {
- n = pmc_parse_mask(iap_prefetch_mask, p, &evmask);
- if (n != 1)
- return (-1);
- } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) {
- n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate);
- } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE &&
- KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) {
- n = pmc_parse_mask(iap_transition_mask, p, &evmask);
- if (n != 1)
- return (-1);
- } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) {
- if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) {
- n = pmc_parse_mask(iap_snoopresponse_mask, p,
- &evmask);
- } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) {
- n = pmc_parse_mask(iap_snooptype_mask, p,
- &evmask);
- } else
- return (-1);
- } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_NEHALEM_EX ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE_EX) {
- if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
- n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp);
- } else
- return (-1);
- } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) {
- if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
- n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp);
- } else
- return (-1);
- } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL_XEON) {
- if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
- n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp);
- } else
- return (-1);
- } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_BROADWELL ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_BROADWELL_XEON) {
- /* Broadwell is defined to use same mask as haswell */
- if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
- n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp);
- } else
- return (-1);
-
- } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SKYLAKE ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_SKYLAKE_XEON) {
- if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
- n = pmc_parse_mask(iap_rsp_mask_skylake, p, &rsp);
- } else
- return (-1);
-
- } else
- return (-1);
-
- if (n < 0) /* Parsing failed. */
- return (-1);
- }
-
- pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;
-
- /*
- * If the event requires a 'cachestate' qualifier but was not
- * specified by the user, use a sensible default.
- */
- switch (pe) {
- case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */
- case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */
- case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */
- case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */
- case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */
- case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */
- case PMC_EV_IAP_EVENT_32H: /* Core */
- case PMC_EV_IAP_EVENT_40H: /* Core */
- case PMC_EV_IAP_EVENT_41H: /* Core */
- case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */
- if (cachestate == 0)
- cachestate = (0xF << 8);
- break;
- case PMC_EV_IAP_EVENT_77H: /* Atom */
- /* IAP_EVENT_77H only accepts a cachestate qualifier on the
- * Atom processor
- */
- if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0)
- cachestate = (0xF << 8);
- break;
- default:
- break;
- }
-
- pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate;
- pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp;
-
- return (0);
-}
-
-/*
- * Intel Uncore.
- */
-
-static int
-ucf_allocate_pmc(enum pmc_event pe, char *ctrspec,
- struct pmc_op_pmcallocate *pmc_config)
-{
- (void) pe;
- (void) ctrspec;
-
- pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
- pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0;
-
- return (0);
-}
-
-#define UCP_KW_CMASK "cmask"
-#define UCP_KW_EDGE "edge"
-#define UCP_KW_INV "inv"
-
-static int
-ucp_allocate_pmc(enum pmc_event pe, char *ctrspec,
- struct pmc_op_pmcallocate *pmc_config)
-{
- char *e, *p, *q;
- int count, n;
-
- (void) pe;
-
- pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
- PMC_CAP_QUALIFIER);
- pmc_config->pm_md.pm_ucp.pm_ucp_config = 0;
-
- /* Parse additional modifiers if present */
- while ((p = strsep(&ctrspec, ",")) != NULL) {
-
- n = 0;
- if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) {
- q = strchr(p, '=');
- if (*++q == '\0') /* skip '=' */
- return (-1);
- count = strtol(q, &e, 0);
- if (e == q || *e != '\0')
- return (-1);
- pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
- pmc_config->pm_md.pm_ucp.pm_ucp_config |=
- UCP_CMASK(count);
- } else if (KWMATCH(p, UCP_KW_EDGE)) {
- pmc_config->pm_caps |= PMC_CAP_EDGE;
- } else if (KWMATCH(p, UCP_KW_INV)) {
- pmc_config->pm_caps |= PMC_CAP_INVERT;
- } else
- return (-1);
-
- if (n < 0) /* Parsing failed. */
- return (-1);
- }
-
- return (0);
-}
-
-/*
* AMD K8 PMCs.
*
- * These are very similar to AMD K7 PMCs, but support more kinds of
- * events.
*/
static struct pmc_event_alias k8_aliases[] = {
@@ -1520,962 +716,6 @@ k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
#endif
-#if defined(__amd64__) || defined(__i386__)
-
-/*
- * Intel P4 PMCs
- */
-
-static struct pmc_event_alias p4_aliases[] = {
- EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"),
- EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"),
- EV_ALIAS("cycles", "tsc"),
- EV_ALIAS("instructions",
- "p4-instr-retired,mask=nbogusntag+nbogustag"),
- EV_ALIAS("unhalted-cycles", "p4-global-power-events"),
- EV_ALIAS(NULL, NULL)
-};
-
-#define P4_KW_ACTIVE "active"
-#define P4_KW_ACTIVE_ANY "any"
-#define P4_KW_ACTIVE_BOTH "both"
-#define P4_KW_ACTIVE_NONE "none"
-#define P4_KW_ACTIVE_SINGLE "single"
-#define P4_KW_BUSREQTYPE "busreqtype"
-#define P4_KW_CASCADE "cascade"
-#define P4_KW_EDGE "edge"
-#define P4_KW_INV "complement"
-#define P4_KW_OS "os"
-#define P4_KW_MASK "mask"
-#define P4_KW_PRECISE "precise"
-#define P4_KW_TAG "tag"
-#define P4_KW_THRESHOLD "threshold"
-#define P4_KW_USR "usr"
-
-#define __P4MASK(N,V) PMCMASK(N, (1 << (V)))
-
-static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */
- __P4MASK(dd, 0),
- __P4MASK(db, 1),
- __P4MASK(di, 2),
- __P4MASK(bd, 3),
- __P4MASK(bb, 4),
- __P4MASK(bi, 5),
- __P4MASK(id, 6),
- __P4MASK(ib, 7),
- NULLMASK
-};
-
-static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */
- __P4MASK(tcmiss, 0),
- NULLMASK,
-};
-
-static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */
- __P4MASK(hit, 0),
- __P4MASK(miss, 1),
- __P4MASK(hit-uc, 2),
- NULLMASK
-};
-
-static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */
- __P4MASK(st-rb-full, 2),
- __P4MASK(64k-conf, 3),
- NULLMASK
-};
-
-static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */
- __P4MASK(lsc, 0),
- __P4MASK(ssc, 1),
- NULLMASK
-};
-
-static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */
- __P4MASK(split-ld, 1),
- NULLMASK
-};
-
-static const struct pmc_masks p4_mask_spr[] = { /* store port replay */
- __P4MASK(split-st, 1),
- NULLMASK
-};
-
-static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */
- __P4MASK(no-sta, 1),
- __P4MASK(no-std, 3),
- __P4MASK(partial-data, 4),
- __P4MASK(unalgn-addr, 5),
- NULLMASK
-};
-
-static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */
- __P4MASK(dtmiss, 0),
- __P4MASK(itmiss, 1),
- NULLMASK
-};
-
-static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */
- __P4MASK(rd-2ndl-hits, 0),
- __P4MASK(rd-2ndl-hite, 1),
- __P4MASK(rd-2ndl-hitm, 2),
- __P4MASK(rd-3rdl-hits, 3),
- __P4MASK(rd-3rdl-hite, 4),
- __P4MASK(rd-3rdl-hitm, 5),
- __P4MASK(rd-2ndl-miss, 8),
- __P4MASK(rd-3rdl-miss, 9),
- __P4MASK(wr-2ndl-miss, 10),
- NULLMASK
-};
-
-static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */
- __P4MASK(all-read, 5),
- __P4MASK(all-write, 6),
- __P4MASK(mem-uc, 7),
- __P4MASK(mem-wc, 8),
- __P4MASK(mem-wt, 9),
- __P4MASK(mem-wp, 10),
- __P4MASK(mem-wb, 11),
- __P4MASK(own, 13),
- __P4MASK(other, 14),
- __P4MASK(prefetch, 15),
- NULLMASK
-};
-
-static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */
- __P4MASK(all-read, 5),
- __P4MASK(all-write, 6),
- __P4MASK(mem-uc, 7),
- __P4MASK(mem-wc, 8),
- __P4MASK(mem-wt, 9),
- __P4MASK(mem-wp, 10),
- __P4MASK(mem-wb, 11),
- __P4MASK(own, 13),
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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