svn commit: r331224 - head/sys/dev/ixgbe
Eric Joyner
erj at FreeBSD.org
Mon Mar 19 20:55:08 UTC 2018
Author: erj
Date: Mon Mar 19 20:55:05 2018
New Revision: 331224
URL: https://svnweb.freebsd.org/changeset/base/331224
Log:
ixgbe(4): Update shared code, add support for X552 1G, fix bug
This patch will:
- Update ixgbe shared code
- Add support for Intel(R) Ethernet Connection X552 1000BASE-T
- Add error handling for link state check preventing VF from stopping traffic
after changing PF's MTU value
Submitted by: Krzysztof Galazka <krzysztof.galazka at intel.com>
Reviewed by: Intel Networking
Sponsored by: Intel Corporation
Differential Revision: https://reviews.freebsd.org/D13885
Modified:
head/sys/dev/ixgbe/if_ix.c
head/sys/dev/ixgbe/if_ixv.c
head/sys/dev/ixgbe/ixgbe_82598.c
head/sys/dev/ixgbe/ixgbe_82599.c
head/sys/dev/ixgbe/ixgbe_api.c
head/sys/dev/ixgbe/ixgbe_common.c
head/sys/dev/ixgbe/ixgbe_common.h
head/sys/dev/ixgbe/ixgbe_dcb.c
head/sys/dev/ixgbe/ixgbe_dcb_82598.c
head/sys/dev/ixgbe/ixgbe_dcb_82599.c
head/sys/dev/ixgbe/ixgbe_phy.c
head/sys/dev/ixgbe/ixgbe_type.h
head/sys/dev/ixgbe/ixgbe_vf.c
head/sys/dev/ixgbe/ixgbe_x540.c
head/sys/dev/ixgbe/ixgbe_x550.c
Modified: head/sys/dev/ixgbe/if_ix.c
==============================================================================
--- head/sys/dev/ixgbe/if_ix.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/if_ix.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -47,7 +47,7 @@
/************************************************************************
* Driver version
************************************************************************/
-char ixgbe_driver_version[] = "4.0.0-k";
+char ixgbe_driver_version[] = "4.0.1-k";
/************************************************************************
@@ -92,6 +92,7 @@ static pci_vendor_info_t ixgbe_vendor_info_array[] =
PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
+ PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L, "Intel(R) PRO/10GbE PCI-Express Network Driver"),
Modified: head/sys/dev/ixgbe/if_ixv.c
==============================================================================
--- head/sys/dev/ixgbe/if_ixv.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/if_ixv.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -45,7 +45,7 @@
/************************************************************************
* Driver version
************************************************************************/
-char ixv_driver_version[] = "2.0.0-k";
+char ixv_driver_version[] = "2.0.1-k";
/************************************************************************
* PCI Device ID Table
@@ -616,6 +616,7 @@ ixv_if_init(if_ctx_t ctx)
/* Reset VF and renegotiate mailbox API version */
hw->mac.ops.reset_hw(hw);
+ hw->mac.ops.start_hw(hw);
error = ixv_negotiate_api(adapter);
if (error) {
device_printf(dev,
@@ -909,10 +910,18 @@ ixv_if_update_admin_status(if_ctx_t ctx)
{
struct adapter *adapter = iflib_get_softc(ctx);
device_t dev = iflib_get_dev(ctx);
+ s32 status;
adapter->hw.mac.get_link_status = TRUE;
- ixgbe_check_link(&adapter->hw, &adapter->link_speed, &adapter->link_up,
- FALSE);
+
+ status = ixgbe_check_link(&adapter->hw, &adapter->link_speed,
+ &adapter->link_up, FALSE);
+
+ if (status != IXGBE_SUCCESS && adapter->hw.adapter_stopped == FALSE) {
+ /* Mailbox's Clear To Send status is lost or timeout occurred.
+ * We need reinitialization. */
+ iflib_get_ifp(ctx)->if_init(ctx);
+ }
if (adapter->link_up) {
if (adapter->link_active == FALSE) {
Modified: head/sys/dev/ixgbe/ixgbe_82598.c
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_82598.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_82598.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -550,6 +550,7 @@ out:
/**
* ixgbe_start_mac_link_82598 - Configures MAC link settings
* @hw: pointer to hardware structure
+ * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
*
* Configures link settings based on values in the ixgbe_hw struct.
* Restarts the link. Performs autonegotiation if needed.
@@ -1207,7 +1208,7 @@ s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u
* ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
* @hw: pointer to hardware structure
* @byte_offset: byte offset at address 0xA2
- * @eeprom_data: value read
+ * @sff8472_data: value read
*
* Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
**/
Modified: head/sys/dev/ixgbe/ixgbe_82599.c
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_82599.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_82599.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -270,7 +270,7 @@ s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *l
/**
* prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
* @hw: pointer to hardware structure
- * @reg_val: value to write to AUTOC
+ * @autoc: value to write to AUTOC
* @locked: bool to indicate whether the SW/FW lock was already taken by
* previous proc_autoc_read_82599.
*
@@ -1373,6 +1373,7 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *h
s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
bool cloud_mode)
{
+ UNREFERENCED_1PARAMETER(cloud_mode);
DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
/*
@@ -1461,7 +1462,8 @@ do { \
/**
* ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
- * @stream: input bitstream to compute the hash on
+ * @input: input bitstream to compute the hash on
+ * @common: compressed common input dword
*
* This function is almost identical to the function above but contains
* several optimizations such as unwinding all of the loops, letting the
@@ -1600,7 +1602,7 @@ do { \
/**
* ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
- * @atr_input: input bitstream to compute the hash on
+ * @input: input bitstream to compute the hash on
* @input_mask: mask for the input bitstream
*
* This function serves two main purposes. First it applies the input_mask
@@ -1701,6 +1703,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *h
u32 fdirm = IXGBE_FDIRM_DIPv6;
u32 fdirtcpm;
u32 fdirip6m;
+ UNREFERENCED_1PARAMETER(cloud_mode);
DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
/*
@@ -1877,6 +1880,7 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe
u32 addr_low, addr_high;
u32 cloud_type = 0;
s32 err;
+ UNREFERENCED_1PARAMETER(cloud_mode);
DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
if (!cloud_mode) {
@@ -2001,6 +2005,7 @@ s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe
* @input_mask: mask for the input bitstream
* @soft_id: software index for the filters
* @queue: queue index to direct traffic to
+ * @cloud_mode: unused
*
* Note that the caller to this function must lock before calling, since the
* hardware writes must be protected from one another.
@@ -2011,6 +2016,7 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_h
u16 soft_id, u8 queue, bool cloud_mode)
{
s32 err = IXGBE_ERR_CONFIG;
+ UNREFERENCED_1PARAMETER(cloud_mode);
DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
@@ -2520,6 +2526,7 @@ reset_pipeline_out:
* ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
+ * @dev_addr: address to read from
* @data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface at
@@ -2577,6 +2584,7 @@ release_i2c_access:
* ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to write
+ * @dev_addr: address to read from
* @data: value to write
*
* Performs byte write operation to SFP module's EEPROM over I2C interface at
Modified: head/sys/dev/ixgbe/ixgbe_api.c
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_api.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_api.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -521,6 +521,7 @@ s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw
* ixgbe_read_phy_reg - Read PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read
+ * @device_type: type of device you want to communicate with
* @phy_data: Pointer to read data from PHY register
*
* Reads a value from a specified PHY register
@@ -539,6 +540,7 @@ s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_ad
* ixgbe_write_phy_reg - Write PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit PHY register to write
+ * @device_type: type of device you want to communicate with
* @phy_data: Data to write to the PHY register
*
* Writes a value to specified PHY register
@@ -582,6 +584,8 @@ s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw)
/**
* ixgbe_check_phy_link - Determine link and speed status
* @hw: pointer to hardware structure
+ * @speed: link speed
+ * @link_up: TRUE when link is up
*
* Reads a PHY register to determine if link is up and the current speed for
* the PHY.
@@ -597,6 +601,7 @@ s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_li
* ixgbe_setup_phy_link_speed - Set auto advertise
* @hw: pointer to hardware structure
* @speed: new link speed
+ * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
*
* Sets the auto advertised capabilities
**/
@@ -622,6 +627,9 @@ s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on)
/**
* ixgbe_check_link - Get link and speed status
* @hw: pointer to hardware structure
+ * @speed: pointer to link speed
+ * @link_up: TRUE when link is up
+ * @link_up_wait_to_complete: bool used to wait for link up or not
*
* Reads the links register to determine if link is up and the current speed
**/
@@ -675,6 +683,7 @@ void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
* ixgbe_setup_link - Set link speed
* @hw: pointer to hardware structure
* @speed: new link speed
+ * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
*
* Configures link settings. Restarts the link.
* Performs autonegotiation if needed.
@@ -691,6 +700,7 @@ s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_s
* ixgbe_setup_mac_link - Set link speed
* @hw: pointer to hardware structure
* @speed: new link speed
+ * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
*
* Configures link settings. Restarts the link.
* Performs autonegotiation if needed.
@@ -706,6 +716,8 @@ s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_li
/**
* ixgbe_get_link_capabilities - Returns link capabilities
* @hw: pointer to hardware structure
+ * @speed: link speed capabilities
+ * @autoneg: TRUE when autoneg or autotry is enabled
*
* Determines the link capabilities of the current configuration.
**/
@@ -758,6 +770,7 @@ s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 ind
/**
* ixgbe_blink_led_stop - Stop blinking LEDs
* @hw: pointer to hardware structure
+ * @index: led number to stop
*
* Stop blinking LED based on index.
**/
@@ -1000,6 +1013,7 @@ s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8
* @mc_addr_list: the list of new multicast addresses
* @mc_addr_count: number of addresses
* @func: iterator function to walk the multicast address list
+ * @clear: flag, when set clears the table beforehand
*
* The given list replaces any existing list. Clears the MC addrs from receive
* address registers and the multicast table. Uses unused receive address
@@ -1190,7 +1204,7 @@ s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_e
/**
* ixgbe_set_source_address_pruning - Enable/Disable source address pruning
* @hw: pointer to hardware structure
- * @enbale: enable or disable source address pruning
+ * @enable: enable or disable source address pruning
* @pool: Rx pool - Rx pool to toggle source address pruning
**/
void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
Modified: head/sys/dev/ixgbe/ixgbe_common.c
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_common.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_common.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -2099,6 +2099,7 @@ static void ixgbe_shift_out_eeprom_bits(struct ixgbe_h
/**
* ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
* @hw: pointer to hardware structure
+ * @count: number of bits to shift
**/
static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
{
@@ -2157,7 +2158,7 @@ static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw
/**
* ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
* @hw: pointer to hardware structure
- * @eecd: EECD's current value
+ * @eec: EEC's current value
**/
static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
{
@@ -2537,6 +2538,7 @@ s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
* ixgbe_add_uc_addr - Adds a secondary unicast address.
* @hw: pointer to hardware structure
* @addr: new address
+ * @vmdq: VMDq "set" or "pool" index
*
* Adds it to unused receive address register or goes into promiscuous mode.
**/
@@ -2681,7 +2683,7 @@ static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *m
/**
* ixgbe_set_mta - Set bit-vector in multicast table
* @hw: pointer to hardware structure
- * @hash_value: Multicast address hash value
+ * @mc_addr: Multicast address
*
* Sets the bit-vector in the multicast table.
**/
@@ -3385,6 +3387,7 @@ s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw
/**
* prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
* @hw: pointer to hardware structure
+ * @locked: bool to indicate whether the SW/FW lock was taken
* @reg_val: Value we read from AUTOC
*
* The default case requires no protection so just to the register read.
@@ -3911,7 +3914,10 @@ s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
* ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
* @hw: pointer to hardware structure
* @vlan: VLAN id to write to VLAN filter
+ * @vlvf_bypass: TRUE to find vlanid only, FALSE returns first empty slot if
+ * vlanid not found
*
+ *
* return the VLVF index where this VLAN id should be placed
*
**/
@@ -4253,9 +4259,8 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
case IXGBE_LINKS_SPEED_10_X550EM_A:
*speed = IXGBE_LINK_SPEED_UNKNOWN;
if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
- hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
+ hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
*speed = IXGBE_LINK_SPEED_10_FULL;
- }
break;
default:
*speed = IXGBE_LINK_SPEED_UNKNOWN;
@@ -4583,10 +4588,11 @@ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw,
u32 length, u32 timeout, bool return_data)
{
u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
- u16 dword_len;
+ struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer;
u16 buf_len;
s32 status;
u32 bi;
+ u32 dword_len;
DEBUGFUNC("ixgbe_host_interface_command");
@@ -4616,8 +4622,23 @@ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw,
IXGBE_LE32_TO_CPUS(&buffer[bi]);
}
- /* If there is any thing in data position pull it in */
- buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
+ /*
+ * If there is any thing in data position pull it in
+ * Read Flash command requires reading buffer length from
+ * two byes instead of one byte
+ */
+ if (resp->cmd == 0x30) {
+ for (; bi < dword_len + 2; bi++) {
+ buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
+ bi);
+ IXGBE_LE32_TO_CPUS(&buffer[bi]);
+ }
+ buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
+ & 0xF00) | resp->buf_len;
+ hdr_size += (2 << 2);
+ } else {
+ buf_len = resp->buf_len;
+ }
if (!buf_len)
goto rel_out;
@@ -4649,6 +4670,8 @@ rel_out:
* @min: driver version minor number
* @build: driver version build number
* @sub: driver version sub build number
+ * @len: unused
+ * @driver_ver: unused
*
* Sends driver version number to firmware through the manageability
* block. On success return IXGBE_SUCCESS
@@ -4675,10 +4698,10 @@ s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw,
fw_cmd.ver_build = build;
fw_cmd.ver_sub = sub;
fw_cmd.hdr.checksum = 0;
- fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
- (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
fw_cmd.pad = 0;
fw_cmd.pad2 = 0;
+ fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
+ (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
@@ -5067,8 +5090,119 @@ s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u
return IXGBE_SUCCESS;
}
+/**
+ * ixgbe_get_orom_version - Return option ROM from EEPROM
+ *
+ * @hw: pointer to hardware structure
+ * @nvm_ver: pointer to output structure
+ *
+ * if valid option ROM version, nvm_ver->or_valid set to TRUE
+ * else nvm_ver->or_valid is FALSE.
+ **/
+void ixgbe_get_orom_version(struct ixgbe_hw *hw,
+ struct ixgbe_nvm_version *nvm_ver)
+{
+ u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
+ nvm_ver->or_valid = FALSE;
+ /* Option Rom may or may not be present. Start with pointer */
+ hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
+
+ /* make sure offset is valid */
+ if ((offset == 0x0) || (offset == NVM_INVALID_PTR))
+ return;
+
+ hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
+ hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
+
+ /* option rom exists and is valid */
+ if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 ||
+ eeprom_cfg_blkl == NVM_VER_INVALID ||
+ eeprom_cfg_blkh == NVM_VER_INVALID)
+ return;
+
+ nvm_ver->or_valid = TRUE;
+ nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
+ nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
+ (eeprom_cfg_blkh >> NVM_OROM_SHIFT);
+ nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
+}
+
/**
+ * ixgbe_get_oem_prod_version - Return OEM Product version
+ *
+ * @hw: pointer to hardware structure
+ * @nvm_ver: pointer to output structure
+ *
+ * if valid OEM product version, nvm_ver->oem_valid set to TRUE
+ * else nvm_ver->oem_valid is FALSE.
+ **/
+void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
+ struct ixgbe_nvm_version *nvm_ver)
+{
+ u16 rel_num, prod_ver, mod_len, cap, offset;
+
+ nvm_ver->oem_valid = FALSE;
+ hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
+
+ /* Return is offset to OEM Product Version block is invalid */
+ if (offset == 0x0 && offset == NVM_INVALID_PTR)
+ return;
+
+ /* Read product version block */
+ hw->eeprom.ops.read(hw, offset, &mod_len);
+ hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
+
+ /* Return if OEM product version block is invalid */
+ if (mod_len != NVM_OEM_PROD_VER_MOD_LEN ||
+ (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
+ return;
+
+ hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
+ hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
+
+ /* Return if version is invalid */
+ if ((rel_num | prod_ver) == 0x0 ||
+ rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID)
+ return;
+
+ nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
+ nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
+ nvm_ver->oem_release = rel_num;
+ nvm_ver->oem_valid = TRUE;
+}
+
+/**
+ * ixgbe_get_etk_id - Return Etrack ID from EEPROM
+ *
+ * @hw: pointer to hardware structure
+ * @nvm_ver: pointer to output structure
+ *
+ * word read errors will return 0xFFFF
+ **/
+void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
+{
+ u16 etk_id_l, etk_id_h;
+
+ if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
+ etk_id_l = NVM_VER_INVALID;
+ if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
+ etk_id_h = NVM_VER_INVALID;
+
+ /* The word order for the version format is determined by high order
+ * word bit 15.
+ */
+ if ((etk_id_h & NVM_ETK_VALID) == 0) {
+ nvm_ver->etk_id = etk_id_h;
+ nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
+ } else {
+ nvm_ver->etk_id = etk_id_l;
+ nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
+ }
+}
+
+
+/**
* ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
* @hw: pointer to hardware structure
* @map: pointer to u8 arr for returning map
@@ -5138,8 +5272,8 @@ bool ixgbe_mng_present(struct ixgbe_hw *hw)
return FALSE;
fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
- fwsm &= IXGBE_FWSM_MODE_MASK;
- return fwsm == IXGBE_FWSM_FW_MODE_PT;
+
+ return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
}
/**
Modified: head/sys/dev/ixgbe/ixgbe_common.h
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_common.h Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_common.h Mon Mar 19 20:55:05 2018 (r331224)
@@ -180,6 +180,12 @@ extern void ixgbe_stop_mac_link_on_d3_82599(struct ixg
bool ixgbe_mng_present(struct ixgbe_hw *hw);
bool ixgbe_mng_enabled(struct ixgbe_hw *hw);
+
+void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver);
+void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
+ struct ixgbe_nvm_version *nvm_ver);
+void ixgbe_get_orom_version(struct ixgbe_hw *hw,
+ struct ixgbe_nvm_version *nvm_ver);
void ixgbe_disable_rx_generic(struct ixgbe_hw *hw);
void ixgbe_enable_rx_generic(struct ixgbe_hw *hw);
s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
Modified: head/sys/dev/ixgbe/ixgbe_dcb.c
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_dcb.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_dcb.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -45,6 +45,10 @@
* are the smallest unit programmable into the underlying
* hardware. The IEEE 802.1Qaz specification do not use bandwidth
* groups so this is much simplified from the CEE case.
+ * @bw: bandwidth index by traffic class
+ * @refill: refill credits index by traffic class
+ * @max: max credits by traffic class
+ * @max_frame_size: maximum frame size
*/
s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max,
int max_frame_size)
@@ -79,8 +83,10 @@ s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill
/**
* ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits
- * @ixgbe_dcb_config: Struct containing DCB settings.
- * @direction: Configuring either Tx or Rx.
+ * @hw: pointer to hardware structure
+ * @dcb_config: Struct containing DCB settings
+ * @max_frame_size: Maximum frame size
+ * @direction: Configuring either Tx or Rx
*
* This function calculates the credits allocated to each traffic class.
* It should be called only after the rules are checked by
Modified: head/sys/dev/ixgbe/ixgbe_dcb_82598.c
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_dcb_82598.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_dcb_82598.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -112,7 +112,9 @@ s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
/**
* ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
* @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @refill: refill credits index by traffic class
+ * @max: max credits index by traffic class
+ * @tsa: transmission selection algorithm indexed by traffic class
*
* Configure Rx Data Arbiter and credits for each traffic class.
*/
@@ -167,7 +169,10 @@ s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw
/**
* ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
* @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @refill: refill credits index by traffic class
+ * @max: max credits index by traffic class
+ * @bwg_id: bandwidth grouping indexed by traffic class
+ * @tsa: transmission selection algorithm indexed by traffic class
*
* Configure Tx Descriptor Arbiter and credits for each traffic class.
*/
@@ -211,7 +216,10 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgb
/**
* ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
* @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @refill: refill credits index by traffic class
+ * @max: max credits index by traffic class
+ * @bwg_id: bandwidth grouping indexed by traffic class
+ * @tsa: transmission selection algorithm indexed by traffic class
*
* Configure Tx Data Arbiter and credits for each traffic class.
*/
@@ -256,7 +264,7 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgb
/**
* ixgbe_dcb_config_pfc_82598 - Config priority flow control
* @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @pfc_en: enabled pfc bitmask
*
* Configure Priority Flow Control for each traffic class.
*/
@@ -340,7 +348,11 @@ s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *h
/**
* ixgbe_dcb_hw_config_82598 - Config and enable DCB
* @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @link_speed: unused
+ * @refill: refill credits index by traffic class
+ * @max: max credits index by traffic class
+ * @bwg_id: bandwidth grouping indexed by traffic class
+ * @tsa: transmission selection algorithm indexed by traffic class
*
* Configure dcb settings and enable dcb mode.
*/
Modified: head/sys/dev/ixgbe/ixgbe_dcb_82599.c
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_dcb_82599.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_dcb_82599.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -111,7 +111,11 @@ s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,
/**
* ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
* @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @refill: refill credits index by traffic class
+ * @max: max credits index by traffic class
+ * @bwg_id: bandwidth grouping indexed by traffic class
+ * @tsa: transmission selection algorithm indexed by traffic class
+ * @map: priority to tc assignments indexed by priority
*
* Configure Rx Packet Arbiter and credits for each traffic class.
*/
@@ -170,7 +174,10 @@ s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw
/**
* ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
* @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @refill: refill credits index by traffic class
+ * @max: max credits index by traffic class
+ * @bwg_id: bandwidth grouping indexed by traffic class
+ * @tsa: transmission selection algorithm indexed by traffic class
*
* Configure Tx Descriptor Arbiter and credits for each traffic class.
*/
@@ -215,7 +222,11 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgb
/**
* ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
* @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @refill: refill credits index by traffic class
+ * @max: max credits index by traffic class
+ * @bwg_id: bandwidth grouping indexed by traffic class
+ * @tsa: transmission selection algorithm indexed by traffic class
+ * @map: priority to tc assignments indexed by priority
*
* Configure Tx Packet Arbiter and credits for each traffic class.
*/
@@ -363,6 +374,7 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8
/**
* ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
* @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
*
* Configure queue statistics registers, all queues belonging to same traffic
* class uses a single set of queue statistics counters.
@@ -573,7 +585,12 @@ s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw,
/**
* ixgbe_dcb_hw_config_82599 - Configure and enable DCB
* @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @link_speed: unused
+ * @refill: refill credits index by traffic class
+ * @max: max credits index by traffic class
+ * @bwg_id: bandwidth grouping indexed by traffic class
+ * @tsa: transmission selection algorithm indexed by traffic class
+ * @map: priority to tc assignments indexed by priority
*
* Configure dcb settings and enable dcb mode.
*/
Modified: head/sys/dev/ixgbe/ixgbe_phy.c
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_phy.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_phy.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -88,8 +88,8 @@ static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw,
/**
* ixgbe_ones_comp_byte_add - Perform one's complement addition
- * @add1 - addend 1
- * @add2 - addend 2
+ * @add1: addend 1
+ * @add2: addend 2
*
* Returns one's complement 8-bit sum.
*/
@@ -400,6 +400,7 @@ s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
/**
* ixgbe_validate_phy_addr - Determines phy address is valid
* @hw: pointer to hardware structure
+ * @phy_addr: PHY address
*
**/
bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
@@ -577,6 +578,7 @@ out:
* the SWFW lock
* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read
+ * @device_type: 5 bit device type
* @phy_data: Pointer to read data from PHY register
**/
s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
@@ -658,6 +660,7 @@ s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 re
* using the SWFW lock - this function is needed in most cases
* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read
+ * @device_type: 5 bit device type
* @phy_data: Pointer to read data from PHY register
**/
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
@@ -874,6 +877,7 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
* ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
* @hw: pointer to hardware structure
* @speed: new link speed
+ * @autoneg_wait_to_complete: unused
**/
s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
ixgbe_link_speed speed,
@@ -979,6 +983,8 @@ s32 ixgbe_get_copper_link_capabilities_generic(struct
/**
* ixgbe_check_phy_link_tnx - Determine link and speed status
* @hw: pointer to hardware structure
+ * @speed: current link speed
+ * @link_up: TRUE is link is up, FALSE otherwise
*
* Reads the VS1 register to determine if link is up and the current speed for
* the PHY.
@@ -1934,7 +1940,7 @@ s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw,
* ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
* @hw: pointer to hardware structure
* @byte_offset: byte offset at address 0xA2
- * @eeprom_data: value read
+ * @sff8472_data: value read
*
* Performs byte read operation to SFP module's SFF-8472 data over I2C
**/
@@ -1983,6 +1989,7 @@ static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8
* ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
+ * @dev_addr: address to read from
* @data: value read
* @lock: TRUE if to take and release semaphore
*
@@ -2074,6 +2081,7 @@ fail:
* ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
+ * @dev_addr: address to read from
* @data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface at
@@ -2090,6 +2098,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u
* ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
+ * @dev_addr: address to read from
* @data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface at
@@ -2106,6 +2115,7 @@ s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_
* ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to write
+ * @dev_addr: address to write to
* @data: value to write
* @lock: TRUE if to take and release semaphore
*
@@ -2177,6 +2187,7 @@ fail:
* ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to write
+ * @dev_addr: address to write to
* @data: value to write
*
* Performs byte write operation to SFP module's EEPROM over I2C interface at
@@ -2193,6 +2204,7 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw,
* ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to write
+ * @dev_addr: address to write to
* @data: value to write
*
* Performs byte write operation to SFP module's EEPROM over I2C interface at
@@ -2575,6 +2587,7 @@ static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u3
{
u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
bool data;
+ UNREFERENCED_1PARAMETER(hw);
DEBUGFUNC("ixgbe_get_i2c_data");
Modified: head/sys/dev/ixgbe/ixgbe_type.h
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_type.h Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_type.h Mon Mar 19 20:55:05 2018 (r331224)
@@ -274,7 +274,6 @@
#define IXGBE_I2C_BB_EN_X550 0x00000100
#define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550
#define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550
-
#define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN)
#define IXGBE_I2C_CLK_OE_N_EN 0
@@ -286,6 +285,47 @@
#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
+
+#define NVM_OROM_OFFSET 0x17
+#define NVM_OROM_BLK_LOW 0x83
+#define NVM_OROM_BLK_HI 0x84
+#define NVM_OROM_PATCH_MASK 0xFF
+#define NVM_OROM_SHIFT 8
+
+#define NVM_VER_MASK 0x00FF /* version mask */
+#define NVM_VER_SHIFT 8 /* version bit shift */
+#define NVM_OEM_PROD_VER_PTR 0x1B /* OEM Product version block pointer */
+#define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */
+#define NVM_OEM_PROD_VER_OFF_L 0x2 /* OEM Product version offset low */
+#define NVM_OEM_PROD_VER_OFF_H 0x3 /* OEM Product version offset high */
+#define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */
+#define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */
+#define NVM_ETK_OFF_LOW 0x2D /* version low order word */
+#define NVM_ETK_OFF_HI 0x2E /* version high order word */
+#define NVM_ETK_SHIFT 16 /* high version word shift */
+#define NVM_VER_INVALID 0xFFFF
+#define NVM_ETK_VALID 0x8000
+#define NVM_INVALID_PTR 0xFFFF
+#define NVM_VER_SIZE 32 /* version sting size */
+
+struct ixgbe_nvm_version {
+ u32 etk_id;
+ u8 nvm_major;
+ u16 nvm_minor;
+ u8 nvm_id;
+
+ bool oem_valid;
+ u8 oem_major;
+ u8 oem_minor;
+ u16 oem_release;
+
+ bool or_valid;
+ u8 or_major;
+ u16 or_build;
+ u8 or_patch;
+
+};
+
/* Interrupt Registers */
#define IXGBE_EICR 0x00800
#define IXGBE_EICS 0x00808
@@ -553,7 +593,6 @@
#define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff /* VXLAN port */
#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000 /* GENEVE port */
#define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff /* GENEVE/VXLAN */
-
#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16
#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
@@ -563,7 +602,6 @@
/* Four Flexible Filters are supported */
#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
-
/* Six Flexible Filters are supported */
#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6
/* Eight Flexible Filters are supported */
@@ -711,8 +749,6 @@ struct ixgbe_dmac_config {
#define IXGBE_EEE_RX_LPI_STATUS 0x40000000 /* RX Link in LPI status */
#define IXGBE_EEE_TX_LPI_STATUS 0x80000000 /* TX Link in LPI status */
-
-
/* Security Control Registers */
#define IXGBE_SECTXCTRL 0x08800
#define IXGBE_SECTXSTAT 0x08804
@@ -850,7 +886,6 @@ struct ixgbe_dmac_config {
#define IXGBE_RTTBCNRTT 0x05150
#define IXGBE_RTTBCNRD 0x0498C
-
/* FCoE DMA Context Registers */
/* FCoE Direct DMA Context */
#define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
@@ -4274,7 +4309,6 @@ struct ixgbe_bypass_eeprom {
#define BYPASS_LOG_EVENT_SHIFT 28
#define BYPASS_LOG_CLEAR_SHIFT 24 /* bit offset */
-
#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
#define IXGBE_FUSES0_300MHZ (1 << 5)
Modified: head/sys/dev/ixgbe/ixgbe_vf.c
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_vf.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_vf.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -376,6 +376,7 @@ s32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u
* @mc_addr_list: array of multicast addresses to program
* @mc_addr_count: number of multicast addresses to program
* @next: caller supplied function to return next address in list
+ * @clear: unused
*
* Updates the Multicast Table Array.
**/
@@ -509,8 +510,9 @@ u32 ixgbe_get_num_of_rx_queues_vf(struct ixgbe_hw *hw)
}
/**
- * ixgbe_get_mac_addr_vf - Read device MAC address
- * @hw: pointer to the HW structure
+ * ixgbe_get_mac_addr_vf - Read device MAC address
+ * @hw: pointer to the HW structure
+ * @mac_addr: the MAC address
**/
s32 ixgbe_get_mac_addr_vf(struct ixgbe_hw *hw, u8 *mac_addr)
{
@@ -556,7 +558,6 @@ s32 ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, u32 in
* ixgbe_setup_mac_link_vf - Setup MAC link settings
* @hw: pointer to hardware structure
* @speed: new link speed
- * @autoneg: TRUE if autonegotiation enabled
* @autoneg_wait_to_complete: TRUE when waiting for completion is needed
*
* Set the link speed in the AUTOC register and restarts link.
Modified: head/sys/dev/ixgbe/ixgbe_x540.c
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_x540.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_x540.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -785,6 +785,9 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw,
swmask |= swi2c_mask;
fwmask |= swi2c_mask << 2;
+ if (hw->mac.type >= ixgbe_mac_X550)
+ timeout = 1000;
+
for (i = 0; i < timeout; i++) {
/* SW NVM semaphore bit is used for access to all
* SW_FW_SYNC bits (not just NVM)
Modified: head/sys/dev/ixgbe/ixgbe_x550.c
==============================================================================
--- head/sys/dev/ixgbe/ixgbe_x550.c Mon Mar 19 20:19:00 2018 (r331223)
+++ head/sys/dev/ixgbe/ixgbe_x550.c Mon Mar 19 20:55:05 2018 (r331224)
@@ -337,98 +337,6 @@ static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
}
/**
- * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit address of PHY register to read
- * @dev_type: always unused
- * @phy_data: Pointer to read data from PHY register
- */
-static s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
- u32 dev_type, u16 *phy_data)
-{
- u32 i, data, command;
- UNREFERENCED_1PARAMETER(dev_type);
-
- /* Setup and write the read command */
- command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
- (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
- IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
- IXGBE_MSCA_MDI_COMMAND;
-
- IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
-
- /* Check every 10 usec to see if the access completed.
- * The MDI Command bit will clear when the operation is
- * complete
- */
- for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
- usec_delay(10);
-
- command = IXGBE_READ_REG(hw, IXGBE_MSCA);
- if (!(command & IXGBE_MSCA_MDI_COMMAND))
- break;
- }
-
- if (command & IXGBE_MSCA_MDI_COMMAND) {
- ERROR_REPORT1(IXGBE_ERROR_POLLING,
- "PHY read command did not complete.\n");
- return IXGBE_ERR_PHY;
- }
-
- /* Read operation is complete. Get the data from MSRWD */
- data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
- data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
- *phy_data = (u16)data;
-
- return IXGBE_SUCCESS;
-}
-
-/**
- * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit PHY register to write
- * @dev_type: always unused
- * @phy_data: Data to write to the PHY register
- */
-static s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
- u32 dev_type, u16 phy_data)
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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