svn commit: r332780 - head/sys/dev/nvme

[Warner Losh]

Author: imp
Date: Thu Apr 19 15:39:20 2018
New Revision: 332780
URL: https://svnweb.freebsd.org/changeset/base/332780

Log:
  Intel drives have an optimal alignment for I/O. While they honor I/Os
  that cross this boundary, they perform better when this isn't the
  case. Intel uses the 3rd byte in the vendor specific area for
  this. The DC P3500 was previously listed without any explanation. Add
  the DC P3520 and DC P4500 to the list.
  
  There won't be any others drives needing this quirk. Intel has
  standardized a field in the namespace data in 1.3 (noiob).  A future
  patch will use that if it exists, with fallback to this method.
  
  Submitted by: Keith Busch
  Reviewed by: jimharris@

Modified:
  head/sys/dev/nvme/nvme_ns.c

Modified: head/sys/dev/nvme/nvme_ns.c
==============================================================================
--- head/sys/dev/nvme/nvme_ns.c	Thu Apr 19 15:29:10 2018	(r332779)
+++ head/sys/dev/nvme/nvme_ns.c	Thu Apr 19 15:39:20 2018	(r332780)
@@ -505,9 +505,23 @@ nvme_ns_construct(struct nvme_namespace *ns, uint32_t 
 	ns->id = id;
 	ns->stripesize = 0;
 
-	if (pci_get_devid(ctrlr->dev) == 0x09538086 && ctrlr->cdata.vs[3] != 0)
-		ns->stripesize =
-		    (1 << ctrlr->cdata.vs[3]) * ctrlr->min_page_size;
+	/*
+	 * Some Intel devices advertise an alignment that improves performance,
+	 * but is in it's vendor specific space in the cdata. Use it for these
+	 * drives, if present, to suggest a stripe size.  Future versions of
+	 * Intel hardware will use fields standardized in NVMe 1.3 for this.
+	 */
+	switch (pci_get_devid(ctrlr->dev)) {
+	case 0x09538086:		/* Intel DC PC3500 */
+	case 0x0a538086:		/* Intel DC PC3520 */
+	case 0x0a548086:		/* Intel DC PC4500 */
+		if (ctrlr->cdata.vs[3] != 0)
+			ns->stripesize =
+			    (1 << ctrlr->cdata.vs[3]) * ctrlr->min_page_size;
+		break;
+	default:
+		break;
+	}
 
 	/*
 	 * Namespaces are reconstructed after a controller reset, so check