svn commit: r323610 - in head/sys/arm64: arm64 include
Andrew Turner
andrew at FreeBSD.org
Fri Sep 15 12:57:35 UTC 2017
Author: andrew
Date: Fri Sep 15 12:57:34 2017
New Revision: 323610
URL: https://svnweb.freebsd.org/changeset/base/323610
Log:
Add the ARMv8.3 ID register fields. These were found in the A-Profile
exploration tools documentation:
https://developer.arm.com/products/architecture/a-profile/exploration-tools
Sponsored by: DARPA, AFRL
Modified:
head/sys/arm64/arm64/identcpu.c
head/sys/arm64/include/armreg.h
Modified: head/sys/arm64/arm64/identcpu.c
==============================================================================
--- head/sys/arm64/arm64/identcpu.c Fri Sep 15 09:03:01 2017 (r323609)
+++ head/sys/arm64/arm64/identcpu.c Fri Sep 15 12:57:34 2017 (r323610)
@@ -282,6 +282,9 @@ print_cpu_features(u_int cpu)
case ID_AA64ISAR0_SHA2_BASE:
printf("%sSHA2", SEP_STR);
break;
+ case ID_AA64ISAR0_SHA2_512:
+ printf("%sSHA2+SHA512", SEP_STR);
+ break;
default:
printf("%sUnknown SHA2", SEP_STR);
break;
@@ -298,6 +301,50 @@ print_cpu_features(u_int cpu)
break;
}
+ switch (ID_AA64ISAR0_SHA3(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_SHA3_NONE:
+ break;
+ case ID_AA64ISAR0_SHA3_IMPL:
+ printf("%sSHA3", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown SHA3", SEP_STR);
+ break;
+ }
+
+ switch (ID_AA64ISAR0_SM3(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_SM3_NONE:
+ break;
+ case ID_AA64ISAR0_SM3_IMPL:
+ printf("%sSM3", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown SM3", SEP_STR);
+ break;
+ }
+
+ switch (ID_AA64ISAR0_SM4(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_SM4_NONE:
+ break;
+ case ID_AA64ISAR0_SM4_IMPL:
+ printf("%sSM4", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown SM4", SEP_STR);
+ break;
+ }
+
+ switch (ID_AA64ISAR0_DP(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_DP_NONE:
+ break;
+ case ID_AA64ISAR0_DP_IMPL:
+ printf("%sDotProd", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown DP", SEP_STR);
+ break;
+ }
+
if ((cpu_desc[cpu].id_aa64isar0 & ~ID_AA64ISAR0_MASK) != 0)
printf("%s%#lx", SEP_STR,
cpu_desc[cpu].id_aa64isar0 & ~ID_AA64ISAR0_MASK);
@@ -310,6 +357,83 @@ print_cpu_features(u_int cpu)
printed = 0;
printf(" Instruction Set Attributes 1 = <");
+ switch (ID_AA64ISAR1_GPI(cpu_desc[cpu].id_aa64isar1)) {
+ case ID_AA64ISAR1_GPI_NONE:
+ break;
+ case ID_AA64ISAR1_GPI_IMPL:
+ printf("%sImpl GenericAuth", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown GenericAuth", SEP_STR);
+ break;
+ }
+
+ switch (ID_AA64ISAR1_GPA(cpu_desc[cpu].id_aa64isar1)) {
+ case ID_AA64ISAR1_GPA_NONE:
+ break;
+ case ID_AA64ISAR1_GPA_IMPL:
+ printf("%sPrince GenericAuth", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown GenericAuth", SEP_STR);
+ break;
+ }
+
+ switch (ID_AA64ISAR1_LRCPC(cpu_desc[cpu].id_aa64isar1)) {
+ case ID_AA64ISAR1_LRCPC_NONE:
+ break;
+ case ID_AA64ISAR1_LRCPC_IMPL:
+ printf("%sRCpc", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown RCpc", SEP_STR);
+ break;
+ }
+
+ switch (ID_AA64ISAR1_FCMA(cpu_desc[cpu].id_aa64isar1)) {
+ case ID_AA64ISAR1_FCMA_NONE:
+ break;
+ case ID_AA64ISAR1_FCMA_IMPL:
+ printf("%sFCMA", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown FCMA", SEP_STR);
+ break;
+ }
+
+ switch (ID_AA64ISAR1_JSCVT(cpu_desc[cpu].id_aa64isar1)) {
+ case ID_AA64ISAR1_JSCVT_NONE:
+ break;
+ case ID_AA64ISAR1_JSCVT_IMPL:
+ printf("%sJS Conv", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown JS Conv", SEP_STR);
+ break;
+ }
+
+ switch (ID_AA64ISAR1_API(cpu_desc[cpu].id_aa64isar1)) {
+ case ID_AA64ISAR1_API_NONE:
+ break;
+ case ID_AA64ISAR1_API_IMPL:
+ printf("%sImpl AddrAuth", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown Impl AddrAuth", SEP_STR);
+ break;
+ }
+
+ switch (ID_AA64ISAR1_APA(cpu_desc[cpu].id_aa64isar1)) {
+ case ID_AA64ISAR1_APA_NONE:
+ break;
+ case ID_AA64ISAR1_APA_IMPL:
+ printf("%sPrince AddrAuth", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown Prince AddrAuth", SEP_STR);
+ break;
+ }
+
switch (ID_AA64ISAR1_DPB(cpu_desc[cpu].id_aa64isar1)) {
case ID_AA64ISAR1_DPB_NONE:
break;
@@ -687,6 +811,29 @@ print_cpu_features(u_int cpu)
if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR2) != 0) {
printed = 0;
printf(" Memory Model Features 2 = <");
+
+ switch (ID_AA64MMFR2_NV(cpu_desc[cpu].id_aa64mmfr2)) {
+ case ID_AA64MMFR2_NV_NONE:
+ break;
+ case ID_AA64MMFR2_NV_IMPL:
+ printf("%sNestedVirt", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown NestedVirt", SEP_STR);
+ break;
+ }
+
+ switch (ID_AA64MMFR2_CCIDX(cpu_desc[cpu].id_aa64mmfr2)) {
+ case ID_AA64MMFR2_CCIDX_32:
+ printf("%s32b CCIDX", SEP_STR);
+ break;
+ case ID_AA64MMFR2_CCIDX_64:
+ printf("%s64b CCIDX", SEP_STR);
+ break;
+ default:
+ printf("%sUnknown CCIDX", SEP_STR);
+ break;
+ }
switch (ID_AA64MMFR2_VA_RANGE(cpu_desc[cpu].id_aa64mmfr2)) {
case ID_AA64MMFR2_VA_RANGE_48:
Modified: head/sys/arm64/include/armreg.h
==============================================================================
--- head/sys/arm64/include/armreg.h Fri Sep 15 09:03:01 2017 (r323609)
+++ head/sys/arm64/include/armreg.h Fri Sep 15 12:57:34 2017 (r323610)
@@ -205,7 +205,7 @@
#define ID_AA64DFR0_PMS_VER_V1 (0x1ul << ID_AA64DFR0_PMS_VER_SHIFT)
/* ID_AA64ISAR0_EL1 */
-#define ID_AA64ISAR0_MASK 0xf0fffff0
+#define ID_AA64ISAR0_MASK 0x0000fffff0fffff0ul
#define ID_AA64ISAR0_AES_SHIFT 4
#define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK)
@@ -222,6 +222,7 @@
#define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK)
#define ID_AA64ISAR0_SHA2_NONE (0x0 << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT)
+#define ID_AA64ISAR0_SHA2_512 (0x2 << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_CRC32_SHIFT 16
#define ID_AA64ISAR0_CRC32_MASK (0xf << ID_AA64ISAR0_CRC32_SHIFT)
#define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK)
@@ -237,14 +238,69 @@
#define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK)
#define ID_AA64ISAR0_RDM_NONE (0x0 << ID_AA64ISAR0_RDM_SHIFT)
#define ID_AA64ISAR0_RDM_IMPL (0x1 << ID_AA64ISAR0_RDM_SHIFT)
+#define ID_AA64ISAR0_SHA3_SHIFT 32
+#define ID_AA64ISAR0_SHA3_MASK (0xful << ID_AA64ISAR0_SHA3_SHIFT)
+#define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK)
+#define ID_AA64ISAR0_SHA3_NONE (0x0ul << ID_AA64ISAR0_SHA3_SHIFT)
+#define ID_AA64ISAR0_SHA3_IMPL (0x1ul << ID_AA64ISAR0_SHA3_SHIFT)
+#define ID_AA64ISAR0_SM3_SHIFT 36
+#define ID_AA64ISAR0_SM3_MASK (0xful << ID_AA64ISAR0_SM3_SHIFT)
+#define ID_AA64ISAR0_SM3(x) ((x) & ID_AA64ISAR0_SM3_MASK)
+#define ID_AA64ISAR0_SM3_NONE (0x0ul << ID_AA64ISAR0_SM3_SHIFT)
+#define ID_AA64ISAR0_SM3_IMPL (0x1ul << ID_AA64ISAR0_SM3_SHIFT)
+#define ID_AA64ISAR0_SM4_SHIFT 40
+#define ID_AA64ISAR0_SM4_MASK (0xful << ID_AA64ISAR0_SM4_SHIFT)
+#define ID_AA64ISAR0_SM4(x) ((x) & ID_AA64ISAR0_SM4_MASK)
+#define ID_AA64ISAR0_SM4_NONE (0x0ul << ID_AA64ISAR0_SM4_SHIFT)
+#define ID_AA64ISAR0_SM4_IMPL (0x1ul << ID_AA64ISAR0_SM4_SHIFT)
+#define ID_AA64ISAR0_DP_SHIFT 48
+#define ID_AA64ISAR0_DP_MASK (0xful << ID_AA64ISAR0_DP_SHIFT)
+#define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK)
+#define ID_AA64ISAR0_DP_NONE (0x0ul << ID_AA64ISAR0_DP_SHIFT)
+#define ID_AA64ISAR0_DP_IMPL (0x1ul << ID_AA64ISAR0_DP_SHIFT)
/* ID_AA64ISAR1_EL1 */
-#define ID_AA64ISAR1_MASK 0x0000000f
+#define ID_AA64ISAR1_MASK 0xffffffff
#define ID_AA64ISAR1_DPB_SHIFT 0
#define ID_AA64ISAR1_DPB_MASK (0xf << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK)
#define ID_AA64ISAR1_DPB_NONE (0x0 << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB_IMPL (0x1 << ID_AA64ISAR1_DPB_SHIFT)
+#define ID_AA64ISAR1_APA_SHIFT 4
+#define ID_AA64ISAR1_APA_MASK (0xf << ID_AA64ISAR1_APA_SHIFT)
+#define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK)
+#define ID_AA64ISAR1_APA_NONE (0x0 << ID_AA64ISAR1_APA_SHIFT)
+#define ID_AA64ISAR1_APA_IMPL (0x1 << ID_AA64ISAR1_APA_SHIFT)
+#define ID_AA64ISAR1_API_SHIFT 8
+#define ID_AA64ISAR1_API_MASK (0xf << ID_AA64ISAR1_API_SHIFT)
+#define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK)
+#define ID_AA64ISAR1_API_NONE (0x0 << ID_AA64ISAR1_API_SHIFT)
+#define ID_AA64ISAR1_API_IMPL (0x1 << ID_AA64ISAR1_API_SHIFT)
+#define ID_AA64ISAR1_JSCVT_SHIFT 12
+#define ID_AA64ISAR1_JSCVT_MASK (0xf << ID_AA64ISAR1_JSCVT_SHIFT)
+#define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK)
+#define ID_AA64ISAR1_JSCVT_NONE (0x0 << ID_AA64ISAR1_JSCVT_SHIFT)
+#define ID_AA64ISAR1_JSCVT_IMPL (0x1 << ID_AA64ISAR1_JSCVT_SHIFT)
+#define ID_AA64ISAR1_FCMA_SHIFT 16
+#define ID_AA64ISAR1_FCMA_MASK (0xf << ID_AA64ISAR1_FCMA_SHIFT)
+#define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK)
+#define ID_AA64ISAR1_FCMA_NONE (0x0 << ID_AA64ISAR1_FCMA_SHIFT)
+#define ID_AA64ISAR1_FCMA_IMPL (0x1 << ID_AA64ISAR1_FCMA_SHIFT)
+#define ID_AA64ISAR1_LRCPC_SHIFT 20
+#define ID_AA64ISAR1_LRCPC_MASK (0xf << ID_AA64ISAR1_LRCPC_SHIFT)
+#define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK)
+#define ID_AA64ISAR1_LRCPC_NONE (0x0 << ID_AA64ISAR1_LRCPC_SHIFT)
+#define ID_AA64ISAR1_LRCPC_IMPL (0x1 << ID_AA64ISAR1_LRCPC_SHIFT)
+#define ID_AA64ISAR1_GPA_SHIFT 24
+#define ID_AA64ISAR1_GPA_MASK (0xf << ID_AA64ISAR1_GPA_SHIFT)
+#define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK)
+#define ID_AA64ISAR1_GPA_NONE (0x0 << ID_AA64ISAR1_GPA_SHIFT)
+#define ID_AA64ISAR1_GPA_IMPL (0x1 << ID_AA64ISAR1_GPA_SHIFT)
+#define ID_AA64ISAR1_GPI_SHIFT 28
+#define ID_AA64ISAR1_GPI_MASK (0xf << ID_AA64ISAR1_GPI_SHIFT)
+#define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK)
+#define ID_AA64ISAR1_GPI_NONE (0x0 << ID_AA64ISAR1_GPI_SHIFT)
+#define ID_AA64ISAR1_GPI_IMPL (0x1 << ID_AA64ISAR1_GPI_SHIFT)
/* ID_AA64MMFR0_EL1 */
#define ID_AA64MMFR0_MASK 0xffffffff
@@ -342,7 +398,7 @@
/* ID_AA64MMFR2_EL1 */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
-#define ID_AA64MMFR2_MASK 0x000fffff
+#define ID_AA64MMFR2_MASK 0x0fffffff
#define ID_AA64MMFR2_CNP_SHIFT 0
#define ID_AA64MMFR2_CNP_MASK (0xf << ID_AA64MMFR2_CNP_SHIFT)
#define ID_AA64MMFR2_CNP(x) ((x) & ID_AA64MMFR2_CNP_MASK)
@@ -368,6 +424,16 @@
#define ID_AA64MMFR2_VA_RANGE(x) ((x) & ID_AA64MMFR2_VA_RANGE_MASK)
#define ID_AA64MMFR2_VA_RANGE_48 (0x0 << ID_AA64MMFR2_VA_RANGE_SHIFT)
#define ID_AA64MMFR2_VA_RANGE_52 (0x1 << ID_AA64MMFR2_VA_RANGE_SHIFT)
+#define ID_AA64MMFR2_CCIDX_SHIFT 20
+#define ID_AA64MMFR2_CCIDX_MASK (0xf << ID_AA64MMFR2_CCIDX_SHIFT)
+#define ID_AA64MMFR2_CCIDX(x) ((x) & ID_AA64MMFR2_CCIDX_MASK)
+#define ID_AA64MMFR2_CCIDX_32 (0x0 << ID_AA64MMFR2_CCIDX_SHIFT)
+#define ID_AA64MMFR2_CCIDX_64 (0x1 << ID_AA64MMFR2_CCIDX_SHIFT)
+#define ID_AA64MMFR2_NV_SHIFT 24
+#define ID_AA64MMFR2_NV_MASK (0xf << ID_AA64MMFR2_NV_SHIFT)
+#define ID_AA64MMFR2_NV(x) ((x) & ID_AA64MMFR2_NV_MASK)
+#define ID_AA64MMFR2_NV_NONE (0x0 << ID_AA64MMFR2_NV_SHIFT)
+#define ID_AA64MMFR2_NV_IMPL (0x1 << ID_AA64MMFR2_NV_SHIFT)
/* ID_AA64PFR0_EL1 */
#define ID_AA64PFR0_MASK 0x0000000ffffffffful
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