svn commit: r324207 - head/sys/arm64/arm64

[Mark Millard]

> Author: andrew
> Date: Mon Oct  2 14:22:35 2017
> New Revision: 324207
> URL: 
> https://svnweb.freebsd.org/changeset/base/324207
> 
> 
> Log:
>   Add a memory barrier to ensure the atomic write is visible to the other
>   CPUs before waking them up.
>   
>   Sponsored by:	DARPA, AFRL
> 
> Modified:
>   head/sys/arm64/arm64/mp_machdep.c
> 
> Modified: head/sys/arm64/arm64/mp_machdep.c
> ==============================================================================
> --- head/sys/arm64/arm64/mp_machdep.c	Mon Oct  2 14:19:31 2017	(r324206)
> +++ head/sys/arm64/arm64/mp_machdep.c	Mon Oct  2 14:22:35 2017	(r324207)
> @@ -236,7 +236,10 @@ release_aps(void *dummy __unused)
>  
>  	atomic_store_rel_int(&aps_ready, 1);
>  	/* Wake up the other CPUs */
> -	__asm __volatile("sev");
> +	__asm __volatile(
> +	    "dsb ishst	\n"
> +	    "sev	\n"
> +	    ::: "memory");
>  
>  	printf("Release APs\n");


There is another sev instruction without a prior memory barrier:

Index: /usr/src/sys/arm64/arm64/identcpu.c
===================================================================
--- /usr/src/sys/arm64/arm64/identcpu.c	(revision 323676)
+++ /usr/src/sys/arm64/arm64/identcpu.c	(working copy)
@@ -1109,6 +1109,9 @@
 
 		/* Wake up the other CPUs */
 		atomic_store_rel_int(&ident_lock, 0);
-		__asm __volatile("sev" ::: "memory");
+		__asm __volatile(
+			"dsb ish	\n"
+			"sev		\n"
+			::: "memory");
 	}
 }

(No claim that the dsb form is optimal. Arm documentation says
that they recommend every sev be preceded by a dsb and I picked
ish to experiment with.)

See comments and extra attachment in bugzilla 222234
(which you have fixed with your change).

[Specifically your change should make non-debug kernels
boot Pine64+ 2GB's again. (I had used just "dsb ish"
get get such to boot.)]



===
Mark Millard
markmi at dsl-only.net