svn commit: r316989 - head/contrib/llvm/lib/Target/X86

[Dimitry Andric]

Author: dim
Date: Sat Apr 15 22:34:22 2017
New Revision: 316989
URL: https://svnweb.freebsd.org/changeset/base/316989

Log:
  Pull in r300404 from upstream llvm trunk (by me):
  
    Use correct registers for "A" inline asm constraint
  
    Summary:
    In PR32594, inline assembly using the 'A' constraint on x86_64 causes
    llvm to crash with a "Cannot select" stack trace.  This is because
    `X86TargetLowering::getRegForInlineAsmConstraint` hardcodes that 'A'
    means the EAX and EDX registers.
  
    However, on x86_64 it means the RAX and RDX registers, and on 16-bit
    x86 (ia16?) it means the old AX and DX registers.
  
    Add new register classes in `X86RegisterInfo.td` to support these
    cases, and amend the logic in `getRegForInlineAsmConstraint` to cope
    with different subtargets.  Also add a test case, derived from
    PR32594.
  
    Reviewers: craig.topper, qcolombet, RKSimon, ab
  
    Reviewed By: ab
  
    Subscribers: ab, emaste, royger, llvm-commits
  
    Differential Revision: https://reviews.llvm.org/D31902
  
  This should fix crashes when using the 'A' constraint on amd64, for
  example as it is being used in Xen.
  
  Reported by:	royger
  MFC after:	3 days

Modified:
  head/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
  head/contrib/llvm/lib/Target/X86/X86RegisterInfo.td

Modified: head/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp	Sat Apr 15 21:33:44 2017	(r316988)
+++ head/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp	Sat Apr 15 22:34:22 2017	(r316989)
@@ -34717,10 +34717,20 @@ X86TargetLowering::getRegForInlineAsmCon
       return Res;
     }
 
-    // 'A' means EAX + EDX.
+    // 'A' means [ER]AX + [ER]DX.
     if (Constraint == "A") {
-      Res.first = X86::EAX;
-      Res.second = &X86::GR32_ADRegClass;
+      if (Subtarget.is64Bit()) {
+        Res.first = X86::RAX;
+        Res.second = &X86::GR64_ADRegClass;
+      } else if (Subtarget.is32Bit()) {
+        Res.first = X86::EAX;
+        Res.second = &X86::GR32_ADRegClass;
+      } else if (Subtarget.is16Bit()) {
+        Res.first = X86::AX;
+        Res.second = &X86::GR16_ADRegClass;
+      } else {
+        llvm_unreachable("Expecting 64, 32 or 16 bit subtarget");
+      }
       return Res;
     }
     return Res;

Modified: head/contrib/llvm/lib/Target/X86/X86RegisterInfo.td
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86RegisterInfo.td	Sat Apr 15 21:33:44 2017	(r316988)
+++ head/contrib/llvm/lib/Target/X86/X86RegisterInfo.td	Sat Apr 15 22:34:22 2017	(r316989)
@@ -437,8 +437,10 @@ def LOW32_ADDR_ACCESS : RegisterClass<"X
 def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
                                           (add LOW32_ADDR_ACCESS, RBP)>;
 
-// A class to support the 'A' assembler constraint: EAX then EDX.
+// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
+def GR16_AD : RegisterClass<"X86", [i16], 16, (add AX, DX)>;
 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
+def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
 
 // Scalar SSE2 floating point registers.
 def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;