svn commit: r296825 - in head/sys: arm/conf arm/mv arm/mv/armada38x boot/fdt/dts/arm

[Andrew Turner]

On Mon, 14 Mar 2016 07:05:41 +0000 (UTC)
Wojciech Macek <wma at FreeBSD.org> wrote:

> Author: wma
> Date: Mon Mar 14 07:05:41 2016
> New Revision: 296825
> URL: https://svnweb.freebsd.org/changeset/base/296825
> 
> Log:
>   Make MPIC compatible with ARM_INTRNG
>   
>   After ARM_INTRNG introduction, MPIC code needed several
> modifications:
>   - IRQ resource and its handler added
>   -  several DEVMETHODs of INTRNG interface implemented
>   -  defines enhanced to ensure code compiles as well for AXP as for
> A38X
>   - added dummy MSI_IRQ, ERR_IRQ defines for Armada38x
>   - MPIC driver was added to files.armada38x, ARM_INTRNG option
> enabled in kernconf file and regs of MPIC corrected in dts file.
>   
>   Instead of modifying Armada38X DTS, offsets to CPU registers
> defined in driver were changed. That required restoring 'reg'
> property of mpic node in ArmadaXP to state compliant with Linux DTS.
>   
>   Additionally, required ARM_INTRNG definitions were added to
> mv_common.c. 
>   Submitted by:          Bartosz Szczepanek <bsz at semihalf.com>
>   Obtained from:         Semihalf
>   Sponsored by:          Stormshield
>   Reviewed by:           adrian, andrew, ian, skra
>   Approved by:           cognet (mentor)
>   Differential Revision: https://reviews.freebsd.org/D5030
> 
> Modified:
>   head/sys/arm/conf/ARMADA38X
>   head/sys/arm/mv/armada38x/files.armada38x
>   head/sys/arm/mv/mpic.c
>   head/sys/arm/mv/mvreg.h
>   head/sys/boot/fdt/dts/arm/db78460.dts
> 
> Modified: head/sys/arm/conf/ARMADA38X
> ==============================================================================
> --- head/sys/arm/conf/ARMADA38X	Mon Mar 14 06:30:37
> 2016	(r296824) +++ head/sys/arm/conf/ARMADA38X	Mon Mar
> 14 07:05:41 2016	(r296825) @@ -23,6 +23,7 @@ options
> SCHED_ULE		# ULE scheduler #options
> SCHED_4BSD		# 4BSD scheduler 
>  options 	SMP
> +options 	ARM_INTRNG

This file already had ARM_INTRNG set. It now has it twice.

Andrew