svn commit: r302834 - head/sys/amd64/amd64

[Andriy Gapon]

Author: avg
Date: Thu Jul 14 11:03:05 2016
New Revision: 302834
URL: https://svnweb.freebsd.org/changeset/base/302834

Log:
  fix-up for configuration of AMD Family 10h processors borrowed from Linux
  
  http://lxr.free-electrons.com/source/arch/x86/kernel/cpu/amd.c#L643
  BIOS may configure Family 10h processors to convert WC+ cache type
  to CD.  That can hurt performance of guest VMs using nested paging.
  
  Reviewed by:	kib
  MFC after:	3 weeks
  Differential Revision: https://reviews.freebsd.org/D6059

Modified:
  head/sys/amd64/amd64/initcpu.c

Modified: head/sys/amd64/amd64/initcpu.c
==============================================================================
--- head/sys/amd64/amd64/initcpu.c	Thu Jul 14 09:47:49 2016	(r302833)
+++ head/sys/amd64/amd64/initcpu.c	Thu Jul 14 11:03:05 2016	(r302834)
@@ -94,6 +94,20 @@ init_amd(void)
 			wrmsr(MSR_NB_CFG1, msr);
 		}
 	}
+
+	/*
+	 * BIOS may configure Family 10h processors to convert WC+ cache type
+	 * to CD.  That can hurt performance of guest VMs using nested paging.
+	 * The relevant MSR bit is not documented in the BKDG,
+	 * the fix is borrowed from Linux.
+	 */
+	if (CPUID_TO_FAMILY(cpu_id) == 0x10) {
+		if ((cpu_feature2 & CPUID2_HV) == 0) {
+			msr = rdmsr(0xc001102a);
+			msr &= ~((uint64_t)1 << 24);
+			wrmsr(0xc001102a, msr);
+		}
+	}
 }
 
 /*
@@ -179,6 +193,7 @@ initializecpu(void)
 void
 initializecpucache(void)
 {
+	uint64_t msr;
 
 	/*
 	 * CPUID with %eax = 1, %ebx returns