svn commit: r302528 - in head/sys: arm/allwinner arm/allwinner/clk arm/nvidia arm/nvidia/tegra124 dev/dwc dev/extres/clk dev/extres/hwreset dev/extres/phy dev/extres/regulator dev/iicbus/twsi dev/u...
Michal Meloun
mmel at FreeBSD.org
Sun Jul 10 18:28:21 UTC 2016
Author: mmel
Date: Sun Jul 10 18:28:15 2016
New Revision: 302528
URL: https://svnweb.freebsd.org/changeset/base/302528
Log:
EXTRES: Add OF node as argument to all <foo>_get_by_ofw_<bar>() functions.
In some cases, the driver must handle given properties located in
specific OF subnode. Instead of creating duplicate set of function, add
'node' as argument to existing functions, defaulting it to device OF node.
MFC after: 3 weeks
Modified:
head/sys/arm/allwinner/a10_ahci.c
head/sys/arm/allwinner/a10_codec.c
head/sys/arm/allwinner/a10_dmac.c
head/sys/arm/allwinner/a10_ehci.c
head/sys/arm/allwinner/a10_fb.c
head/sys/arm/allwinner/a10_gpio.c
head/sys/arm/allwinner/a10_hdmi.c
head/sys/arm/allwinner/a10_mmc.c
head/sys/arm/allwinner/aw_if_dwc.c
head/sys/arm/allwinner/aw_rsb.c
head/sys/arm/allwinner/aw_usbphy.c
head/sys/arm/allwinner/clk/aw_ahbclk.c
head/sys/arm/allwinner/clk/aw_apbclk.c
head/sys/arm/allwinner/clk/aw_axiclk.c
head/sys/arm/allwinner/clk/aw_codecclk.c
head/sys/arm/allwinner/clk/aw_cpuclk.c
head/sys/arm/allwinner/clk/aw_cpusclk.c
head/sys/arm/allwinner/clk/aw_debeclk.c
head/sys/arm/allwinner/clk/aw_gate.c
head/sys/arm/allwinner/clk/aw_gmacclk.c
head/sys/arm/allwinner/clk/aw_hdmiclk.c
head/sys/arm/allwinner/clk/aw_lcdclk.c
head/sys/arm/allwinner/clk/aw_mmcclk.c
head/sys/arm/allwinner/clk/aw_modclk.c
head/sys/arm/allwinner/clk/aw_pll.c
head/sys/arm/allwinner/clk/aw_usbclk.c
head/sys/arm/allwinner/if_awg.c
head/sys/arm/allwinner/if_emac.c
head/sys/arm/nvidia/tegra124/tegra124_cpufreq.c
head/sys/arm/nvidia/tegra124/tegra124_pmc.c
head/sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
head/sys/arm/nvidia/tegra_ahci.c
head/sys/arm/nvidia/tegra_efuse.c
head/sys/arm/nvidia/tegra_ehci.c
head/sys/arm/nvidia/tegra_i2c.c
head/sys/arm/nvidia/tegra_pcie.c
head/sys/arm/nvidia/tegra_rtc.c
head/sys/arm/nvidia/tegra_sdhci.c
head/sys/arm/nvidia/tegra_soctherm.c
head/sys/arm/nvidia/tegra_uart.c
head/sys/arm/nvidia/tegra_usbphy.c
head/sys/dev/dwc/if_dwc.c
head/sys/dev/extres/clk/clk.c
head/sys/dev/extres/clk/clk.h
head/sys/dev/extres/clk/clk_fixed.c
head/sys/dev/extres/hwreset/hwreset.c
head/sys/dev/extres/hwreset/hwreset.h
head/sys/dev/extres/phy/phy.c
head/sys/dev/extres/phy/phy.h
head/sys/dev/extres/regulator/regulator.c
head/sys/dev/extres/regulator/regulator.h
head/sys/dev/iicbus/twsi/a10_twsi.c
head/sys/dev/uart/uart_dev_snps.c
head/sys/dev/usb/controller/generic_ohci.c
Modified: head/sys/arm/allwinner/a10_ahci.c
==============================================================================
--- head/sys/arm/allwinner/a10_ahci.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/a10_ahci.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -313,12 +313,12 @@ ahci_a10_attach(device_t dev)
return (ENXIO);
/* Enable clocks */
- error = clk_get_by_ofw_index(dev, 0, &clk_pll);
+ error = clk_get_by_ofw_index(dev, 0, 0, &clk_pll);
if (error != 0) {
device_printf(dev, "Cannot get PLL clock\n");
goto fail;
}
- error = clk_get_by_ofw_index(dev, 1, &clk_gate);
+ error = clk_get_by_ofw_index(dev, 0, 1, &clk_gate);
if (error != 0) {
device_printf(dev, "Cannot get gate clock\n");
goto fail;
Modified: head/sys/arm/allwinner/a10_codec.c
==============================================================================
--- head/sys/arm/allwinner/a10_codec.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/a10_codec.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -786,12 +786,12 @@ a10codec_attach(device_t dev)
}
/* Get clocks */
- error = clk_get_by_ofw_name(dev, "apb", &clk_apb);
+ error = clk_get_by_ofw_name(dev, 0, "apb", &clk_apb);
if (error != 0) {
device_printf(dev, "cannot find apb clock\n");
goto fail;
}
- error = clk_get_by_ofw_name(dev, "codec", &clk_codec);
+ error = clk_get_by_ofw_name(dev, 0, "codec", &clk_codec);
if (error != 0) {
device_printf(dev, "cannot find codec clock\n");
goto fail;
Modified: head/sys/arm/allwinner/a10_dmac.c
==============================================================================
--- head/sys/arm/allwinner/a10_dmac.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/a10_dmac.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -124,7 +124,7 @@ a10dmac_attach(device_t dev)
mtx_init(&sc->sc_mtx, "a10 dmac", NULL, MTX_SPIN);
/* Activate DMA controller clock */
- error = clk_get_by_ofw_index(dev, 0, &clk);
+ error = clk_get_by_ofw_index(dev, 0, 0, &clk);
if (error != 0) {
device_printf(dev, "cannot get clock\n");
return (error);
Modified: head/sys/arm/allwinner/a10_ehci.c
==============================================================================
--- head/sys/arm/allwinner/a10_ehci.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/a10_ehci.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -208,7 +208,7 @@ a10_ehci_attach(device_t self)
sc->sc_flags |= EHCI_SCFLG_DONTRESET;
/* De-assert reset */
- if (hwreset_get_by_ofw_idx(self, 0, &aw_sc->rst) == 0) {
+ if (hwreset_get_by_ofw_idx(self, 0, 0, &aw_sc->rst) == 0) {
err = hwreset_deassert(aw_sc->rst);
if (err != 0) {
device_printf(self, "Could not de-assert reset\n");
@@ -217,7 +217,7 @@ a10_ehci_attach(device_t self)
}
/* Enable clock for USB */
- err = clk_get_by_ofw_index(self, 0, &aw_sc->clk);
+ err = clk_get_by_ofw_index(self, 0, 0, &aw_sc->clk);
if (err != 0) {
device_printf(self, "Could not get clock\n");
goto error;
@@ -229,7 +229,7 @@ a10_ehci_attach(device_t self)
}
/* Enable USB PHY */
- err = phy_get_by_ofw_name(self, "usb", &aw_sc->phy);
+ err = phy_get_by_ofw_name(self, 0, "usb", &aw_sc->phy);
if (err != 0) {
device_printf(self, "Could not get phy\n");
goto error;
Modified: head/sys/arm/allwinner/a10_fb.c
==============================================================================
--- head/sys/arm/allwinner/a10_fb.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/a10_fb.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -209,7 +209,7 @@ a10fb_setup_debe(struct a10fb_softc *sc,
height = mode->vdisplay << interlace;
/* Leave reset */
- error = hwreset_get_by_ofw_name(sc->dev, "de_be", &rst);
+ error = hwreset_get_by_ofw_name(sc->dev, 0, "de_be", &rst);
if (error != 0) {
device_printf(sc->dev, "cannot find reset 'de_be'\n");
return (error);
@@ -220,7 +220,7 @@ a10fb_setup_debe(struct a10fb_softc *sc,
return (error);
}
/* Gating AHB clock for BE */
- error = clk_get_by_ofw_name(sc->dev, "ahb_de_be", &clk_ahb);
+ error = clk_get_by_ofw_name(sc->dev, 0, "ahb_de_be", &clk_ahb);
if (error != 0) {
device_printf(sc->dev, "cannot find clk 'ahb_de_be'\n");
return (error);
@@ -231,7 +231,7 @@ a10fb_setup_debe(struct a10fb_softc *sc,
return (error);
}
/* Enable DRAM clock to BE */
- error = clk_get_by_ofw_name(sc->dev, "dram_de_be", &clk_dram);
+ error = clk_get_by_ofw_name(sc->dev, 0, "dram_de_be", &clk_dram);
if (error != 0) {
device_printf(sc->dev, "cannot find clk 'dram_de_be'\n");
return (error);
@@ -242,7 +242,7 @@ a10fb_setup_debe(struct a10fb_softc *sc,
return (error);
}
/* Set BE clock to 300MHz and enable */
- error = clk_get_by_ofw_name(sc->dev, "de_be", &clk_debe);
+ error = clk_get_by_ofw_name(sc->dev, 0, "de_be", &clk_debe);
if (error != 0) {
device_printf(sc->dev, "cannot find clk 'de_be'\n");
return (error);
@@ -309,12 +309,12 @@ a10fb_setup_pll(struct a10fb_softc *sc,
clk_t clk_sclk1, clk_sclk2;
int error;
- error = clk_get_by_ofw_name(sc->dev, "lcd_ch1_sclk1", &clk_sclk1);
+ error = clk_get_by_ofw_name(sc->dev, 0, "lcd_ch1_sclk1", &clk_sclk1);
if (error != 0) {
device_printf(sc->dev, "cannot find clk 'lcd_ch1_sclk1'\n");
return (error);
}
- error = clk_get_by_ofw_name(sc->dev, "lcd_ch1_sclk2", &clk_sclk2);
+ error = clk_get_by_ofw_name(sc->dev, 0, "lcd_ch1_sclk2", &clk_sclk2);
if (error != 0) {
device_printf(sc->dev, "cannot find clk 'lcd_ch1_sclk2'\n");
return (error);
@@ -360,7 +360,7 @@ a10fb_setup_tcon(struct a10fb_softc *sc,
start_delay = START_DELAY(vbl);
/* Leave reset */
- error = hwreset_get_by_ofw_name(sc->dev, "lcd", &rst);
+ error = hwreset_get_by_ofw_name(sc->dev, 0, "lcd", &rst);
if (error != 0) {
device_printf(sc->dev, "cannot find reset 'lcd'\n");
return (error);
@@ -371,7 +371,7 @@ a10fb_setup_tcon(struct a10fb_softc *sc,
return (error);
}
/* Gating AHB clock for LCD */
- error = clk_get_by_ofw_name(sc->dev, "ahb_lcd", &clk_ahb);
+ error = clk_get_by_ofw_name(sc->dev, 0, "ahb_lcd", &clk_ahb);
if (error != 0) {
device_printf(sc->dev, "cannot find clk 'ahb_lcd'\n");
return (error);
Modified: head/sys/arm/allwinner/a10_gpio.c
==============================================================================
--- head/sys/arm/allwinner/a10_gpio.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/a10_gpio.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -619,7 +619,7 @@ a10_gpio_attach(device_t dev)
sc->padconf = (struct allwinner_padconf *)ofw_bus_search_compatible(dev,
compat_data)->ocd_data;
- if (hwreset_get_by_ofw_idx(dev, 0, &rst) == 0) {
+ if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
error = hwreset_deassert(rst);
if (error != 0) {
device_printf(dev, "cannot de-assert reset\n");
@@ -627,7 +627,7 @@ a10_gpio_attach(device_t dev)
}
}
- if (clk_get_by_ofw_index(dev, 0, &clk) == 0) {
+ if (clk_get_by_ofw_index(dev, 0, 0, &clk) == 0) {
error = clk_enable(clk);
if (error != 0) {
device_printf(dev, "could not enable clock\n");
Modified: head/sys/arm/allwinner/a10_hdmi.c
==============================================================================
--- head/sys/arm/allwinner/a10_hdmi.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/a10_hdmi.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -293,17 +293,17 @@ a10hdmi_attach(device_t dev)
}
/* Setup clocks */
- error = clk_get_by_ofw_name(dev, "ahb", &sc->clk_ahb);
+ error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->clk_ahb);
if (error != 0) {
device_printf(dev, "cannot find ahb clock\n");
return (error);
}
- error = clk_get_by_ofw_name(dev, "hdmi", &sc->clk_hdmi);
+ error = clk_get_by_ofw_name(dev, 0, "hdmi", &sc->clk_hdmi);
if (error != 0) {
device_printf(dev, "cannot find hdmi clock\n");
return (error);
}
- error = clk_get_by_ofw_name(dev, "lcd", &sc->clk_lcd);
+ error = clk_get_by_ofw_name(dev, 0, "lcd", &sc->clk_lcd);
if (error != 0) {
device_printf(dev, "cannot find lcd clock\n");
}
Modified: head/sys/arm/allwinner/a10_mmc.c
==============================================================================
--- head/sys/arm/allwinner/a10_mmc.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/a10_mmc.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -198,7 +198,7 @@ a10_mmc_attach(device_t dev)
}
/* De-assert reset */
- if (hwreset_get_by_ofw_name(dev, "ahb", &sc->a10_rst_ahb) == 0) {
+ if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->a10_rst_ahb) == 0) {
error = hwreset_deassert(sc->a10_rst_ahb);
if (error != 0) {
device_printf(dev, "cannot de-assert reset\n");
@@ -207,7 +207,7 @@ a10_mmc_attach(device_t dev)
}
/* Activate the module clock. */
- error = clk_get_by_ofw_name(dev, "ahb", &sc->a10_clk_ahb);
+ error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->a10_clk_ahb);
if (error != 0) {
device_printf(dev, "cannot get ahb clock\n");
goto fail;
@@ -217,7 +217,7 @@ a10_mmc_attach(device_t dev)
device_printf(dev, "cannot enable ahb clock\n");
goto fail;
}
- error = clk_get_by_ofw_name(dev, "mmc", &sc->a10_clk_mmc);
+ error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->a10_clk_mmc);
if (error != 0) {
device_printf(dev, "cannot get mmc clock\n");
goto fail;
Modified: head/sys/arm/allwinner/aw_if_dwc.c
==============================================================================
--- head/sys/arm/allwinner/aw_if_dwc.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/aw_if_dwc.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -73,7 +73,7 @@ a20_if_dwc_init(device_t dev)
/* Configure PHY for MII or RGMII mode */
if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type)) {
- error = clk_get_by_ofw_name(dev, "allwinner_gmac_tx", &clk_tx);
+ error = clk_get_by_ofw_name(dev, 0, "allwinner_gmac_tx", &clk_tx);
if (error != 0) {
device_printf(dev, "could not get tx clk\n");
return (error);
@@ -99,7 +99,7 @@ a20_if_dwc_init(device_t dev)
}
/* Enable PHY regulator if applicable */
- if (regulator_get_by_ofw_property(dev, "phy-supply", ®) == 0) {
+ if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) {
error = regulator_enable(reg);
if (error != 0) {
device_printf(dev, "could not enable PHY regulator\n");
Modified: head/sys/arm/allwinner/aw_rsb.c
==============================================================================
--- head/sys/arm/allwinner/aw_rsb.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/aw_rsb.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -395,14 +395,14 @@ rsb_attach(device_t dev)
sc = device_get_softc(dev);
mtx_init(&sc->mtx, device_get_nameunit(dev), "rsb", MTX_DEF);
- if (clk_get_by_ofw_index(dev, 0, &sc->clk) == 0) {
+ if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) == 0) {
error = clk_enable(sc->clk);
if (error != 0) {
device_printf(dev, "cannot enable clock\n");
goto fail;
}
}
- if (hwreset_get_by_ofw_idx(dev, 0, &sc->rst) == 0) {
+ if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst) == 0) {
error = hwreset_deassert(sc->rst);
if (error != 0) {
device_printf(dev, "cannot de-assert reset\n");
Modified: head/sys/arm/allwinner/aw_usbphy.c
==============================================================================
--- head/sys/arm/allwinner/aw_usbphy.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/aw_usbphy.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -87,7 +87,7 @@ awusbphy_init(device_t dev)
node = ofw_bus_get_node(dev);
/* Enable clocks */
- for (off = 0; clk_get_by_ofw_index(dev, off, &clk) == 0; off++) {
+ for (off = 0; clk_get_by_ofw_index(dev, 0, off, &clk) == 0; off++) {
error = clk_enable(clk);
if (error != 0) {
device_printf(dev, "couldn't enable clock %s\n",
@@ -97,7 +97,7 @@ awusbphy_init(device_t dev)
}
/* De-assert resets */
- for (off = 0; hwreset_get_by_ofw_idx(dev, off, &rst) == 0; off++) {
+ for (off = 0; hwreset_get_by_ofw_idx(dev, 0, off, &rst) == 0; off++) {
error = hwreset_deassert(rst);
if (error != 0) {
device_printf(dev, "couldn't de-assert reset %d\n",
@@ -109,7 +109,7 @@ awusbphy_init(device_t dev)
/* Get regulators */
for (off = 0; off < USBPHY_NPHYS; off++) {
snprintf(pname, sizeof(pname), "usb%d_vbus-supply", off);
- if (regulator_get_by_ofw_property(dev, pname, ®) == 0)
+ if (regulator_get_by_ofw_property(dev, 0, pname, ®) == 0)
sc->reg[off] = reg;
}
Modified: head/sys/arm/allwinner/clk/aw_ahbclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_ahbclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_ahbclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -315,7 +315,7 @@ aw_ahbclk_attach(device_t dev)
def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP,
M_WAITOK);
for (i = 0; i < ncells; i++) {
- error = clk_get_by_ofw_index(dev, i, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot get clock %d\n", i);
goto fail;
Modified: head/sys/arm/allwinner/clk/aw_apbclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_apbclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_apbclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -248,7 +248,7 @@ aw_apbclk_attach(device_t dev)
def.id = 1;
def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
for (i = 0; i < ncells; i++) {
- error = clk_get_by_ofw_index(dev, i, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot get clock %d\n", i);
goto fail;
Modified: head/sys/arm/allwinner/clk/aw_axiclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_axiclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_axiclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -135,7 +135,7 @@ aw_axiclk_attach(device_t dev)
clkdom = clkdom_create(dev);
- error = clk_get_by_ofw_index(dev, 0, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, 0, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot parse clock parent\n");
return (ENXIO);
Modified: head/sys/arm/allwinner/clk/aw_codecclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_codecclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_codecclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -120,7 +120,7 @@ aw_codecclk_attach(device_t dev)
goto fail;
}
- error = clk_get_by_ofw_index(dev, 0, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, 0, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot parse clock parent\n");
return (ENXIO);
Modified: head/sys/arm/allwinner/clk/aw_cpuclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_cpuclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_cpuclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -95,7 +95,7 @@ aw_cpuclk_attach(device_t dev)
def.clkdef.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP,
M_WAITOK);
for (i = 0; i < ncells; i++) {
- error = clk_get_by_ofw_index(dev, i, &clk);
+ error = clk_get_by_ofw_index(dev, 0, i, &clk);
if (error != 0) {
device_printf(dev, "cannot get clock %d\n", i);
goto fail;
Modified: head/sys/arm/allwinner/clk/aw_cpusclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_cpusclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_cpusclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -255,7 +255,7 @@ aw_cpusclk_attach(device_t dev)
def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP,
M_WAITOK);
for (i = 0; i < ncells; i++) {
- error = clk_get_by_ofw_index(dev, i, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot get clock %d\n", i);
goto fail;
Modified: head/sys/arm/allwinner/clk/aw_debeclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_debeclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_debeclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -287,7 +287,7 @@ aw_debeclk_attach(device_t dev)
def.id = 1;
def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
for (i = 0; i < ncells; i++) {
- error = clk_get_by_ofw_index(dev, i, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot get clock %d\n", i);
goto fail;
Modified: head/sys/arm/allwinner/clk/aw_gate.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_gate.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_gate.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -168,7 +168,7 @@ aw_gate_attach(device_t dev)
goto fail;
}
- error = clk_get_by_ofw_index(dev, 0, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, 0, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot parse clock parent\n");
return (ENXIO);
Modified: head/sys/arm/allwinner/clk/aw_gmacclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_gmacclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_gmacclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -240,7 +240,7 @@ aw_gmacclk_attach(device_t dev)
def.id = 1;
def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
for (i = 0; i < ncells; i++) {
- error = clk_get_by_ofw_index(dev, i, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot get clock %d\n", error);
goto fail;
Modified: head/sys/arm/allwinner/clk/aw_hdmiclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_hdmiclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_hdmiclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -249,7 +249,7 @@ aw_hdmiclk_attach(device_t dev)
clkdom = clkdom_create(dev);
- error = clk_get_by_ofw_index(dev, 0, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, 0, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot parse clock parent\n");
return (ENXIO);
Modified: head/sys/arm/allwinner/clk/aw_lcdclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_lcdclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_lcdclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -493,7 +493,7 @@ aw_lcdclk_attach(device_t dev)
parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
for (i = 0; i < ncells; i++) {
- error = clk_get_by_ofw_index(dev, i, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot get clock %d\n", i);
goto fail;
Modified: head/sys/arm/allwinner/clk/aw_mmcclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_mmcclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_mmcclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -292,7 +292,7 @@ aw_mmcclk_attach(device_t dev)
def.id = 0;
def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
for (i = 0; i < ncells; i++) {
- error = clk_get_by_ofw_index(dev, i, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot get clock %d\n", i);
goto fail;
Modified: head/sys/arm/allwinner/clk/aw_modclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_modclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_modclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -260,7 +260,7 @@ aw_modclk_attach(device_t dev)
def.id = 1;
def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
for (i = 0; i < ncells; i++) {
- error = clk_get_by_ofw_index(dev, i, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot get clock %d\n", i);
goto fail;
Modified: head/sys/arm/allwinner/clk/aw_pll.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_pll.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_pll.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -856,7 +856,7 @@ aw_pll_attach(device_t dev)
goto fail;
}
- if (clk_get_by_ofw_index(dev, 0, &clk_parent) != 0)
+ if (clk_get_by_ofw_index(dev, 0, 0, &clk_parent) != 0)
clk_parent = NULL;
for (index = 0; index < nout; index++) {
Modified: head/sys/arm/allwinner/clk/aw_usbclk.c
==============================================================================
--- head/sys/arm/allwinner/clk/aw_usbclk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/clk/aw_usbclk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -202,13 +202,13 @@ aw_usbclk_attach(device_t dev)
else if (indices == NULL && type == AW_H3_USBCLK)
indices = aw_usbclk_indices_h3;
- error = clk_get_by_ofw_index(dev, 0, &clk_parent);
+ error = clk_get_by_ofw_index(dev, 0, 0, &clk_parent);
if (error != 0) {
device_printf(dev, "cannot parse clock parent\n");
return (ENXIO);
}
if (type == AW_A83T_USBCLK) {
- error = clk_get_by_ofw_index(dev, 1, &clk_parent_pll);
+ error = clk_get_by_ofw_index(dev, 0, 1, &clk_parent_pll);
if (error != 0) {
device_printf(dev, "cannot parse pll clock parent\n");
return (ENXIO);
Modified: head/sys/arm/allwinner/if_awg.c
==============================================================================
--- head/sys/arm/allwinner/if_awg.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/if_awg.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -931,12 +931,12 @@ awg_setup_extres(device_t dev)
phy_type = NULL;
/* Get AHB clock and reset resources */
- error = hwreset_get_by_ofw_name(dev, "ahb", &rst_ahb);
+ error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb);
if (error != 0) {
device_printf(dev, "cannot get ahb reset\n");
goto fail;
}
- error = clk_get_by_ofw_name(dev, "ahb", &clk_ahb);
+ error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb);
if (error != 0) {
device_printf(dev, "cannot get ahb clock\n");
goto fail;
@@ -954,7 +954,7 @@ awg_setup_extres(device_t dev)
OF_prop_free(phy_type);
/* Get the TX clock */
- error = clk_get_by_ofw_name(dev, "tx", &clk_tx);
+ error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx);
if (error != 0) {
device_printf(dev, "cannot get tx clock\n");
goto fail;
@@ -998,7 +998,7 @@ awg_setup_extres(device_t dev)
}
/* Enable PHY regulator if applicable */
- if (regulator_get_by_ofw_property(dev, "phy-supply", ®) == 0) {
+ if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) {
error = regulator_enable(reg);
if (error != 0) {
device_printf(dev, "cannot enable PHY regulator\n");
Modified: head/sys/arm/allwinner/if_emac.c
==============================================================================
--- head/sys/arm/allwinner/if_emac.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/allwinner/if_emac.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -146,7 +146,7 @@ emac_sys_setup(struct emac_softc *sc)
int error;
/* Activate EMAC clock. */
- error = clk_get_by_ofw_index(sc->emac_dev, 0, &sc->emac_clk);
+ error = clk_get_by_ofw_index(sc->emac_dev, 0, 0, &sc->emac_clk);
if (error != 0) {
device_printf(sc->emac_dev, "cannot get clock\n");
return (error);
Modified: head/sys/arm/nvidia/tegra124/tegra124_cpufreq.c
==============================================================================
--- head/sys/arm/nvidia/tegra124/tegra124_cpufreq.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra124/tegra124_cpufreq.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -432,36 +432,36 @@ get_fdt_resources(struct tegra124_cpufre
device_t parent_dev;
parent_dev = device_get_parent(sc->dev);
- rv = regulator_get_by_ofw_property(parent_dev, "vdd-cpu-supply",
+ rv = regulator_get_by_ofw_property(parent_dev, 0, "vdd-cpu-supply",
&sc->supply_vdd_cpu);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'vdd-cpu' regulator\n");
return (rv);
}
- rv = clk_get_by_ofw_name(parent_dev, "cpu_g", &sc->clk_cpu_g);
+ rv = clk_get_by_ofw_name(parent_dev, 0, "cpu_g", &sc->clk_cpu_g);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'cpu_g' clock: %d\n", rv);
return (ENXIO);
}
- rv = clk_get_by_ofw_name(parent_dev, "cpu_lp", &sc->clk_cpu_lp);
+ rv = clk_get_by_ofw_name(parent_dev, 0, "cpu_lp", &sc->clk_cpu_lp);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'cpu_lp' clock\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(parent_dev, "pll_x", &sc->clk_pll_x);
+ rv = clk_get_by_ofw_name(parent_dev, 0, "pll_x", &sc->clk_pll_x);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'pll_x' clock\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(parent_dev, "pll_p", &sc->clk_pll_p);
+ rv = clk_get_by_ofw_name(parent_dev, 0, "pll_p", &sc->clk_pll_p);
if (rv != 0) {
device_printf(parent_dev, "Cannot get 'pll_p' clock\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(parent_dev, "dfll", &sc->clk_dfll);
+ rv = clk_get_by_ofw_name(parent_dev, 0, "dfll", &sc->clk_dfll);
if (rv != 0) {
/* XXX DPLL is not implemented yet */
/*
Modified: head/sys/arm/nvidia/tegra124/tegra124_pmc.c
==============================================================================
--- head/sys/arm/nvidia/tegra124/tegra124_pmc.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra124/tegra124_pmc.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -494,7 +494,7 @@ tegra124_pmc_attach(device_t dev)
return (rv);
}
- rv = clk_get_by_ofw_name(sc->dev, "pclk", &sc->clk);
+ rv = clk_get_by_ofw_name(sc->dev, 0, "pclk", &sc->clk);
if (rv != 0) {
device_printf(sc->dev, "Cannot get \"pclk\" clock\n");
return (ENXIO);
Modified: head/sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
==============================================================================
--- head/sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -556,7 +556,7 @@ xusbpadctl_attach(device_t dev)
}
node = ofw_bus_get_node(dev);
- rv = hwreset_get_by_ofw_name(dev, "padctl", &sc->rst);
+ rv = hwreset_get_by_ofw_name(dev, 0, "padctl", &sc->rst);
if (rv != 0) {
device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv);
return (rv);
Modified: head/sys/arm/nvidia/tegra_ahci.c
==============================================================================
--- head/sys/arm/nvidia/tegra_ahci.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra_ahci.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -206,77 +206,77 @@ get_fdt_resources(struct tegra_ahci_sc *
int rv;
- rv = regulator_get_by_ofw_property(sc->dev, "hvdd-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-supply",
&sc->supply_hvdd );
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'hvdd' regulator\n");
return (ENXIO);
}
- rv = regulator_get_by_ofw_property(sc->dev, "vddio-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-supply",
&sc->supply_vddio);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'vddio' regulator\n");
return (ENXIO);
}
- rv = regulator_get_by_ofw_property(sc->dev, "avdd-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-supply",
&sc->supply_avdd);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'avdd' regulator\n");
return (ENXIO);
}
- rv = regulator_get_by_ofw_property(sc->dev, "target-5v-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "target-5v-supply",
&sc->supply_target_5v);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'target-5v' regulator\n");
return (ENXIO);
}
- rv = regulator_get_by_ofw_property(sc->dev, "target-12v-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "target-12v-supply",
&sc->supply_target_12v);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'target-12v' regulator\n");
return (ENXIO);
}
- rv = hwreset_get_by_ofw_name(sc->dev, "sata", &sc->hwreset_sata );
+ rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata", &sc->hwreset_sata );
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sata' reset\n");
return (ENXIO);
}
- rv = hwreset_get_by_ofw_name(sc->dev, "sata-oob",
+ rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-oob",
&sc->hwreset_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sata oob' reset\n");
return (ENXIO);
}
- rv = hwreset_get_by_ofw_name(sc->dev, "sata-cold",
+ rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-cold",
&sc->hwreset_sata_cold);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sata cold' reset\n");
return (ENXIO);
}
- rv = phy_get_by_ofw_name(sc->dev, "sata-phy", &sc->phy);
+ rv = phy_get_by_ofw_name(sc->dev, 0, "sata-phy", &sc->phy);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sata' phy\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(sc->dev, "sata", &sc->clk_sata);
+ rv = clk_get_by_ofw_name(sc->dev, 0, "sata", &sc->clk_sata);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sata' clock\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(sc->dev, "sata-oob", &sc->clk_sata_oob);
+ rv = clk_get_by_ofw_name(sc->dev, 0, "sata-oob", &sc->clk_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sata oob' clock\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(sc->dev, "cml1", &sc->clk_cml);
+ rv = clk_get_by_ofw_name(sc->dev, 0, "cml1", &sc->clk_cml);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'cml1' clock\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(sc->dev, "pll_e", &sc->clk_pll_e);
+ rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'pll_e' clock\n");
return (ENXIO);
Modified: head/sys/arm/nvidia/tegra_efuse.c
==============================================================================
--- head/sys/arm/nvidia/tegra_efuse.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra_efuse.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -291,7 +291,7 @@ tegra_efuse_attach(device_t dev)
}
/* OFW resources. */
- rv = clk_get_by_ofw_name(dev, "fuse", &sc->clk);
+ rv = clk_get_by_ofw_name(dev, 0, "fuse", &sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot get fuse clock: %d\n", rv);
goto fail;
@@ -301,7 +301,7 @@ tegra_efuse_attach(device_t dev)
device_printf(dev, "Cannot enable clock: %d\n", rv);
goto fail;
}
- rv = hwreset_get_by_ofw_name(sc->dev, "fuse", &sc->reset);
+ rv = hwreset_get_by_ofw_name(sc->dev, 0, "fuse", &sc->reset);
if (rv != 0) {
device_printf(dev, "Cannot get fuse reset\n");
goto fail;
Modified: head/sys/arm/nvidia/tegra_ehci.c
==============================================================================
--- head/sys/arm/nvidia/tegra_ehci.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra_ehci.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -174,21 +174,21 @@ tegra_ehci_attach(device_t dev)
goto out;
}
- rv = hwreset_get_by_ofw_name(dev, "usb", &sc->reset);
+ rv = hwreset_get_by_ofw_name(dev, 0, "usb", &sc->reset);
if (rv != 0) {
device_printf(dev, "Cannot get reset\n");
rv = ENXIO;
goto out;
}
- rv = phy_get_by_ofw_property(sc->dev, "nvidia,phy", &sc->phy);
+ rv = phy_get_by_ofw_property(sc->dev, 0, "nvidia,phy", &sc->phy);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'nvidia,phy' phy\n");
rv = ENXIO;
goto out;
}
- rv = clk_get_by_ofw_index(sc->dev, 0, &sc->clk);
+ rv = clk_get_by_ofw_index(sc->dev, 0, 0, &sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot get clock\n");
goto out;
Modified: head/sys/arm/nvidia/tegra_i2c.c
==============================================================================
--- head/sys/arm/nvidia/tegra_i2c.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra_i2c.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -666,12 +666,12 @@ tegra_i2c_attach(device_t dev)
}
/* FDT resources. */
- rv = clk_get_by_ofw_name(dev, "div-clk", &sc->clk);
+ rv = clk_get_by_ofw_name(dev, 0, "div-clk", &sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot get i2c clock: %d\n", rv);
goto fail;
}
- rv = hwreset_get_by_ofw_name(sc->dev, "i2c", &sc->reset);
+ rv = hwreset_get_by_ofw_name(sc->dev, 0, "i2c", &sc->reset);
if (rv != 0) {
device_printf(sc->dev, "Cannot get i2c reset\n");
return (ENXIO);
Modified: head/sys/arm/nvidia/tegra_pcie.c
==============================================================================
--- head/sys/arm/nvidia/tegra_pcie.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra_pcie.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -1080,49 +1080,49 @@ tegra_pcib_parse_fdt_resources(struct te
int rv;
/* Power supplies. */
- rv = regulator_get_by_ofw_property(sc->dev, "avddio-pex-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply",
&sc->supply_avddio_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'avddio-pex' regulator\n");
return (ENXIO);
}
- rv = regulator_get_by_ofw_property(sc->dev, "dvddio-pex-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply",
&sc->supply_dvddio_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'dvddio-pex' regulator\n");
return (ENXIO);
}
- rv = regulator_get_by_ofw_property(sc->dev, "avdd-pex-pll-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pex-pll-supply",
&sc->supply_avdd_pex_pll);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'avdd-pex-pll' regulator\n");
return (ENXIO);
}
- rv = regulator_get_by_ofw_property(sc->dev, "hvdd-pex-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-supply",
&sc->supply_hvdd_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'hvdd-pex' regulator\n");
return (ENXIO);
}
- rv = regulator_get_by_ofw_property(sc->dev, "hvdd-pex-pll-e-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-pll-e-supply",
&sc->supply_hvdd_pex_pll_e);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'hvdd-pex-pll-e' regulator\n");
return (ENXIO);
}
- rv = regulator_get_by_ofw_property(sc->dev, "vddio-pex-ctl-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-pex-ctl-supply",
&sc->supply_vddio_pex_ctl);
if (rv != 0) {
device_printf(sc->dev,
"Cannot get 'vddio-pex-ctl' regulator\n");
return (ENXIO);
}
- rv = regulator_get_by_ofw_property(sc->dev, "avdd-pll-erefe-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply",
&sc->supply_avdd_pll_erefe);
if (rv != 0) {
device_printf(sc->dev,
@@ -1131,46 +1131,46 @@ tegra_pcib_parse_fdt_resources(struct te
}
/* Resets. */
- rv = hwreset_get_by_ofw_name(sc->dev, "pex", &sc->hwreset_pex);
+ rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'pex' reset\n");
return (ENXIO);
}
- rv = hwreset_get_by_ofw_name(sc->dev, "afi", &sc->hwreset_afi);
+ rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'afi' reset\n");
return (ENXIO);
}
- rv = hwreset_get_by_ofw_name(sc->dev, "pcie_x", &sc->hwreset_pcie_x);
+ rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'pcie_x' reset\n");
return (ENXIO);
}
/* Clocks. */
- rv = clk_get_by_ofw_name(sc->dev, "pex", &sc->clk_pex);
+ rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'pex' clock\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(sc->dev, "afi", &sc->clk_afi);
+ rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'afi' clock\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(sc->dev, "pll_e", &sc->clk_pll_e);
+ rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'pll_e' clock\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(sc->dev, "cml", &sc->clk_cml);
+ rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'cml' clock\n");
return (ENXIO);
}
/* Phy. */
- rv = phy_get_by_ofw_name(sc->dev, "pcie", &sc->phy);
+ rv = phy_get_by_ofw_name(sc->dev, 0, "pcie", &sc->phy);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'pcie' phy\n");
return (ENXIO);
Modified: head/sys/arm/nvidia/tegra_rtc.c
==============================================================================
--- head/sys/arm/nvidia/tegra_rtc.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra_rtc.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -219,7 +219,7 @@ tegra_rtc_attach(device_t dev)
}
/* OFW resources. */
- rv = clk_get_by_ofw_index(dev, 0, &sc->clk);
+ rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot get i2c clock: %d\n", rv);
goto fail;
Modified: head/sys/arm/nvidia/tegra_sdhci.c
==============================================================================
--- head/sys/arm/nvidia/tegra_sdhci.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra_sdhci.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -289,7 +289,7 @@ tegra_sdhci_attach(device_t dev)
goto fail;
}
- rv = hwreset_get_by_ofw_name(sc->dev, "sdhci", &sc->reset);
+ rv = hwreset_get_by_ofw_name(sc->dev, 0, "sdhci", &sc->reset);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'sdhci' reset\n");
goto fail;
@@ -304,14 +304,14 @@ tegra_sdhci_attach(device_t dev)
gpio_pin_get_by_ofw_property(sc->dev, node, "power-gpios", &sc->gpio_power);
gpio_pin_get_by_ofw_property(sc->dev, node, "wp-gpios", &sc->gpio_wp);
- rv = clk_get_by_ofw_index(dev, 0, &sc->clk);
+ rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot get clock\n");
goto fail;
}
- rv = clk_get_by_ofw_index(dev, 0, &sc->clk);
+ rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot get clock\n");
goto fail;
Modified: head/sys/arm/nvidia/tegra_soctherm.c
==============================================================================
--- head/sys/arm/nvidia/tegra_soctherm.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra_soctherm.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -579,17 +579,17 @@ soctherm_attach(device_t dev)
*/
/* OWF resources */
- rv = hwreset_get_by_ofw_name(dev, "soctherm", &sc->reset);
+ rv = hwreset_get_by_ofw_name(dev, 0, "soctherm", &sc->reset);
if (rv != 0) {
device_printf(dev, "Cannot get fuse reset\n");
goto fail;
}
- rv = clk_get_by_ofw_name(dev, "tsensor", &sc->tsensor_clk);
+ rv = clk_get_by_ofw_name(dev, 0, "tsensor", &sc->tsensor_clk);
if (rv != 0) {
device_printf(dev, "Cannot get 'tsensor' clock: %d\n", rv);
goto fail;
}
- rv = clk_get_by_ofw_name(dev, "soctherm", &sc->soctherm_clk);
+ rv = clk_get_by_ofw_name(dev, 0, "soctherm", &sc->soctherm_clk);
if (rv != 0) {
device_printf(dev, "Cannot get 'soctherm' clock: %d\n", rv);
goto fail;
Modified: head/sys/arm/nvidia/tegra_uart.c
==============================================================================
--- head/sys/arm/nvidia/tegra_uart.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra_uart.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -189,7 +189,7 @@ tegra_uart_probe(device_t dev)
return (ENXIO);
sc->ns8250_base.base.sc_class = (struct uart_class *)cd->ocd_data;
- rv = hwreset_get_by_ofw_name(dev, "serial", &sc->reset);
+ rv = hwreset_get_by_ofw_name(dev, 0, "serial", &sc->reset);
if (rv != 0) {
device_printf(dev, "Cannot get 'serial' reset\n");
return (ENXIO);
@@ -202,7 +202,7 @@ tegra_uart_probe(device_t dev)
node = ofw_bus_get_node(dev);
shift = uart_fdt_get_shift1(node);
- rv = clk_get_by_ofw_index(dev, 0, &sc->clk);
+ rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot get UART clock: %d\n", rv);
return (ENXIO);
Modified: head/sys/arm/nvidia/tegra_usbphy.c
==============================================================================
--- head/sys/arm/nvidia/tegra_usbphy.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/arm/nvidia/tegra_usbphy.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -726,28 +726,28 @@ usbphy_attach(device_t dev)
node = ofw_bus_get_node(dev);
- rv = hwreset_get_by_ofw_name(sc->dev, "usb", &sc->reset_usb);
+ rv = hwreset_get_by_ofw_name(sc->dev, 0, "usb", &sc->reset_usb);
if (rv != 0) {
device_printf(dev, "Cannot get 'usb' reset\n");
return (ENXIO);
}
- rv = hwreset_get_by_ofw_name(sc->dev, "utmi-pads", &sc->reset_pads);
+ rv = hwreset_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->reset_pads);
if (rv != 0) {
device_printf(dev, "Cannot get 'utmi-pads' reset\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(sc->dev, "reg", &sc->clk_reg);
+ rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'reg' clock\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(sc->dev, "pll_u", &sc->clk_pllu);
+ rv = clk_get_by_ofw_name(sc->dev, 0, "pll_u", &sc->clk_pllu);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'pll_u' clock\n");
return (ENXIO);
}
- rv = clk_get_by_ofw_name(sc->dev, "utmi-pads", &sc->clk_pads);
+ rv = clk_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->clk_pads);
if (rv != 0) {
device_printf(sc->dev, "Cannot get 'utmi-pads' clock\n");
return (ENXIO);
@@ -788,7 +788,7 @@ usbphy_attach(device_t dev)
return rv;
if (OF_hasprop(node, "vbus-supply")) {
- rv = regulator_get_by_ofw_property(sc->dev, "vbus-supply",
+ rv = regulator_get_by_ofw_property(sc->dev, 0, "vbus-supply",
&sc->supply_vbus);
if (rv != 0) {
device_printf(sc->dev,
Modified: head/sys/dev/dwc/if_dwc.c
==============================================================================
--- head/sys/dev/dwc/if_dwc.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/dev/dwc/if_dwc.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -1097,7 +1097,7 @@ dwc_clock_init(device_t dev)
int error;
/* Enable clock */
- if (clk_get_by_ofw_name(dev, "stmmaceth", &clk) == 0) {
+ if (clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk) == 0) {
error = clk_enable(clk);
if (error != 0) {
device_printf(dev, "could not enable main clock\n");
@@ -1106,7 +1106,7 @@ dwc_clock_init(device_t dev)
}
/* De-assert reset */
- if (hwreset_get_by_ofw_name(dev, "stmmaceth", &rst) == 0) {
+ if (hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst) == 0) {
error = hwreset_deassert(rst);
if (error != 0) {
device_printf(dev, "could not de-assert reset\n");
Modified: head/sys/dev/extres/clk/clk.c
==============================================================================
--- head/sys/dev/extres/clk/clk.c Sun Jul 10 17:16:56 2016 (r302527)
+++ head/sys/dev/extres/clk/clk.c Sun Jul 10 18:28:15 2016 (r302528)
@@ -1196,22 +1196,7 @@ clk_get_by_id(device_t dev, struct clkdo
#ifdef FDT
int
-clk_get_by_ofw_index(device_t dev, int idx, clk_t *clk)
-{
- phandle_t cnode;
-
- cnode = ofw_bus_get_node(dev);
- if (cnode <= 0) {
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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