svn commit: r294662 - head/lib/libproc

[Ruslan Bukin]

Author: br
Date: Sun Jan 24 12:10:29 2016
New Revision: 294662
URL: https://svnweb.freebsd.org/changeset/base/294662

Log:
  Add support for RISC-V ISA.
  
  Reviewed by:	andrew
  Sponsored by:	DARPA, AFRL
  Sponsored by:	HEIF5
  Differential Revision:	https://reviews.freebsd.org/D5040

Modified:
  head/lib/libproc/proc_bkpt.c
  head/lib/libproc/proc_regs.c

Modified: head/lib/libproc/proc_bkpt.c
==============================================================================
--- head/lib/libproc/proc_bkpt.c	Sun Jan 24 11:03:35 2016	(r294661)
+++ head/lib/libproc/proc_bkpt.c	Sun Jan 24 12:10:29 2016	(r294662)
@@ -61,6 +61,9 @@ __FBSDID("$FreeBSD$");
 #elif defined(__powerpc__)
 #define	BREAKPOINT_INSTR	0x7fe00008	/* trap */
 #define	BREAKPOINT_INSTR_SZ	4
+#elif defined(__riscv__)
+#define	BREAKPOINT_INSTR	0x00100073	/* sbreak */
+#define	BREAKPOINT_INSTR_SZ	4
 #else
 #error "Add support for your architecture"
 #endif

Modified: head/lib/libproc/proc_regs.c
==============================================================================
--- head/lib/libproc/proc_regs.c	Sun Jan 24 11:03:35 2016	(r294661)
+++ head/lib/libproc/proc_regs.c	Sun Jan 24 12:10:29 2016	(r294662)
@@ -66,6 +66,8 @@ proc_regget(struct proc_handle *phdl, pr
 		*regvalue = regs.r_regs[PC];
 #elif defined(__powerpc__)
 		*regvalue = regs.pc;
+#elif defined(__riscv__)
+		*regvalue = regs.sepc;
 #endif
 		break;
 	case REG_SP:
@@ -81,6 +83,8 @@ proc_regget(struct proc_handle *phdl, pr
 		*regvalue = regs.r_regs[SP];
 #elif defined(__powerpc__)
 		*regvalue = regs.fixreg[1];
+#elif defined(__riscv__)
+		*regvalue = regs.sp;
 #endif
 		break;
 	default:
@@ -117,6 +121,8 @@ proc_regset(struct proc_handle *phdl, pr
 		regs.r_regs[PC] = regvalue;
 #elif defined(__powerpc__)
 		regs.pc = regvalue;
+#elif defined(__riscv__)
+		regs.sepc = regvalue;
 #endif
 		break;
 	case REG_SP:
@@ -132,6 +138,8 @@ proc_regset(struct proc_handle *phdl, pr
 		regs.r_regs[PC] = regvalue;
 #elif defined(__powerpc__)
 		regs.fixreg[1] = regvalue;
+#elif defined(__riscv__)
+		regs.sp = regvalue;
 #endif
 		break;
 	default: