svn commit: r294432 - in head/sys: arm/conf boot/fdt/dts/arm
Zbigniew Bodek
zbb at FreeBSD.org
Wed Jan 20 14:14:32 UTC 2016
Author: zbb
Date: Wed Jan 20 14:14:30 2016
New Revision: 294432
URL: https://svnweb.freebsd.org/changeset/base/294432
Log:
Change DTS entry of PCIe controller for Armada38x
Invalid (in FreeBSD) definition of PCI controller was
replaced with another one, working in FreeBSD environment.
PCI controller's entry had to move from its parent node
so as to be recognized properly by FBSD.
PCI was enabled in kernel configuration file.
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz at semihalf.com>
Differential revision: https://reviews.freebsd.org/D4379
Modified:
head/sys/arm/conf/ARMADA38X
head/sys/boot/fdt/dts/arm/armada-385.dtsi
head/sys/boot/fdt/dts/arm/armada-388-gp.dts
head/sys/boot/fdt/dts/arm/armada-38x.dtsi
Modified: head/sys/arm/conf/ARMADA38X
==============================================================================
--- head/sys/arm/conf/ARMADA38X Wed Jan 20 14:10:00 2016 (r294431)
+++ head/sys/arm/conf/ARMADA38X Wed Jan 20 14:14:30 2016 (r294432)
@@ -51,6 +51,12 @@ device uart_ns8250
# Network
device ether
device vlan
+device mii
+device bpf
+device re
+
+# PCI
+device pci
# Interrupt controllers
device gic
Modified: head/sys/boot/fdt/dts/arm/armada-385.dtsi
==============================================================================
--- head/sys/boot/fdt/dts/arm/armada-385.dtsi Wed Jan 20 14:10:00 2016 (r294431)
+++ head/sys/boot/fdt/dts/arm/armada-385.dtsi Wed Jan 20 14:14:30 2016 (r294432)
@@ -77,110 +77,5 @@
compatible = "marvell,mv88f6820-pinctrl";
};
};
-
- pcie-controller {
- compatible = "marvell,armada-370-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- msi-parent = <&mpic>;
- bus-range = <0x00 0xff>;
-
- ranges =
- <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
- 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
- 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
- 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
- 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
- 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
- 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
- 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
- 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
- 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
- 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
-
- /*
- * This port can be either x4 or x1. When
- * configured in x4 by the bootloader, then
- * pcie at 4,0 is not available.
- */
- pcie at 1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
- 0x81000000 0 0 0x81000000 0x1 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 8>;
- status = "disabled";
- };
-
- /* x1 port */
- pcie at 2,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
- 0x81000000 0 0 0x81000000 0x2 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 5>;
- status = "disabled";
- };
-
- /* x1 port */
- pcie at 3,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
- reg = <0x1800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
- 0x81000000 0 0 0x81000000 0x3 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- marvell,pcie-port = <2>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 6>;
- status = "disabled";
- };
-
- /*
- * x1 port only available when pcie at 1,0 is
- * configured as a x1 port
- */
- pcie at 4,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
- reg = <0x2000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
- 0x81000000 0 0 0x81000000 0x4 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- marvell,pcie-port = <3>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 7>;
- status = "disabled";
- };
- };
};
};
Modified: head/sys/boot/fdt/dts/arm/armada-388-gp.dts
==============================================================================
--- head/sys/boot/fdt/dts/arm/armada-388-gp.dts Wed Jan 20 14:10:00 2016 (r294431)
+++ head/sys/boot/fdt/dts/arm/armada-388-gp.dts Wed Jan 20 14:14:30 2016 (r294432)
@@ -226,31 +226,6 @@
};
};
- pcie-controller {
- status = "okay";
- /*
- * One PCIe units is accessible through
- * standard PCIe slot on the board.
- */
- pcie at 1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /*
- * The two other PCIe units are accessible
- * through mini PCIe slot on the board.
- */
- pcie at 2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- pcie at 3,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- };
-
gpio-fan {
compatible = "gpio-fan";
gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
@@ -259,6 +234,10 @@
};
};
+ pci0: pcie at f1080000 {
+ status = "okay";
+ };
+
reg_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus";
Modified: head/sys/boot/fdt/dts/arm/armada-38x.dtsi
==============================================================================
--- head/sys/boot/fdt/dts/arm/armada-38x.dtsi Wed Jan 20 14:10:00 2016 (r294431)
+++ head/sys/boot/fdt/dts/arm/armada-38x.dtsi Wed Jan 20 14:14:30 2016 (r294432)
@@ -593,6 +593,25 @@
};
};
+ pci0: pcie at f1080000 {
+ compatible = "mrvl,pcie";
+ status = "disabled";
+ device_type = "pci";
+ #interrupt-cells = <3>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf1080000 0x2000>;
+ bus-range = <0 255>;
+ ranges = <0x42000000 0x0 0xf1200000 0xf1200000 0x0 0x00100000
+ 0x41000000 0x0 0x00000000 0xf1300000 0x0 0x00100000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 91 0>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ 0x0000 0x0 0x0 0x1 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
+ >;
+ };
+
clocks {
/* 2 GHz fixed main PLL */
mainpll: mainpll {
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