svn commit: r298802 - head/sys/arm/ti
Oleksandr Tymoshenko
gonzo at FreeBSD.org
Fri Apr 29 20:31:50 UTC 2016
Author: gonzo
Date: Fri Apr 29 20:31:49 2016
New Revision: 298802
URL: https://svnweb.freebsd.org/changeset/base/298802
Log:
Add driver for AM33xx SoC touchscreen
Split ADC driver in two halves: ADC(analog ot digital) and
TSC(touchscreen). Touchscreen driver is fully functional
up to the point of reporting samples. This part will be added
once FreeBSD has API for touchscreen.
Tested on: Beaglebone Black + 4DCAPE-43T
Reviewed by: loos
Differential Revision: https://reviews.freebsd.org/D5847
Modified:
head/sys/arm/ti/ti_adc.c
head/sys/arm/ti/ti_adcreg.h
head/sys/arm/ti/ti_adcvar.h
Modified: head/sys/arm/ti/ti_adc.c
==============================================================================
--- head/sys/arm/ti/ti_adc.c Fri Apr 29 20:22:10 2016 (r298801)
+++ head/sys/arm/ti/ti_adc.c Fri Apr 29 20:31:49 2016 (r298802)
@@ -31,17 +31,23 @@ __FBSDID("$FreeBSD$");
#include <sys/systm.h>
#include <sys/bus.h>
+#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/limits.h>
#include <sys/lock.h>
#include <sys/module.h>
#include <sys/mutex.h>
+#include <sys/condvar.h>
#include <sys/resource.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
+#include <sys/selinfo.h>
+#include <sys/poll.h>
+#include <sys/uio.h>
#include <machine/bus.h>
+#include <dev/fdt/fdt_common.h>
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
@@ -50,16 +56,26 @@ __FBSDID("$FreeBSD$");
#include <arm/ti/ti_adcreg.h>
#include <arm/ti/ti_adcvar.h>
+#undef DEBUG_TSC
+
+#define DEFAULT_CHARGE_DELAY 0x400
+#define STEPDLY_OPEN 0x98
+
+#define ORDER_XP 0
+#define ORDER_XN 1
+#define ORDER_YP 2
+#define ORDER_YN 3
+
/* Define our 8 steps, one for each input channel. */
static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = {
- { .stepconfig = ADC_STEPCFG1, .stepdelay = ADC_STEPDLY1 },
- { .stepconfig = ADC_STEPCFG2, .stepdelay = ADC_STEPDLY2 },
- { .stepconfig = ADC_STEPCFG3, .stepdelay = ADC_STEPDLY3 },
- { .stepconfig = ADC_STEPCFG4, .stepdelay = ADC_STEPDLY4 },
- { .stepconfig = ADC_STEPCFG5, .stepdelay = ADC_STEPDLY5 },
- { .stepconfig = ADC_STEPCFG6, .stepdelay = ADC_STEPDLY6 },
- { .stepconfig = ADC_STEPCFG7, .stepdelay = ADC_STEPDLY7 },
- { .stepconfig = ADC_STEPCFG8, .stepdelay = ADC_STEPDLY8 },
+ { .stepconfig = ADC_STEPCFG(1), .stepdelay = ADC_STEPDLY(1) },
+ { .stepconfig = ADC_STEPCFG(2), .stepdelay = ADC_STEPDLY(2) },
+ { .stepconfig = ADC_STEPCFG(3), .stepdelay = ADC_STEPDLY(3) },
+ { .stepconfig = ADC_STEPCFG(4), .stepdelay = ADC_STEPDLY(4) },
+ { .stepconfig = ADC_STEPCFG(5), .stepdelay = ADC_STEPDLY(5) },
+ { .stepconfig = ADC_STEPCFG(6), .stepdelay = ADC_STEPDLY(6) },
+ { .stepconfig = ADC_STEPCFG(7), .stepdelay = ADC_STEPDLY(7) },
+ { .stepconfig = ADC_STEPCFG(8), .stepdelay = ADC_STEPDLY(8) },
};
static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 };
@@ -67,6 +83,7 @@ static int ti_adc_samples[5] = { 0, 2, 4
static void
ti_adc_enable(struct ti_adc_softc *sc)
{
+ uint32_t reg;
TI_ADC_LOCK_ASSERT(sc);
@@ -75,10 +92,28 @@ ti_adc_enable(struct ti_adc_softc *sc)
/* Enable the FIFO0 threshold and the end of sequence interrupt. */
ADC_WRITE4(sc, ADC_IRQENABLE_SET,
- ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ);
+ ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ);
+ reg = ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID;
+ if (sc->sc_tsc_wires > 0) {
+ reg |= ADC_CTRL_TSC_ENABLE;
+ switch (sc->sc_tsc_wires) {
+ case 4:
+ reg |= ADC_CTRL_TSC_4WIRE;
+ break;
+ case 5:
+ reg |= ADC_CTRL_TSC_5WIRE;
+ break;
+ case 8:
+ reg |= ADC_CTRL_TSC_8WIRE;
+ break;
+ default:
+ break;
+ }
+ }
+ reg |= ADC_CTRL_ENABLE;
/* Enable the ADC. Run thru enabled steps, start the conversions. */
- ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) | ADC_CTRL_ENABLE);
+ ADC_WRITE4(sc, ADC_CTRL, reg);
sc->sc_last_state = 1;
}
@@ -102,7 +137,7 @@ ti_adc_disable(struct ti_adc_softc *sc)
/* Disable the FIFO0 threshold and the end of sequence interrupt. */
ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
- ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ);
+ ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ);
/* ACK any pending interrupt. */
ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS));
@@ -114,20 +149,27 @@ ti_adc_disable(struct ti_adc_softc *sc)
count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
}
+ count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
+ while (count > 0) {
+ data = ADC_READ4(sc, ADC_FIFO1DATA);
+ count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
+ }
+
sc->sc_last_state = 0;
}
static int
ti_adc_setup(struct ti_adc_softc *sc)
{
- int ain;
+ int ain, i;
uint32_t enabled;
TI_ADC_LOCK_ASSERT(sc);
/* Check for enabled inputs. */
- enabled = 0;
- for (ain = 0; ain < TI_ADC_NPINS; ain++) {
+ enabled = sc->sc_tsc_enabled;
+ for (i = 0; i < sc->sc_adc_nchannels; i++) {
+ ain = sc->sc_adc_channels[i];
if (ti_adc_inputs[ain].enable)
enabled |= (1U << (ain + 1));
}
@@ -182,13 +224,15 @@ ti_adc_input_setup(struct ti_adc_softc *
static void
ti_adc_reset(struct ti_adc_softc *sc)
{
- int ain;
+ int ain, i;
TI_ADC_LOCK_ASSERT(sc);
/* Disable all the inputs. */
- for (ain = 0; ain < TI_ADC_NPINS; ain++)
+ for (i = 0; i < sc->sc_adc_nchannels; i++) {
+ ain = sc->sc_adc_channels[i];
ti_adc_inputs[ain].enable = 0;
+ }
}
static int
@@ -345,31 +389,127 @@ ti_adc_read_data(struct ti_adc_softc *sc
}
}
+static int
+cmp_values(const void *a, const void *b)
+{
+ const uint32_t *v1, *v2;
+ v1 = a;
+ v2 = b;
+ if (*v1 < *v2)
+ return -1;
+ if (*v1 > *v2)
+ return 1;
+
+ return (0);
+}
+
+static void
+ti_adc_tsc_read_data(struct ti_adc_softc *sc)
+{
+ int count;
+ uint32_t data[16];
+ uint32_t x, y;
+ int i, start, end;
+
+ TI_ADC_LOCK_ASSERT(sc);
+
+ /* Read the available data. */
+ count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
+ if (count == 0)
+ return;
+
+ i = 0;
+ while (count > 0) {
+ data[i++] = ADC_READ4(sc, ADC_FIFO1DATA) & ADC_FIFO_DATA_MSK;
+ count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
+ }
+
+ if (sc->sc_coord_readouts > 3) {
+ start = 1;
+ end = sc->sc_coord_readouts - 1;
+ qsort(data, sc->sc_coord_readouts,
+ sizeof(data[0]), &cmp_values);
+ qsort(&data[sc->sc_coord_readouts + 2],
+ sc->sc_coord_readouts,
+ sizeof(data[0]), &cmp_values);
+ }
+ else {
+ start = 0;
+ end = sc->sc_coord_readouts;
+ }
+
+ x = y = 0;
+ for (i = start; i < end; i++)
+ y += data[i];
+ y /= (end - start);
+
+ for (i = sc->sc_coord_readouts + 2 + start; i < sc->sc_coord_readouts + 2 + end; i++)
+ x += data[i];
+ x /= (end - start);
+
+#ifdef DEBUG_TSC
+ device_printf(sc->sc_dev, "touchscreen x: %d, y: %d\n", x, y);
+#endif
+ /* TODO: That's where actual event reporting should take place */
+}
+
+static void
+ti_adc_intr_locked(struct ti_adc_softc *sc, uint32_t status)
+{
+ /* Read the available data. */
+ if (status & ADC_IRQ_FIFO0_THRES)
+ ti_adc_read_data(sc);
+}
+
+static void
+ti_adc_tsc_intr_locked(struct ti_adc_softc *sc, uint32_t status)
+{
+ /* Read the available data. */
+ if (status & ADC_IRQ_FIFO1_THRES)
+ ti_adc_tsc_read_data(sc);
+
+}
+
static void
ti_adc_intr(void *arg)
{
struct ti_adc_softc *sc;
- uint32_t status;
+ uint32_t status, rawstatus;
sc = (struct ti_adc_softc *)arg;
+ TI_ADC_LOCK(sc);
+
+ rawstatus = ADC_READ4(sc, ADC_IRQSTATUS_RAW);
status = ADC_READ4(sc, ADC_IRQSTATUS);
- if (status == 0)
- return;
- if (status & ~(ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ))
- device_printf(sc->sc_dev, "stray interrupt: %#x\n", status);
- TI_ADC_LOCK(sc);
- /* ACK the interrupt. */
- ADC_WRITE4(sc, ADC_IRQSTATUS, status);
+ if (rawstatus & ADC_IRQ_HW_PEN_ASYNC) {
+ sc->sc_pen_down = 1;
+ status |= ADC_IRQ_HW_PEN_ASYNC;
+ ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
+ ADC_IRQ_HW_PEN_ASYNC);
+ }
+
+ if (rawstatus & ADC_IRQ_PEN_UP) {
+ sc->sc_pen_down = 0;
+ status |= ADC_IRQ_PEN_UP;
+ }
- /* Read the available data. */
if (status & ADC_IRQ_FIFO0_THRES)
- ti_adc_read_data(sc);
+ ti_adc_intr_locked(sc, status);
+
+ if (status & ADC_IRQ_FIFO1_THRES)
+ ti_adc_tsc_intr_locked(sc, status);
+
+ if (status) {
+ /* ACK the interrupt. */
+ ADC_WRITE4(sc, ADC_IRQSTATUS, status);
+ }
/* Start the next conversion ? */
if (status & ADC_IRQ_END_OF_SEQ)
ti_adc_setup(sc);
+
TI_ADC_UNLOCK(sc);
}
@@ -380,7 +520,7 @@ ti_adc_sysctl_init(struct ti_adc_softc *
struct sysctl_ctx_list *ctx;
struct sysctl_oid *tree_node, *inp_node, *inpN_node;
struct sysctl_oid_list *tree, *inp_tree, *inpN_tree;
- int ain;
+ int ain, i;
/*
* Add per-pin sysctl tree/handlers.
@@ -395,7 +535,8 @@ ti_adc_sysctl_init(struct ti_adc_softc *
CTLFLAG_RD, NULL, "ADC inputs");
inp_tree = SYSCTL_CHILDREN(inp_node);
- for (ain = 0; ain < TI_ADC_NPINS; ain++) {
+ for (i = 0; i < sc->sc_adc_nchannels; i++) {
+ ain = sc->sc_adc_channels[i];
snprintf(pinbuf, sizeof(pinbuf), "%d", ain);
inpN_node = SYSCTL_ADD_NODE(ctx, inp_tree, OID_AUTO, pinbuf,
@@ -420,11 +561,12 @@ ti_adc_sysctl_init(struct ti_adc_softc *
static void
ti_adc_inputs_init(struct ti_adc_softc *sc)
{
- int ain;
+ int ain, i;
struct ti_adc_input *input;
TI_ADC_LOCK(sc);
- for (ain = 0; ain < TI_ADC_NPINS; ain++) {
+ for (i = 0; i < sc->sc_adc_nchannels; i++) {
+ ain = sc->sc_adc_channels[i];
input = &ti_adc_inputs[ain];
input->sc = sc;
input->input = ain;
@@ -437,29 +579,126 @@ ti_adc_inputs_init(struct ti_adc_softc *
}
static void
-ti_adc_idlestep_init(struct ti_adc_softc *sc)
+ti_adc_tsc_init(struct ti_adc_softc *sc)
{
- uint32_t val;
+ int i, start_step, end_step;
+ uint32_t stepconfig, val;
+
+ TI_ADC_LOCK(sc);
+
+ /* X coordinates */
+ stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
+ ADC_STEP_MODE_HW_ONESHOT | sc->sc_xp_bit;
+ if (sc->sc_tsc_wires == 4)
+ stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit;
+ else if (sc->sc_tsc_wires == 5)
+ stepconfig |= ADC_STEP_INP(4) |
+ sc->sc_xn_bit | sc->sc_yn_bit | sc->sc_yp_bit;
+ else if (sc->sc_tsc_wires == 8)
+ stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit;
+
+ start_step = ADC_STEPS - sc->sc_coord_readouts + 1;
+ end_step = start_step + sc->sc_coord_readouts - 1;
+ for (i = start_step; i <= end_step; i++) {
+ ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig);
+ ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN);
+ }
+
+ /* Y coordinates */
+ stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
+ ADC_STEP_MODE_HW_ONESHOT | sc->sc_yn_bit |
+ ADC_STEP_INM(8);
+ if (sc->sc_tsc_wires == 4)
+ stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit;
+ else if (sc->sc_tsc_wires == 5)
+ stepconfig |= ADC_STEP_INP(4) |
+ sc->sc_xp_bit | sc->sc_xn_bit | sc->sc_yp_bit;
+ else if (sc->sc_tsc_wires == 8)
+ stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit;
+
+ start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1;
+ end_step = start_step + sc->sc_coord_readouts - 1;
+ for (i = start_step; i <= end_step; i++) {
+ ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig);
+ ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN);
+ }
+ /* Charge config */
val = ADC_READ4(sc, ADC_IDLECONFIG);
+ ADC_WRITE4(sc, ADC_TC_CHARGE_STEPCONFIG, val);
+ ADC_WRITE4(sc, ADC_TC_CHARGE_DELAY, sc->sc_charge_delay);
- /* Set single ended operation. */
- val &= ~ADC_STEP_DIFF_CNTRL;
+ /* 2 steps for Z */
+ start_step = ADC_STEPS - (sc->sc_coord_readouts + 2) + 1;
+ stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
+ ADC_STEP_MODE_HW_ONESHOT | sc->sc_yp_bit |
+ sc->sc_xn_bit | ADC_STEP_INP(sc->sc_xp_inp) |
+ ADC_STEP_INM(8);
+ ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig);
+ ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN);
+ start_step++;
+ stepconfig |= ADC_STEP_INP(sc->sc_yn_inp);
+ ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig);
+ ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN);
+
+ ADC_WRITE4(sc, ADC_FIFO1THRESHOLD, (sc->sc_coord_readouts*2 + 2) - 1);
+
+ sc->sc_tsc_enabled = 1;
+ start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1;
+ end_step = ADC_STEPS;
+ for (i = start_step; i <= end_step; i++) {
+ sc->sc_tsc_enabled |= (1 << i);
+ }
- /* Set the negative voltage reference. */
- val &= ~ADC_STEP_RFM_MSK;
- /* Set the positive voltage reference. */
- val &= ~ADC_STEP_RFP_MSK;
+ TI_ADC_UNLOCK(sc);
+}
- /* Connect the input to VREFN. */
- val &= ~ADC_STEP_INP_MSK;
- val |= ADC_STEP_IN_VREFN << ADC_STEP_INP_SHIFT;
+static void
+ti_adc_idlestep_init(struct ti_adc_softc *sc)
+{
+ uint32_t val;
+
+ val = ADC_STEP_YNN_SW | ADC_STEP_INM(8) | ADC_STEP_INP(8) | ADC_STEP_YPN_SW;
ADC_WRITE4(sc, ADC_IDLECONFIG, val);
}
static int
+ti_adc_config_wires(struct ti_adc_softc *sc, int *wire_configs, int nwire_configs)
+{
+ int i;
+ int wire, ai;
+
+ for (i = 0; i < nwire_configs; i++) {
+ wire = wire_configs[i] & 0xf;
+ ai = (wire_configs[i] >> 4) & 0xf;
+ switch (wire) {
+ case ORDER_XP:
+ sc->sc_xp_bit = ADC_STEP_XPP_SW;
+ sc->sc_xp_inp = ai;
+ break;
+ case ORDER_XN:
+ sc->sc_xn_bit = ADC_STEP_XNN_SW;
+ sc->sc_xn_inp = ai;
+ break;
+ case ORDER_YP:
+ sc->sc_yp_bit = ADC_STEP_YPP_SW;
+ sc->sc_yp_inp = ai;
+ break;
+ case ORDER_YN:
+ sc->sc_yn_bit = ADC_STEP_YNN_SW;
+ sc->sc_yn_inp = ai;
+ break;
+ default:
+ device_printf(sc->sc_dev, "Invalid wire config\n");
+ return (-1);
+ }
+ }
+ return (0);
+}
+
+static int
ti_adc_probe(device_t dev)
{
@@ -473,17 +712,68 @@ ti_adc_probe(device_t dev)
static int
ti_adc_attach(device_t dev)
{
- int err, rid;
+ int err, rid, i;
struct ti_adc_softc *sc;
- uint32_t reg, rev;
+ uint32_t rev, reg;
+ phandle_t node, child;
+ pcell_t cell;
+ int *channels;
+ int nwire_configs;
+ int *wire_configs;
sc = device_get_softc(dev);
sc->sc_dev = dev;
- /* Activate the ADC_TSC module. */
- err = ti_prcm_clk_enable(TSC_ADC_CLK);
- if (err)
- return (err);
+ node = ofw_bus_get_node(dev);
+
+ sc->sc_tsc_wires = 0;
+ sc->sc_coord_readouts = 1;
+ sc->sc_x_plate_resistance = 0;
+ sc->sc_charge_delay = DEFAULT_CHARGE_DELAY;
+ /* Read "tsc" node properties */
+ child = ofw_bus_find_child(node, "tsc");
+ if (child != 0) {
+ if ((OF_getprop(child, "ti,wires", &cell, sizeof(cell))) > 0)
+ sc->sc_tsc_wires = fdt32_to_cpu(cell);
+ if ((OF_getprop(child, "ti,coordinate-readouts", &cell, sizeof(cell))) > 0)
+ sc->sc_coord_readouts = fdt32_to_cpu(cell);
+ if ((OF_getprop(child, "ti,x-plate-resistance", &cell, sizeof(cell))) > 0)
+ sc->sc_x_plate_resistance = fdt32_to_cpu(cell);
+ if ((OF_getprop(child, "ti,charge-delay", &cell, sizeof(cell))) > 0)
+ sc->sc_charge_delay = fdt32_to_cpu(cell);
+ nwire_configs = OF_getencprop_alloc(child, "ti,wire-config",
+ sizeof(*wire_configs), (void **)&wire_configs);
+ if (nwire_configs != sc->sc_tsc_wires) {
+ device_printf(sc->sc_dev,
+ "invalid nubmer of ti,wire-config: %d (should be %d)\n",
+ nwire_configs, sc->sc_tsc_wires);
+ free(wire_configs, M_OFWPROP);
+ return (EINVAL);
+ }
+ err = ti_adc_config_wires(sc, wire_configs, nwire_configs);
+ free(wire_configs, M_OFWPROP);
+ if (err)
+ return (EINVAL);
+ }
+
+ /* Read "adc" node properties */
+ child = ofw_bus_find_child(node, "adc");
+ if (child != 0) {
+ sc->sc_adc_nchannels = OF_getencprop_alloc(child, "ti,adc-channels",
+ sizeof(*channels), (void **)&channels);
+ if (sc->sc_adc_nchannels > 0) {
+ for (i = 0; i < sc->sc_adc_nchannels; i++)
+ sc->sc_adc_channels[i] = channels[i];
+ free(channels, M_OFWPROP);
+ }
+ }
+
+ /* Sanity check FDT data */
+ if (sc->sc_tsc_wires + sc->sc_adc_nchannels > TI_ADC_NPINS) {
+ device_printf(dev, "total number of chanels (%d) is larger than %d\n",
+ sc->sc_tsc_wires + sc->sc_adc_nchannels, TI_ADC_NPINS);
+ return (ENXIO);
+ }
rid = 0;
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
@@ -493,6 +783,11 @@ ti_adc_attach(device_t dev)
return (ENXIO);
}
+ /* Activate the ADC_TSC module. */
+ err = ti_prcm_clk_enable(TSC_ADC_CLK);
+ if (err)
+ return (err);
+
rid = 0;
sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE);
@@ -521,25 +816,29 @@ ti_adc_attach(device_t dev)
rev & ADC_REV_MINOR_MSK,
(rev & ADC_REV_CUSTOM_MSK) >> ADC_REV_CUSTOM_SHIFT);
- /*
- * Disable the step write protect and make it store the step ID for
- * the captured data on FIFO.
- */
reg = ADC_READ4(sc, ADC_CTRL);
ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID);
/*
- * Set the ADC prescaler to 2400 (yes, the actual value written here
- * is 2400 - 1).
- * This sets the ADC clock to ~10Khz (CLK_M_OSC / 2400).
+ * Set the ADC prescaler to 2400 if touchscreen is not enabled
+ * and to 24 if it is. This sets the ADC clock to ~10Khz and
+ * ~1Mhz respectively (CLK_M_OSC / prescaler).
*/
- ADC_WRITE4(sc, ADC_CLKDIV, 2399);
+ if (sc->sc_tsc_wires)
+ ADC_WRITE4(sc, ADC_CLKDIV, 24 - 1);
+ else
+ ADC_WRITE4(sc, ADC_CLKDIV, 2400 - 1);
TI_ADC_LOCK_INIT(sc);
ti_adc_idlestep_init(sc);
ti_adc_inputs_init(sc);
ti_adc_sysctl_init(sc);
+ ti_adc_tsc_init(sc);
+
+ TI_ADC_LOCK(sc);
+ ti_adc_setup(sc);
+ TI_ADC_UNLOCK(sc);
return (0);
}
Modified: head/sys/arm/ti/ti_adcreg.h
==============================================================================
--- head/sys/arm/ti/ti_adcreg.h Fri Apr 29 20:22:10 2016 (r298801)
+++ head/sys/arm/ti/ti_adcreg.h Fri Apr 29 20:31:49 2016 (r298802)
@@ -60,6 +60,10 @@
#define ADC_IRQ_END_OF_SEQ (1 << 1)
#define ADC_IRQ_HW_PEN_ASYNC (1 << 0)
#define ADC_CTRL 0x040
+#define ADC_CTRL_TSC_ENABLE (1 << 7)
+#define ADC_CTRL_TSC_4WIRE (1 << 5)
+#define ADC_CTRL_TSC_5WIRE (2 << 5)
+#define ADC_CTRL_TSC_8WIRE (3 << 5)
#define ADC_CTRL_STEP_WP (1 << 2)
#define ADC_CTRL_STEP_ID (1 << 1)
#define ADC_CTRL_ENABLE (1 << 0)
@@ -67,22 +71,12 @@
#define ADC_CLKDIV 0x04c
#define ADC_STEPENABLE 0x054
#define ADC_IDLECONFIG 0x058
-#define ADC_STEPCFG1 0x064
-#define ADC_STEPDLY1 0x068
-#define ADC_STEPCFG2 0x06c
-#define ADC_STEPDLY2 0x070
-#define ADC_STEPCFG3 0x074
-#define ADC_STEPDLY3 0x078
-#define ADC_STEPCFG4 0x07c
-#define ADC_STEPDLY4 0x080
-#define ADC_STEPCFG5 0x084
-#define ADC_STEPDLY5 0x088
-#define ADC_STEPCFG6 0x08c
-#define ADC_STEPDLY6 0x090
-#define ADC_STEPCFG7 0x094
-#define ADC_STEPDLY7 0x098
-#define ADC_STEPCFG8 0x09c
-#define ADC_STEPDLY8 0x0a0
+#define ADC_TC_CHARGE_STEPCONFIG 0x05C
+#define ADC_TC_CHARGE_DELAY 0x060
+#define ADC_STEPS 16
+#define ADC_STEPCFG(n) (0x064 + (8*((n)-1)))
+#define ADC_STEPDLY(n) (0x068 + (8*((n)-1)))
+#define ADC_STEP_FIFO1 (1 << 26)
#define ADC_STEP_DIFF_CNTRL (1 << 25)
#define ADC_STEP_RFM_MSK 0x01800000
#define ADC_STEP_RFM_SHIFT 23
@@ -92,8 +86,10 @@
#define ADC_STEP_RFM_VREFN 3
#define ADC_STEP_INP_MSK 0x00780000
#define ADC_STEP_INP_SHIFT 19
+#define ADC_STEP_INP(i) ((i) << ADC_STEP_INP_SHIFT)
#define ADC_STEP_INM_MSK 0x00078000
#define ADC_STEP_INM_SHIFT 15
+#define ADC_STEP_INM(i) ((i) << ADC_STEP_INM_SHIFT)
#define ADC_STEP_IN_VREFN 8
#define ADC_STEP_RFP_MSK 0x00007000
#define ADC_STEP_RFP_SHIFT 12
@@ -102,16 +98,26 @@
#define ADC_STEP_RFP_YPLL 2
#define ADC_STEP_RFP_VREFP 3
#define ADC_STEP_RFP_INTREF 4
+#define ADC_STEP_YPN_SW (1 << 10)
+#define ADC_STEP_YNN_SW (1 << 8)
+#define ADC_STEP_YPP_SW (1 << 7)
+#define ADC_STEP_XNN_SW (1 << 6)
+#define ADC_STEP_XPP_SW (1 << 5)
#define ADC_STEP_AVG_MSK 0x0000001c
#define ADC_STEP_AVG_SHIFT 2
#define ADC_STEP_MODE_MSK 0x00000003
#define ADC_STEP_MODE_ONESHOT 0x00000000
#define ADC_STEP_MODE_CONTINUOUS 0x00000001
+#define ADC_STEP_MODE_HW_ONESHOT 0x00000002
+#define ADC_STEP_MODE_HW_CONTINUOUS 0x00000003
#define ADC_STEP_SAMPLE_DELAY 0xff000000
#define ADC_STEP_OPEN_DELAY 0x0003ffff
#define ADC_FIFO0COUNT 0x0e4
#define ADC_FIFO0THRESHOLD 0x0e8
+#define ADC_FIFO1COUNT 0x0f0
+#define ADC_FIFO1THRESHOLD 0x0f4
#define ADC_FIFO0DATA 0x100
+#define ADC_FIFO1DATA 0x200
#define ADC_FIFO_COUNT_MSK 0x0000007f
#define ADC_FIFO_STEP_ID_MSK 0x000f0000
#define ADC_FIFO_STEP_ID_SHIFT 16
Modified: head/sys/arm/ti/ti_adcvar.h
==============================================================================
--- head/sys/arm/ti/ti_adcvar.h Fri Apr 29 20:22:10 2016 (r298801)
+++ head/sys/arm/ti/ti_adcvar.h Fri Apr 29 20:31:49 2016 (r298802)
@@ -42,6 +42,19 @@ struct ti_adc_softc {
struct resource *sc_mem_res;
struct resource *sc_irq_res;
void *sc_intrhand;
+ int sc_tsc_wires;
+ int sc_tsc_wire_config[TI_ADC_NPINS];
+ int sc_coord_readouts;
+ int sc_x_plate_resistance;
+ int sc_charge_delay;
+ int sc_adc_nchannels;
+ int sc_adc_channels[TI_ADC_NPINS];
+ int sc_xp_bit, sc_xp_inp;
+ int sc_xn_bit, sc_xn_inp;
+ int sc_yp_bit, sc_yp_inp;
+ int sc_yn_bit, sc_yn_inp;
+ uint32_t sc_tsc_enabled;
+ int sc_pen_down;
};
struct ti_adc_input {
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