svn commit: r290213 - head/sys/mips/atheros

[Adrian Chadd]

Author: adrian
Date: Fri Oct 30 23:07:32 2015
New Revision: 290213
URL: https://svnweb.freebsd.org/changeset/base/290213

Log:
  arge: do an explicit flush between updating the TX ring and starting transmit.
  
  The MIPS busdma sync operations currently are a big no-op on coherent memory.
  This isn't strictly correct behaviour as we need a SYNC in here to ensure that
  the writes have finished and are visible in main memory before the MMIO accesses
  occur.  This will have to be addressed in a later commit.
  
  But, before that happens, let's at least do a flush here to make things
  more "correct".
  
  This is required for even remotely sensible behaviour on mips74k with
  write-through memory enabled.

Modified:
  head/sys/mips/atheros/if_arge.c

Modified: head/sys/mips/atheros/if_arge.c
==============================================================================
--- head/sys/mips/atheros/if_arge.c	Fri Oct 30 23:00:47 2015	(r290212)
+++ head/sys/mips/atheros/if_arge.c	Fri Oct 30 23:07:32 2015	(r290213)
@@ -1550,6 +1550,9 @@ arge_encap(struct arge_softc *sc, struct
 	    sc->arge_cdata.arge_tx_ring_map,
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 
+	/* Flush writes */
+	ARGE_BARRIER_WRITE(sc);
+
 	/* Start transmitting */
 	ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n",
 	    __func__);