svn commit: r279352 - head/sys/x86/x86

[Konstantin Belousov]

Author: kib
Date: Fri Feb 27 11:13:46 2015
New Revision: 279352
URL: https://svnweb.freebsd.org/changeset/base/279352

Log:
  Since all generations of Intel CPUs have errata which causes hang on
  the cache line flush in the LAPIC page, keep direct map page covering
  LAPIC mapped uncached.
  
  To have the (incomplete) check for the LAPIC range in
  pmap_invalidate_cache_range() working, lapic_paddr must be initialized
  in x2APIC mode too.
  
  Sponsored by:	The FreeBSD Foundation
  MFC after:	2 months

Modified:
  head/sys/x86/x86/local_apic.c

Modified: head/sys/x86/x86/local_apic.c
==============================================================================
--- head/sys/x86/x86/local_apic.c	Fri Feb 27 07:39:09 2015	(r279351)
+++ head/sys/x86/x86/local_apic.c	Fri Feb 27 11:13:46 2015	(r279352)
@@ -388,16 +388,21 @@ native_lapic_init(vm_paddr_t addr)
 	int i, arat;
 
 	/*
-	 * Enable x2APIC mode if possible, otherwise map the local
-	 * APIC registers page.
+	 * Enable x2APIC mode if possible. Map the local APIC
+	 * registers page.
+	 *
+	 * Keep the LAPIC registers page mapped uncached for x2APIC
+	 * mode too, to have direct map page attribute set to
+	 * uncached.  This is needed to work around CPU errata present
+	 * on all Intel processors.
 	 */
 	KASSERT(trunc_page(addr) == addr,
 	    ("local APIC not aligned on a page boundary"));
+	lapic_paddr = addr;
+	lapic_map = pmap_mapdev(addr, PAGE_SIZE);
 	if (x2apic_mode) {
 		native_lapic_enable_x2apic();
-	} else {
-		lapic_paddr = addr;
-		lapic_map = pmap_mapdev(addr, PAGE_SIZE);
+		lapic_map = NULL;
 	}
 
 	/* Setup the spurious interrupt handler. */