svn commit: r292668 - in head/sys: amd64/amd64 amd64/include i386/i386 i386/include x86/include x86/x86
John Baldwin
jhb at FreeBSD.org
Wed Dec 23 21:41:44 UTC 2015
Author: jhb
Date: Wed Dec 23 21:41:42 2015
New Revision: 292668
URL: https://svnweb.freebsd.org/changeset/base/292668
Log:
Move shared variables from {amd64,i386}/initcpu.c to x86/identcpu.c.
While here, move the common bits of <machine/cputypes.h> to
<x86/cputypes.h> as well.
Reviewed by: kib
Differential Revision: https://reviews.freebsd.org/D4670
Added:
head/sys/x86/include/cputypes.h
- copied, changed from r292667, head/sys/i386/include/cputypes.h
Modified:
head/sys/amd64/amd64/initcpu.c
head/sys/amd64/include/cputypes.h
head/sys/i386/i386/initcpu.c
head/sys/i386/include/cputypes.h
head/sys/x86/x86/identcpu.c
Modified: head/sys/amd64/amd64/initcpu.c
==============================================================================
--- head/sys/amd64/amd64/initcpu.c Wed Dec 23 20:27:23 2015 (r292667)
+++ head/sys/amd64/amd64/initcpu.c Wed Dec 23 21:41:42 2015 (r292668)
@@ -55,37 +55,6 @@ SYSCTL_INT(_hw, OID_AUTO, instruction_ss
*/
static int hw_clflush_disable = -1;
-int cpu; /* Are we 386, 386sx, 486, etc? */
-u_int cpu_feature; /* Feature flags */
-u_int cpu_feature2; /* Feature flags */
-u_int amd_feature; /* AMD feature flags */
-u_int amd_feature2; /* AMD feature flags */
-u_int amd_pminfo; /* AMD advanced power management info */
-u_int via_feature_rng; /* VIA RNG features */
-u_int via_feature_xcrypt; /* VIA ACE features */
-u_int cpu_high; /* Highest arg to CPUID */
-u_int cpu_exthigh; /* Highest arg to extended CPUID */
-u_int cpu_id; /* Stepping ID */
-u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
-u_int cpu_procinfo2; /* Multicore info */
-char cpu_vendor[20]; /* CPU Origin code */
-u_int cpu_vendor_id; /* CPU vendor ID */
-u_int cpu_fxsr; /* SSE enabled */
-u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
-u_int cpu_clflush_line_size = 32;
-u_int cpu_stdext_feature;
-u_int cpu_stdext_feature2;
-u_int cpu_max_ext_state_size;
-u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
-u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
-u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
-u_int cpu_maxphyaddr; /* Max phys addr width in bits */
-
-SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
- &via_feature_rng, 0, "VIA RNG feature available in CPU");
-SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
- &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
-
static void
init_amd(void)
{
Modified: head/sys/amd64/include/cputypes.h
==============================================================================
--- head/sys/amd64/include/cputypes.h Wed Dec 23 20:27:23 2015 (r292667)
+++ head/sys/amd64/include/cputypes.h Wed Dec 23 21:41:42 2015 (r292668)
@@ -30,6 +30,8 @@
#ifndef _MACHINE_CPUTYPES_H_
#define _MACHINE_CPUTYPES_H_
+#include <x86/cputypes.h>
+
/*
* Classes of processor.
*/
@@ -43,17 +45,4 @@
#define CPU_CLAWHAMMER 1 /* AMD Clawhammer */
#define CPU_SLEDGEHAMMER 2 /* AMD Sledgehammer */
-/*
- * Vendors of processor.
- */
-#define CPU_VENDOR_AMD 0x1022 /* AMD */
-#define CPU_VENDOR_IDT 0x111d /* Centaur/IDT/VIA */
-#define CPU_VENDOR_INTEL 0x8086 /* Intel */
-#define CPU_VENDOR_CENTAUR CPU_VENDOR_IDT
-
-#ifndef LOCORE
-extern int cpu;
-extern int cpu_class;
-#endif
-
#endif /* !_MACHINE_CPUTYPES_H_ */
Modified: head/sys/i386/i386/initcpu.c
==============================================================================
--- head/sys/i386/i386/initcpu.c Wed Dec 23 20:27:23 2015 (r292667)
+++ head/sys/i386/i386/initcpu.c Wed Dec 23 21:41:42 2015 (r292668)
@@ -81,39 +81,7 @@ SYSCTL_INT(_hw, OID_AUTO, instruction_ss
*/
static int hw_clflush_disable = -1;
-int cpu; /* Are we 386, 386sx, 486, etc? */
-u_int cpu_feature; /* Feature flags */
-u_int cpu_feature2; /* Feature flags */
-u_int amd_feature; /* AMD feature flags */
-u_int amd_feature2; /* AMD feature flags */
-u_int amd_pminfo; /* AMD advanced power management info */
-u_int via_feature_rng; /* VIA RNG features */
-u_int via_feature_xcrypt; /* VIA ACE features */
-u_int cpu_high; /* Highest arg to CPUID */
-u_int cpu_exthigh; /* Highest arg to extended CPUID */
-u_int cpu_id; /* Stepping ID */
-u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
-u_int cpu_procinfo2; /* Multicore info */
-char cpu_vendor[20]; /* CPU Origin code */
-u_int cpu_vendor_id; /* CPU vendor ID */
-#ifdef CPU_ENABLE_SSE
-u_int cpu_fxsr; /* SSE enabled */
-u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
-#endif
-u_int cpu_clflush_line_size = 32;
-u_int cpu_stdext_feature;
-u_int cpu_stdext_feature2;
-u_int cpu_max_ext_state_size;
-u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
-u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
-u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
u_int cyrix_did; /* Device ID of Cyrix CPU */
-u_int cpu_maxphyaddr; /* Max phys addr width in bits */
-
-SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
- &via_feature_rng, 0, "VIA RNG feature available in CPU");
-SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
- &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
#ifdef I486_CPU
/*
Modified: head/sys/i386/include/cputypes.h
==============================================================================
--- head/sys/i386/include/cputypes.h Wed Dec 23 20:27:23 2015 (r292667)
+++ head/sys/i386/include/cputypes.h Wed Dec 23 21:41:42 2015 (r292668)
@@ -30,6 +30,8 @@
#ifndef _MACHINE_CPUTYPES_H_
#define _MACHINE_CPUTYPES_H_
+#include <x86/cputypes.h>
+
/*
* Classes of processor.
*/
@@ -61,25 +63,4 @@
#define CPU_P4 16 /* Intel Pentium 4 */
#define CPU_GEODE1100 17 /* NS Geode SC1100 */
-/*
- * Vendors of processor.
- */
-#define CPU_VENDOR_NSC 0x100b /* NSC */
-#define CPU_VENDOR_IBM 0x1014 /* IBM */
-#define CPU_VENDOR_AMD 0x1022 /* AMD */
-#define CPU_VENDOR_SIS 0x1039 /* SiS */
-#define CPU_VENDOR_UMC 0x1060 /* UMC */
-#define CPU_VENDOR_NEXGEN 0x1074 /* Nexgen */
-#define CPU_VENDOR_CYRIX 0x1078 /* Cyrix */
-#define CPU_VENDOR_IDT 0x111d /* Centaur/IDT/VIA */
-#define CPU_VENDOR_TRANSMETA 0x1279 /* Transmeta */
-#define CPU_VENDOR_INTEL 0x8086 /* Intel */
-#define CPU_VENDOR_RISE 0xdead2bad /* Rise */
-#define CPU_VENDOR_CENTAUR CPU_VENDOR_IDT
-
-#ifndef LOCORE
-extern int cpu;
-extern int cpu_class;
-#endif
-
#endif /* !_MACHINE_CPUTYPES_H_ */
Copied and modified: head/sys/x86/include/cputypes.h (from r292667, head/sys/i386/include/cputypes.h)
==============================================================================
--- head/sys/i386/include/cputypes.h Wed Dec 23 20:27:23 2015 (r292667, copy source)
+++ head/sys/x86/include/cputypes.h Wed Dec 23 21:41:42 2015 (r292668)
@@ -27,39 +27,8 @@
* $FreeBSD$
*/
-#ifndef _MACHINE_CPUTYPES_H_
-#define _MACHINE_CPUTYPES_H_
-
-/*
- * Classes of processor.
- */
-#define CPUCLASS_286 0
-#define CPUCLASS_386 1
-#define CPUCLASS_486 2
-#define CPUCLASS_586 3
-#define CPUCLASS_686 4
-
-/*
- * Kinds of processor.
- */
-#define CPU_286 0 /* Intel 80286 */
-#define CPU_386SX 1 /* Intel 80386SX */
-#define CPU_386 2 /* Intel 80386DX */
-#define CPU_486SX 3 /* Intel 80486SX */
-#define CPU_486 4 /* Intel 80486DX */
-#define CPU_586 5 /* Intel Pentium */
-#define CPU_486DLC 6 /* Cyrix 486DLC */
-#define CPU_686 7 /* Pentium Pro */
-#define CPU_M1SC 8 /* Cyrix M1sc (aka 5x86) */
-#define CPU_M1 9 /* Cyrix M1 (aka 6x86) */
-#define CPU_BLUE 10 /* IBM BlueLighting CPU */
-#define CPU_M2 11 /* Cyrix M2 (enhanced 6x86 with MMX) */
-#define CPU_NX586 12 /* NexGen (now AMD) 586 */
-#define CPU_CY486DX 13 /* Cyrix 486S/DX/DX2/DX4 */
-#define CPU_PII 14 /* Intel Pentium II */
-#define CPU_PIII 15 /* Intel Pentium III */
-#define CPU_P4 16 /* Intel Pentium 4 */
-#define CPU_GEODE1100 17 /* NS Geode SC1100 */
+#ifndef _X86_CPUTYPES_H_
+#define _X86_CPUTYPES_H_
/*
* Vendors of processor.
@@ -82,4 +51,4 @@ extern int cpu;
extern int cpu_class;
#endif
-#endif /* !_MACHINE_CPUTYPES_H_ */
+#endif /* !_X86_CPUTYPES_H_ */
Modified: head/sys/x86/x86/identcpu.c
==============================================================================
--- head/sys/x86/x86/identcpu.c Wed Dec 23 20:27:23 2015 (r292667)
+++ head/sys/x86/x86/identcpu.c Wed Dec 23 21:41:42 2015 (r292668)
@@ -67,6 +67,10 @@ __FBSDID("$FreeBSD$");
#include <x86/vmware.h>
#ifdef __i386__
+#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
+#define CPU_ENABLE_SSE
+#endif
+
#define IDENTBLUE_CYRIX486 0
#define IDENTBLUE_IBMCPU 1
#define IDENTBLUE_CYRIXM2 2
@@ -83,9 +87,43 @@ static void print_svm_info(void);
static void print_via_padlock_info(void);
static void print_vmx_info(void);
+int cpu; /* Are we 386, 386sx, 486, etc? */
int cpu_class;
+u_int cpu_feature; /* Feature flags */
+u_int cpu_feature2; /* Feature flags */
+u_int amd_feature; /* AMD feature flags */
+u_int amd_feature2; /* AMD feature flags */
+u_int amd_pminfo; /* AMD advanced power management info */
+u_int via_feature_rng; /* VIA RNG features */
+u_int via_feature_xcrypt; /* VIA ACE features */
+u_int cpu_high; /* Highest arg to CPUID */
+u_int cpu_exthigh; /* Highest arg to extended CPUID */
+u_int cpu_id; /* Stepping ID */
+u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
+u_int cpu_procinfo2; /* Multicore info */
+char cpu_vendor[20]; /* CPU Origin code */
+u_int cpu_vendor_id; /* CPU vendor ID */
+#if defined(__amd64__) || defined(CPU_ENABLE_SSE)
+u_int cpu_fxsr; /* SSE enabled */
+u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
+#endif
+u_int cpu_clflush_line_size = 32;
+u_int cpu_stdext_feature;
+u_int cpu_stdext_feature2;
+u_int cpu_max_ext_state_size;
+u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
+u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
+u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
+u_int cpu_maxphyaddr; /* Max phys addr width in bits */
char machine[] = MACHINE;
+SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
+ &via_feature_rng, 0,
+ "VIA RNG feature available in CPU");
+SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
+ &via_feature_xcrypt, 0,
+ "VIA xcrypt feature available in CPU");
+
#ifdef __amd64__
#ifdef SCTL_MASK32
extern int adaptive_machine_arch;
More information about the svn-src-head
mailing list