svn commit: r292264 - head/sys/arm/arm

[Svatopluk Kraus]

Author: skra
Date: Tue Dec 15 13:17:40 2015
New Revision: 292264
URL: https://svnweb.freebsd.org/changeset/base/292264

Log:
  Flush intermediate TLB cache when L2 page table is unlinked.
  
  This fixes an issue observed on Cortex A7 (RPi2) and on Cortex A15
  (Jetson TK1) causing various memory corruptions. It turned out that
  even L2 page table with no valid mapping might be a subject of such
  caching.
  
  Note that not all platforms have intermediate TLB caching implemented.
  An open question is if this fix is sufficient for all platforms with
  this feature.
  
  Approved by:	kib (mentor)

Modified:
  head/sys/arm/arm/pmap-v6-new.c

Modified: head/sys/arm/arm/pmap-v6-new.c
==============================================================================
--- head/sys/arm/arm/pmap-v6-new.c	Tue Dec 15 13:04:44 2015	(r292263)
+++ head/sys/arm/arm/pmap-v6-new.c	Tue Dec 15 13:17:40 2015	(r292264)
@@ -2508,8 +2508,13 @@ pmap_unwire_pt2pg(pmap_t pmap, vm_offset
 		KASSERT(m->md.pt2_wirecount[i] == 0,
 		    ("%s: pmap %p PT2 %u (PG %p) wired", __func__, pmap, i, m));
 		opte1 = pte1_load(pte1p);
-		if (pte1_is_link(opte1))
+		if (pte1_is_link(opte1)) {
 			pte1_clear(pte1p);
+			/*
+			 * Flush intermediate TLB cache.
+			 */
+			pmap_tlb_flush(pmap, (m->pindex + i) << PTE1_SHIFT);
+		}
 #ifdef INVARIANTS
 		else
 			KASSERT((opte1 == 0) || pte1_is_section(opte1),