svn commit: r281751 - head/sys/x86/x86
marius at FreeBSD.org
Sun Apr 19 20:15:58 UTC 2015
Date: Sun Apr 19 20:15:57 2015
New Revision: 281751
Refine the workaround for Intel HSD131  added in r269052:
- Use the full mask described by the erratum as with a sufficiently high
number of these false-positives, the overflow bit (bit 62) additionally
gets set .
- HSD131 has been brought into several other Haswell-derived CPUs including
to the next generation, i. e. Intel Broadwell. Thus, also skip reporting of
these benign errors by default on CPU models affected by HSM142, HSW131 and
BDM48 [2 - 5], describing the HSD131 silicon bug for additional models.
Also, Celeron 2955U with a CPU ID of 0x45 have been reported to be covered
by this fault , with the specification update concerned with HSM142 
only referring to 0x3c and 0x46.
Submitted by: David Froehlich 
MFC after: 3 days
--- head/sys/x86/x86/mca.c Sun Apr 19 20:08:36 2015 (r281750)
+++ head/sys/x86/x86/mca.c Sun Apr 19 20:15:57 2015 (r281751)
@@ -251,15 +251,24 @@ mca_mute(const struct mca_record *rec)
- * Skip spurious corrected parity errors generated by desktop Haswell
- * (see HSD131 erratum) unless reporting is enabled.
- * Note that these errors also have been observed with D0-stepping,
- * while the revision 014 desktop Haswell specification update only
- * talks about C0-stepping.
+ * Skip spurious corrected parity errors generated by Intel Haswell-
+ * and Broadwell-based CPUs (see HSD131, HSM142, HSW131 and BDM48
+ * erratum respectively), unless reporting is enabled.
+ * Note that these errors also have been observed with the D0-stepping
+ * of Haswell, while at least initially the CPU specification updates
+ * suggested only the C0-stepping to be affected. Similarly, Celeron
+ * 2955U with a CPU ID of 0x45 apparently are also concerned with the
+ * same problem, with HSM142 only referring to 0x3c and 0x46.
- if (rec->mr_cpu_vendor_id == CPU_VENDOR_INTEL &&
- rec->mr_cpu_id == 0x306c3 && rec->mr_bank == 0 &&
- rec->mr_status == 0x90000040000f0005 && !intel6h_HSD131)
+ if (cpu_vendor_id == CPU_VENDOR_INTEL &&
+ CPUID_TO_FAMILY(cpu_id) == 0x6 &&
+ (CPUID_TO_MODEL(cpu_id) == 0x3c || /* HSD131, HSM142, HSW131 */
+ CPUID_TO_MODEL(cpu_id) == 0x3d || /* BDM48 */
+ CPUID_TO_MODEL(cpu_id) == 0x45 ||
+ CPUID_TO_MODEL(cpu_id) == 0x46) && /* HSM142 */
+ rec->mr_bank == 0 &&
+ (rec->mr_status & 0xa0000000ffffffff) == 0x80000000000f0005 &&
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