svn commit: r271405 - in head/sys: i386/i386 i386/include x86/x86

[John Baldwin]

Author: jhb
Date: Wed Sep 10 21:04:44 2014
New Revision: 271405
URL: http://svnweb.freebsd.org/changeset/base/271405

Log:
  Move code to set various MSRs on AMD cpus out of printcpuinfo() and
  into initalizecpu() instead.

Modified:
  head/sys/i386/i386/initcpu.c
  head/sys/i386/include/md_var.h
  head/sys/x86/x86/identcpu.c

Modified: head/sys/i386/i386/initcpu.c
==============================================================================
--- head/sys/i386/i386/initcpu.c	Wed Sep 10 20:23:10 2014	(r271404)
+++ head/sys/i386/i386/initcpu.c	Wed Sep 10 21:04:44 2014	(r271405)
@@ -59,6 +59,12 @@ static void init_i486_on_386(void);
 static void init_6x86(void);
 #endif /* I486_CPU */
 
+#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
+static void	enable_K5_wt_alloc(void);
+static void	enable_K6_wt_alloc(void);
+static void	enable_K6_2_wt_alloc(void);
+#endif
+
 #ifdef I686_CPU
 static void	init_6x86MX(void);
 static void	init_ppro(void);
@@ -692,6 +698,27 @@ initializecpu(void)
 #ifdef I586_CPU
 	case CPU_586:
 		switch (cpu_vendor_id) {
+		case CPU_VENDOR_AMD:
+#ifdef CPU_WT_ALLOC
+			if (((cpu_id & 0x0f0) > 0) &&
+			    ((cpu_id & 0x0f0) < 0x60) &&
+			    ((cpu_id & 0x00f) > 3))
+				enable_K5_wt_alloc();
+			else if (((cpu_id & 0x0f0) > 0x80) ||
+			    (((cpu_id & 0x0f0) == 0x80) &&
+				(cpu_id & 0x00f) > 0x07))
+				enable_K6_2_wt_alloc();
+			else if ((cpu_id & 0x0f0) > 0x50)
+				enable_K6_wt_alloc();
+#endif
+			if ((cpu_id & 0xf0) == 0xa0)
+				/*
+				 * Make sure the TSC runs through
+				 * suspension, otherwise we can't use
+				 * it as timecounter
+				 */
+				wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
+			break;
 		case CPU_VENDOR_CENTAUR:
 			init_winchip();
 			break;
@@ -839,7 +866,7 @@ initializecpu(void)
  * Enable write allocate feature of AMD processors.
  * Following two functions require the Maxmem variable being set.
  */
-void
+static void
 enable_K5_wt_alloc(void)
 {
 	u_int64_t	msr;
@@ -885,7 +912,7 @@ enable_K5_wt_alloc(void)
 	}
 }
 
-void
+static void
 enable_K6_wt_alloc(void)
 {
 	quad_t	size;
@@ -945,7 +972,7 @@ enable_K6_wt_alloc(void)
 	intr_restore(saveintr);
 }
 
-void
+static void
 enable_K6_2_wt_alloc(void)
 {
 	quad_t	size;

Modified: head/sys/i386/include/md_var.h
==============================================================================
--- head/sys/i386/include/md_var.h	Wed Sep 10 20:23:10 2014	(r271404)
+++ head/sys/i386/include/md_var.h	Wed Sep 10 21:04:44 2014	(r271405)
@@ -99,11 +99,6 @@ void	doreti_popl_fs_fault(void) __asm(__
 void	dump_add_page(vm_paddr_t);
 void	dump_drop_page(vm_paddr_t);
 void	finishidentcpu(void);
-#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
-void	enable_K5_wt_alloc(void);
-void	enable_K6_wt_alloc(void);
-void	enable_K6_2_wt_alloc(void);
-#endif
 void	enable_sse(void);
 void	fillw(int /*u_short*/ pat, void *base, size_t cnt);
 void	initializecpu(void);

Modified: head/sys/x86/x86/identcpu.c
==============================================================================
--- head/sys/x86/x86/identcpu.c	Wed Sep 10 20:23:10 2014	(r271404)
+++ head/sys/x86/x86/identcpu.c	Wed Sep 10 21:04:44 2014	(r271405)
@@ -405,30 +405,11 @@ printcpuinfo(void)
 			break;
 		case 0x5a0:
 			strcat(cpu_model, "Geode LX");
-			/*
-			 * Make sure the TSC runs through suspension,
-			 * otherwise we can't use it as timecounter
-			 */
-			wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
 			break;
 		default:
 			strcat(cpu_model, "Unknown");
 			break;
 		}
-#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
-		if ((cpu_id & 0xf00) == 0x500) {
-			if (((cpu_id & 0x0f0) > 0)
-			    && ((cpu_id & 0x0f0) < 0x60)
-			    && ((cpu_id & 0x00f) > 3))
-				enable_K5_wt_alloc();
-			else if (((cpu_id & 0x0f0) > 0x80)
-				 || (((cpu_id & 0x0f0) == 0x80)
-				     && (cpu_id & 0x00f) > 0x07))
-				enable_K6_2_wt_alloc();
-			else if ((cpu_id & 0x0f0) > 0x50)
-				enable_K6_wt_alloc();
-		}
-#endif
 #else
 		if ((cpu_id & 0xf00) == 0xf00)
 			strcat(cpu_model, "AMD64 Processor");