svn commit: r263251 - head/sys/arm/arm

[Ian Lepore]

Author: ian
Date: Sun Mar 16 20:39:39 2014
New Revision: 263251
URL: http://svnweb.freebsd.org/changeset/base/263251

Log:
  Use armv7 TLB flush code, not arm11, for cortex-a processors.
  
  The armv7 architecture uses a unified TLB model for maintenence ops even
  if separate instruction and data TLBs are implemented in hardware.  That
  means that there's no distinction between the 'I' and 'D' flavors of flush,
  they all use the same 'ID' implementation.  On the other hand, there is a
  difference between SMP and UP on armv7, but not on arm11, so use the armv7
  routines for cortex-a processors.

Modified:
  head/sys/arm/arm/cpufunc.c

Modified: head/sys/arm/arm/cpufunc.c
==============================================================================
--- head/sys/arm/arm/cpufunc.c	Sun Mar 16 20:34:45 2014	(r263250)
+++ head/sys/arm/arm/cpufunc.c	Sun Mar 16 20:39:39 2014	(r263251)
@@ -754,14 +754,18 @@ struct cpu_functions cortexa_cpufuncs = 
 	cpufunc_faultstatus,            /* Faultstatus          */
 	cpufunc_faultaddress,           /* Faultaddress         */
 	
-	/* TLB functions */
+	/* 
+	 * TLB functions.  ARMv7 does all TLB ops based on a unified TLB model
+	 * whether the hardware implements separate I+D or not, so we use the
+	 * same 'ID' functions for all 3 variations.
+	 */
 	
 	armv7_tlb_flushID,              /* tlb_flushID          */
 	armv7_tlb_flushID_SE,           /* tlb_flushID_SE       */
-	arm11_tlb_flushI,               /* tlb_flushI           */
-	arm11_tlb_flushI_SE,            /* tlb_flushI_SE        */
-	arm11_tlb_flushD,               /* tlb_flushD           */
-	arm11_tlb_flushD_SE,            /* tlb_flushD_SE        */
+	armv7_tlb_flushID,              /* tlb_flushI           */
+	armv7_tlb_flushID_SE,           /* tlb_flushI_SE        */
+	armv7_tlb_flushID,              /* tlb_flushD           */
+	armv7_tlb_flushID_SE,           /* tlb_flushD_SE        */
 	
 	/* Cache operations */