svn commit: r262958 - in head/sys: arm/arm arm/conf arm/include arm/sa11x0 arm/xscale/pxa conf
Ian Lepore
ian at FreeBSD.org
Sun Mar 9 21:12:31 UTC 2014
Author: ian
Date: Sun Mar 9 21:12:31 2014
New Revision: 262958
URL: http://svnweb.freebsd.org/changeset/base/262958
Log:
Remove all traces of support for ARM chips prior to the arm9 series. We
never actually ran on these chips (other than using SA1 support in an
emulator to do the early porting to FreeBSD long long ago). The clutter
and complexity of some of this code keeps getting in the way of other
maintenance, so it's time to go.
Deleted:
head/sys/arm/arm/cpufunc_asm_arm7tdmi.S
head/sys/arm/arm/cpufunc_asm_arm8.S
head/sys/arm/arm/cpufunc_asm_ixp12x0.S
head/sys/arm/arm/cpufunc_asm_sa1.S
head/sys/arm/arm/cpufunc_asm_sa11x0.S
head/sys/arm/conf/SIMICS
head/sys/arm/sa11x0/
Modified:
head/sys/arm/arm/cpufunc.c
head/sys/arm/arm/elf_trampoline.c
head/sys/arm/arm/identcpu.c
head/sys/arm/arm/pmap.c
head/sys/arm/arm/trap.c
head/sys/arm/conf/NOTES
head/sys/arm/include/armreg.h
head/sys/arm/include/cpuconf.h
head/sys/arm/include/cpufunc.h
head/sys/arm/include/md_var.h
head/sys/arm/include/param.h
head/sys/arm/include/pmap.h
head/sys/arm/xscale/pxa/pxareg.h
head/sys/conf/Makefile.arm
head/sys/conf/files.arm
head/sys/conf/options.arm
Modified: head/sys/arm/arm/cpufunc.c
==============================================================================
--- head/sys/arm/arm/cpufunc.c Sun Mar 9 21:06:22 2014 (r262957)
+++ head/sys/arm/arm/cpufunc.c Sun Mar 9 21:12:31 2014 (r262958)
@@ -1,9 +1,6 @@
/* $NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $ */
/*-
- * arm7tdmi support code Copyright (c) 2001 John Fremlin
- * arm8 support code Copyright (c) 1997 ARM Limited
- * arm8 support code Copyright (c) 1997 Causality Limited
* arm9 support code Copyright (C) 2001 ARM Ltd
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
@@ -112,131 +109,6 @@ u_int arm_cache_loc;
int cpu_do_powersave;
int ctrl;
-#ifdef CPU_ARM7TDMI
-struct cpu_functions arm7tdmi_cpufuncs = {
- /* CPU functions */
-
- cpufunc_id, /* id */
- cpufunc_nullop, /* cpwait */
-
- /* MMU functions */
-
- cpufunc_control, /* control */
- cpufunc_domains, /* domain */
- arm7tdmi_setttb, /* setttb */
- cpufunc_faultstatus, /* faultstatus */
- cpufunc_faultaddress, /* faultaddress */
-
- /* TLB functions */
-
- arm7tdmi_tlb_flushID, /* tlb_flushID */
- arm7tdmi_tlb_flushID_SE, /* tlb_flushID_SE */
- arm7tdmi_tlb_flushID, /* tlb_flushI */
- arm7tdmi_tlb_flushID_SE, /* tlb_flushI_SE */
- arm7tdmi_tlb_flushID, /* tlb_flushD */
- arm7tdmi_tlb_flushID_SE, /* tlb_flushD_SE */
-
- /* Cache operations */
-
- cpufunc_nullop, /* icache_sync_all */
- (void *)cpufunc_nullop, /* icache_sync_range */
-
- arm7tdmi_cache_flushID, /* dcache_wbinv_all */
- (void *)arm7tdmi_cache_flushID, /* dcache_wbinv_range */
- (void *)arm7tdmi_cache_flushID, /* dcache_inv_range */
- (void *)cpufunc_nullop, /* dcache_wb_range */
-
- cpufunc_nullop, /* idcache_inv_all */
- arm7tdmi_cache_flushID, /* idcache_wbinv_all */
- (void *)arm7tdmi_cache_flushID, /* idcache_wbinv_range */
- cpufunc_nullop, /* l2cache_wbinv_all */
- (void *)cpufunc_nullop, /* l2cache_wbinv_range */
- (void *)cpufunc_nullop, /* l2cache_inv_range */
- (void *)cpufunc_nullop, /* l2cache_wb_range */
-
- /* Other functions */
-
- cpufunc_nullop, /* flush_prefetchbuf */
- cpufunc_nullop, /* drain_writebuf */
- cpufunc_nullop, /* flush_brnchtgt_C */
- (void *)cpufunc_nullop, /* flush_brnchtgt_E */
-
- (void *)cpufunc_nullop, /* sleep */
-
- /* Soft functions */
-
- late_abort_fixup, /* dataabt_fixup */
- cpufunc_null_fixup, /* prefetchabt_fixup */
-
- arm7tdmi_context_switch, /* context_switch */
-
- arm7tdmi_setup /* cpu setup */
-
-};
-#endif /* CPU_ARM7TDMI */
-
-#ifdef CPU_ARM8
-struct cpu_functions arm8_cpufuncs = {
- /* CPU functions */
-
- cpufunc_id, /* id */
- cpufunc_nullop, /* cpwait */
-
- /* MMU functions */
-
- cpufunc_control, /* control */
- cpufunc_domains, /* domain */
- arm8_setttb, /* setttb */
- cpufunc_faultstatus, /* faultstatus */
- cpufunc_faultaddress, /* faultaddress */
-
- /* TLB functions */
-
- arm8_tlb_flushID, /* tlb_flushID */
- arm8_tlb_flushID_SE, /* tlb_flushID_SE */
- arm8_tlb_flushID, /* tlb_flushI */
- arm8_tlb_flushID_SE, /* tlb_flushI_SE */
- arm8_tlb_flushID, /* tlb_flushD */
- arm8_tlb_flushID_SE, /* tlb_flushD_SE */
-
- /* Cache operations */
-
- cpufunc_nullop, /* icache_sync_all */
- (void *)cpufunc_nullop, /* icache_sync_range */
-
- arm8_cache_purgeID, /* dcache_wbinv_all */
- (void *)arm8_cache_purgeID, /* dcache_wbinv_range */
-/*XXX*/ (void *)arm8_cache_purgeID, /* dcache_inv_range */
- (void *)arm8_cache_cleanID, /* dcache_wb_range */
-
- cpufunc_nullop, /* idcache_inv_all */
- arm8_cache_purgeID, /* idcache_wbinv_all */
- (void *)arm8_cache_purgeID, /* idcache_wbinv_range */
- cpufunc_nullop, /* l2cache_wbinv_all */
- (void *)cpufunc_nullop, /* l2cache_wbinv_range */
- (void *)cpufunc_nullop, /* l2cache_inv_range */
- (void *)cpufunc_nullop, /* l2cache_wb_range */
-
- /* Other functions */
-
- cpufunc_nullop, /* flush_prefetchbuf */
- cpufunc_nullop, /* drain_writebuf */
- cpufunc_nullop, /* flush_brnchtgt_C */
- (void *)cpufunc_nullop, /* flush_brnchtgt_E */
-
- (void *)cpufunc_nullop, /* sleep */
-
- /* Soft functions */
-
- cpufunc_null_fixup, /* dataabt_fixup */
- cpufunc_null_fixup, /* prefetchabt_fixup */
-
- arm8_context_switch, /* context_switch */
-
- arm8_setup /* cpu setup */
-};
-#endif /* CPU_ARM8 */
-
#ifdef CPU_ARM9
struct cpu_functions arm9_cpufuncs = {
/* CPU functions */
@@ -550,192 +422,6 @@ struct cpu_functions pj4bv7_cpufuncs = {
};
#endif /* CPU_MV_PJ4B */
-#ifdef CPU_SA110
-struct cpu_functions sa110_cpufuncs = {
- /* CPU functions */
-
- cpufunc_id, /* id */
- cpufunc_nullop, /* cpwait */
-
- /* MMU functions */
-
- cpufunc_control, /* control */
- cpufunc_domains, /* domain */
- sa1_setttb, /* setttb */
- cpufunc_faultstatus, /* faultstatus */
- cpufunc_faultaddress, /* faultaddress */
-
- /* TLB functions */
-
- armv4_tlb_flushID, /* tlb_flushID */
- sa1_tlb_flushID_SE, /* tlb_flushID_SE */
- armv4_tlb_flushI, /* tlb_flushI */
- (void *)armv4_tlb_flushI, /* tlb_flushI_SE */
- armv4_tlb_flushD, /* tlb_flushD */
- armv4_tlb_flushD_SE, /* tlb_flushD_SE */
-
- /* Cache operations */
-
- sa1_cache_syncI, /* icache_sync_all */
- sa1_cache_syncI_rng, /* icache_sync_range */
-
- sa1_cache_purgeD, /* dcache_wbinv_all */
- sa1_cache_purgeD_rng, /* dcache_wbinv_range */
-/*XXX*/ sa1_cache_purgeD_rng, /* dcache_inv_range */
- sa1_cache_cleanD_rng, /* dcache_wb_range */
-
- sa1_cache_flushID, /* idcache_inv_all */
- sa1_cache_purgeID, /* idcache_wbinv_all */
- sa1_cache_purgeID_rng, /* idcache_wbinv_range */
- cpufunc_nullop, /* l2cache_wbinv_all */
- (void *)cpufunc_nullop, /* l2cache_wbinv_range */
- (void *)cpufunc_nullop, /* l2cache_inv_range */
- (void *)cpufunc_nullop, /* l2cache_wb_range */
-
- /* Other functions */
-
- cpufunc_nullop, /* flush_prefetchbuf */
- armv4_drain_writebuf, /* drain_writebuf */
- cpufunc_nullop, /* flush_brnchtgt_C */
- (void *)cpufunc_nullop, /* flush_brnchtgt_E */
-
- (void *)cpufunc_nullop, /* sleep */
-
- /* Soft functions */
-
- cpufunc_null_fixup, /* dataabt_fixup */
- cpufunc_null_fixup, /* prefetchabt_fixup */
-
- sa110_context_switch, /* context_switch */
-
- sa110_setup /* cpu setup */
-};
-#endif /* CPU_SA110 */
-
-#if defined(CPU_SA1100) || defined(CPU_SA1110)
-struct cpu_functions sa11x0_cpufuncs = {
- /* CPU functions */
-
- cpufunc_id, /* id */
- cpufunc_nullop, /* cpwait */
-
- /* MMU functions */
-
- cpufunc_control, /* control */
- cpufunc_domains, /* domain */
- sa1_setttb, /* setttb */
- cpufunc_faultstatus, /* faultstatus */
- cpufunc_faultaddress, /* faultaddress */
-
- /* TLB functions */
-
- armv4_tlb_flushID, /* tlb_flushID */
- sa1_tlb_flushID_SE, /* tlb_flushID_SE */
- armv4_tlb_flushI, /* tlb_flushI */
- (void *)armv4_tlb_flushI, /* tlb_flushI_SE */
- armv4_tlb_flushD, /* tlb_flushD */
- armv4_tlb_flushD_SE, /* tlb_flushD_SE */
-
- /* Cache operations */
-
- sa1_cache_syncI, /* icache_sync_all */
- sa1_cache_syncI_rng, /* icache_sync_range */
-
- sa1_cache_purgeD, /* dcache_wbinv_all */
- sa1_cache_purgeD_rng, /* dcache_wbinv_range */
-/*XXX*/ sa1_cache_purgeD_rng, /* dcache_inv_range */
- sa1_cache_cleanD_rng, /* dcache_wb_range */
-
- sa1_cache_flushID, /* idcache_inv_all */
- sa1_cache_purgeID, /* idcache_wbinv_all */
- sa1_cache_purgeID_rng, /* idcache_wbinv_range */
- cpufunc_nullop, /* l2cache_wbinv_all */
- (void *)cpufunc_nullop, /* l2cache_wbinv_range */
- (void *)cpufunc_nullop, /* l2cache_inv_range */
- (void *)cpufunc_nullop, /* l2cache_wb_range */
-
- /* Other functions */
-
- sa11x0_drain_readbuf, /* flush_prefetchbuf */
- armv4_drain_writebuf, /* drain_writebuf */
- cpufunc_nullop, /* flush_brnchtgt_C */
- (void *)cpufunc_nullop, /* flush_brnchtgt_E */
-
- sa11x0_cpu_sleep, /* sleep */
-
- /* Soft functions */
-
- cpufunc_null_fixup, /* dataabt_fixup */
- cpufunc_null_fixup, /* prefetchabt_fixup */
-
- sa11x0_context_switch, /* context_switch */
-
- sa11x0_setup /* cpu setup */
-};
-#endif /* CPU_SA1100 || CPU_SA1110 */
-
-#ifdef CPU_IXP12X0
-struct cpu_functions ixp12x0_cpufuncs = {
- /* CPU functions */
-
- cpufunc_id, /* id */
- cpufunc_nullop, /* cpwait */
-
- /* MMU functions */
-
- cpufunc_control, /* control */
- cpufunc_domains, /* domain */
- sa1_setttb, /* setttb */
- cpufunc_faultstatus, /* faultstatus */
- cpufunc_faultaddress, /* faultaddress */
-
- /* TLB functions */
-
- armv4_tlb_flushID, /* tlb_flushID */
- sa1_tlb_flushID_SE, /* tlb_flushID_SE */
- armv4_tlb_flushI, /* tlb_flushI */
- (void *)armv4_tlb_flushI, /* tlb_flushI_SE */
- armv4_tlb_flushD, /* tlb_flushD */
- armv4_tlb_flushD_SE, /* tlb_flushD_SE */
-
- /* Cache operations */
-
- sa1_cache_syncI, /* icache_sync_all */
- sa1_cache_syncI_rng, /* icache_sync_range */
-
- sa1_cache_purgeD, /* dcache_wbinv_all */
- sa1_cache_purgeD_rng, /* dcache_wbinv_range */
-/*XXX*/ sa1_cache_purgeD_rng, /* dcache_inv_range */
- sa1_cache_cleanD_rng, /* dcache_wb_range */
-
- sa1_cache_flushID, /* idcache_inv_all */
- sa1_cache_purgeID, /* idcache_wbinv_all */
- sa1_cache_purgeID_rng, /* idcache_wbinv_range */
- cpufunc_nullop, /* l2cache_wbinv_all */
- (void *)cpufunc_nullop, /* l2cache_wbinv_range */
- (void *)cpufunc_nullop, /* l2cache_inv_range */
- (void *)cpufunc_nullop, /* l2cache_wb_range */
-
- /* Other functions */
-
- ixp12x0_drain_readbuf, /* flush_prefetchbuf */
- armv4_drain_writebuf, /* drain_writebuf */
- cpufunc_nullop, /* flush_brnchtgt_C */
- (void *)cpufunc_nullop, /* flush_brnchtgt_E */
-
- (void *)cpufunc_nullop, /* sleep */
-
- /* Soft functions */
-
- cpufunc_null_fixup, /* dataabt_fixup */
- cpufunc_null_fixup, /* prefetchabt_fixup */
-
- ixp12x0_context_switch, /* context_switch */
-
- ixp12x0_setup /* cpu setup */
-};
-#endif /* CPU_IXP12X0 */
-
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219)
@@ -1128,7 +814,7 @@ struct cpu_functions cpufuncs;
u_int cputype;
u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
-#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
+#if defined(CPU_ARM9) || \
defined (CPU_ARM9E) || defined (CPU_ARM10) || defined (CPU_ARM1136) || \
defined(CPU_ARM1176) || defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
@@ -1247,61 +933,7 @@ get_cachetype_cp15()
arm_dcache_align_mask = arm_dcache_align - 1;
}
}
-#endif /* ARM7TDMI || ARM8 || ARM9 || XSCALE */
-
-#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
- defined(CPU_IXP12X0)
-/* Cache information for CPUs without cache type registers. */
-struct cachetab {
- u_int32_t ct_cpuid;
- int ct_pcache_type;
- int ct_pcache_unified;
- int ct_pdcache_size;
- int ct_pdcache_line_size;
- int ct_pdcache_ways;
- int ct_picache_size;
- int ct_picache_line_size;
- int ct_picache_ways;
-};
-
-struct cachetab cachetab[] = {
- /* cpuid, cache type, u, dsiz, ls, wy, isiz, ls, wy */
- /* XXX is this type right for SA-1? */
- { CPU_ID_SA110, CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32, 32 },
- { CPU_ID_SA1100, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 },
- { CPU_ID_SA1110, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 },
- { CPU_ID_IXP1200, CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32, 32 }, /* XXX */
- { 0, 0, 0, 0, 0, 0, 0, 0}
-};
-
-static void get_cachetype_table(void);
-
-static void
-get_cachetype_table()
-{
- int i;
- u_int32_t cpuid = cpufunc_id();
-
- for (i = 0; cachetab[i].ct_cpuid != 0; i++) {
- if (cachetab[i].ct_cpuid == (cpuid & CPU_ID_CPU_MASK)) {
- arm_pcache_type = cachetab[i].ct_pcache_type;
- arm_pcache_unified = cachetab[i].ct_pcache_unified;
- arm_pdcache_size = cachetab[i].ct_pdcache_size;
- arm_pdcache_line_size =
- cachetab[i].ct_pdcache_line_size;
- arm_pdcache_ways = cachetab[i].ct_pdcache_ways;
- arm_picache_size = cachetab[i].ct_picache_size;
- arm_picache_line_size =
- cachetab[i].ct_picache_line_size;
- arm_picache_ways = cachetab[i].ct_picache_ways;
- }
- }
- arm_dcache_align = arm_pdcache_line_size;
-
- arm_dcache_align_mask = arm_dcache_align - 1;
-}
-
-#endif /* SA110 || SA1100 || SA1111 || IXP12X0 */
+#endif /* ARM9 || XSCALE */
/*
* Cannot panic here as we may not have a console yet ...
@@ -1318,27 +950,6 @@ set_cpufuncs()
* CPU type where we want to use it by default, then we set it.
*/
-#ifdef CPU_ARM7TDMI
- if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
- CPU_ID_IS7(cputype) &&
- (cputype & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V4T) {
- cpufuncs = arm7tdmi_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 0;
- get_cachetype_cp15();
- pmap_pte_init_generic();
- goto out;
- }
-#endif
-#ifdef CPU_ARM8
- if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
- (cputype & 0x0000f000) == 0x00008000) {
- cpufuncs = arm8_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 0; /* XXX correct? */
- get_cachetype_cp15();
- pmap_pte_init_arm8();
- goto out;
- }
-#endif /* CPU_ARM8 */
#ifdef CPU_ARM9
if (((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD ||
(cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_TI) &&
@@ -1464,39 +1075,7 @@ set_cpufuncs()
goto out;
}
#endif /* CPU_MV_PJ4B */
-#ifdef CPU_SA110
- if (cputype == CPU_ID_SA110) {
- cpufuncs = sa110_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
- get_cachetype_table();
- pmap_pte_init_sa1();
- goto out;
- }
-#endif /* CPU_SA110 */
-#ifdef CPU_SA1100
- if (cputype == CPU_ID_SA1100) {
- cpufuncs = sa11x0_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
- get_cachetype_table();
- pmap_pte_init_sa1();
- /* Use powersave on this CPU. */
- cpu_do_powersave = 1;
-
- goto out;
- }
-#endif /* CPU_SA1100 */
-#ifdef CPU_SA1110
- if (cputype == CPU_ID_SA1110) {
- cpufuncs = sa11x0_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
- get_cachetype_table();
- pmap_pte_init_sa1();
- /* Use powersave on this CPU. */
- cpu_do_powersave = 1;
- goto out;
- }
-#endif /* CPU_SA1110 */
#if defined(CPU_FA526) || defined(CPU_FA626TE)
if (cputype == CPU_ID_FA526 || cputype == CPU_ID_FA626TE) {
cpufuncs = fa526_cpufuncs;
@@ -1510,15 +1089,7 @@ set_cpufuncs()
goto out;
}
#endif /* CPU_FA526 || CPU_FA626TE */
-#ifdef CPU_IXP12X0
- if (cputype == CPU_ID_IXP1200) {
- cpufuncs = ixp12x0_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1;
- get_cachetype_table();
- pmap_pte_init_sa1();
- goto out;
- }
-#endif /* CPU_IXP12X0 */
+
#ifdef CPU_XSCALE_80200
if (cputype == CPU_ID_80200) {
int rev = cpufunc_id() & CPU_ID_REVISION_MASK;
@@ -1627,8 +1198,6 @@ out:
*
* DEBUG_FAULT_CORRECTION - Print debugging information during the
* correction of registers after a fault.
- * ARM6_LATE_ABORT - ARM6 supports both early and late aborts
- * when defined should use late aborts
*/
@@ -1643,344 +1212,12 @@ cpufunc_null_fixup(arg)
return(ABORT_FIXUP_OK);
}
-
-#if defined(CPU_ARM7TDMI)
-
-#ifdef DEBUG_FAULT_CORRECTION
-#define DFC_PRINTF(x) printf x
-#define DFC_DISASSEMBLE(x) disassemble(x)
-#else
-#define DFC_PRINTF(x) /* nothing */
-#define DFC_DISASSEMBLE(x) /* nothing */
-#endif
-
/*
- * "Early" data abort fixup.
- *
- * For ARM2, ARM2as, ARM3 and ARM6 (in early-abort mode). Also used
- * indirectly by ARM6 (in late-abort mode) and ARM7[TDMI].
- *
- * In early aborts, we may have to fix up LDM, STM, LDC and STC.
+ * CPU Setup code
*/
-int
-early_abort_fixup(arg)
- void *arg;
-{
- struct trapframe *frame = arg;
- u_int fault_pc;
- u_int fault_instruction;
- int saved_lr = 0;
-
- if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
-
- /* Ok an abort in SVC mode */
-
- /*
- * Copy the SVC r14 into the usr r14 - The usr r14 is garbage
- * as the fault happened in svc mode but we need it in the
- * usr slot so we can treat the registers as an array of ints
- * during fixing.
- * NOTE: This PC is in the position but writeback is not
- * allowed on r15.
- * Doing it like this is more efficient than trapping this
- * case in all possible locations in the following fixup code.
- */
-
- saved_lr = frame->tf_usr_lr;
- frame->tf_usr_lr = frame->tf_svc_lr;
-
- /*
- * Note the trapframe does not have the SVC r13 so a fault
- * from an instruction with writeback to r13 in SVC mode is
- * not allowed. This should not happen as the kstack is
- * always valid.
- */
- }
-
- /* Get fault address and status from the CPU */
-
- fault_pc = frame->tf_pc;
- fault_instruction = *((volatile unsigned int *)fault_pc);
-
- /* Decode the fault instruction and fix the registers as needed */
-
- if ((fault_instruction & 0x0e000000) == 0x08000000) {
- int base;
- int loop;
- int count;
- int *registers = &frame->tf_r0;
-
- DFC_PRINTF(("LDM/STM\n"));
- DFC_DISASSEMBLE(fault_pc);
- if (fault_instruction & (1 << 21)) {
- DFC_PRINTF(("This instruction must be corrected\n"));
- base = (fault_instruction >> 16) & 0x0f;
- if (base == 15)
- return ABORT_FIXUP_FAILED;
- /* Count registers transferred */
- count = 0;
- for (loop = 0; loop < 16; ++loop) {
- if (fault_instruction & (1<<loop))
- ++count;
- }
- DFC_PRINTF(("%d registers used\n", count));
- DFC_PRINTF(("Corrected r%d by %d bytes ",
- base, count * 4));
- if (fault_instruction & (1 << 23)) {
- DFC_PRINTF(("down\n"));
- registers[base] -= count * 4;
- } else {
- DFC_PRINTF(("up\n"));
- registers[base] += count * 4;
- }
- }
- } else if ((fault_instruction & 0x0e000000) == 0x0c000000) {
- int base;
- int offset;
- int *registers = &frame->tf_r0;
-
- /* REGISTER CORRECTION IS REQUIRED FOR THESE INSTRUCTIONS */
-
- DFC_DISASSEMBLE(fault_pc);
-
- /* Only need to fix registers if write back is turned on */
-
- if ((fault_instruction & (1 << 21)) != 0) {
- base = (fault_instruction >> 16) & 0x0f;
- if (base == 13 &&
- (frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE)
- return ABORT_FIXUP_FAILED;
- if (base == 15)
- return ABORT_FIXUP_FAILED;
-
- offset = (fault_instruction & 0xff) << 2;
- DFC_PRINTF(("r%d=%08x\n", base, registers[base]));
- if ((fault_instruction & (1 << 23)) != 0)
- offset = -offset;
- registers[base] += offset;
- DFC_PRINTF(("r%d=%08x\n", base, registers[base]));
- }
- } else if ((fault_instruction & 0x0e000000) == 0x0c000000)
- return ABORT_FIXUP_FAILED;
-
- if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
-
- /* Ok an abort in SVC mode */
-
- /*
- * Copy the SVC r14 into the usr r14 - The usr r14 is garbage
- * as the fault happened in svc mode but we need it in the
- * usr slot so we can treat the registers as an array of ints
- * during fixing.
- * NOTE: This PC is in the position but writeback is not
- * allowed on r15.
- * Doing it like this is more efficient than trapping this
- * case in all possible locations in the prior fixup code.
- */
-
- frame->tf_svc_lr = frame->tf_usr_lr;
- frame->tf_usr_lr = saved_lr;
-
- /*
- * Note the trapframe does not have the SVC r13 so a fault
- * from an instruction with writeback to r13 in SVC mode is
- * not allowed. This should not happen as the kstack is
- * always valid.
- */
- }
-
- return(ABORT_FIXUP_OK);
-}
-#endif /* CPU_ARM2/250/3/6/7 */
-
-
-#if defined(CPU_ARM7TDMI)
-/*
- * "Late" (base updated) data abort fixup
- *
- * For ARM6 (in late-abort mode) and ARM7.
- *
- * In this model, all data-transfer instructions need fixing up. We defer
- * LDM, STM, LDC and STC fixup to the early-abort handler.
- */
-int
-late_abort_fixup(arg)
- void *arg;
-{
- struct trapframe *frame = arg;
- u_int fault_pc;
- u_int fault_instruction;
- int saved_lr = 0;
-
- if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
-
- /* Ok an abort in SVC mode */
-
- /*
- * Copy the SVC r14 into the usr r14 - The usr r14 is garbage
- * as the fault happened in svc mode but we need it in the
- * usr slot so we can treat the registers as an array of ints
- * during fixing.
- * NOTE: This PC is in the position but writeback is not
- * allowed on r15.
- * Doing it like this is more efficient than trapping this
- * case in all possible locations in the following fixup code.
- */
-
- saved_lr = frame->tf_usr_lr;
- frame->tf_usr_lr = frame->tf_svc_lr;
-
- /*
- * Note the trapframe does not have the SVC r13 so a fault
- * from an instruction with writeback to r13 in SVC mode is
- * not allowed. This should not happen as the kstack is
- * always valid.
- */
- }
-
- /* Get fault address and status from the CPU */
-
- fault_pc = frame->tf_pc;
- fault_instruction = *((volatile unsigned int *)fault_pc);
-
- /* Decode the fault instruction and fix the registers as needed */
-
- /* Was is a swap instruction ? */
- if ((fault_instruction & 0x0fb00ff0) == 0x01000090) {
- DFC_DISASSEMBLE(fault_pc);
- } else if ((fault_instruction & 0x0c000000) == 0x04000000) {
-
- /* Was is a ldr/str instruction */
- /* This is for late abort only */
-
- int base;
- int offset;
- int *registers = &frame->tf_r0;
-
- DFC_DISASSEMBLE(fault_pc);
-
- /* This is for late abort only */
-
- if ((fault_instruction & (1 << 24)) == 0
- || (fault_instruction & (1 << 21)) != 0) {
- /* postindexed ldr/str with no writeback */
-
- base = (fault_instruction >> 16) & 0x0f;
- if (base == 13 &&
- (frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE)
- return ABORT_FIXUP_FAILED;
- if (base == 15)
- return ABORT_FIXUP_FAILED;
- DFC_PRINTF(("late abt fix: r%d=%08x : ",
- base, registers[base]));
- if ((fault_instruction & (1 << 25)) == 0) {
- /* Immediate offset - easy */
-
- offset = fault_instruction & 0xfff;
- if ((fault_instruction & (1 << 23)))
- offset = -offset;
- registers[base] += offset;
- DFC_PRINTF(("imm=%08x ", offset));
- } else {
- /* offset is a shifted register */
- int shift;
-
- offset = fault_instruction & 0x0f;
- if (offset == base)
- return ABORT_FIXUP_FAILED;
-
- /*
- * Register offset - hard we have to
- * cope with shifts !
- */
- offset = registers[offset];
-
- if ((fault_instruction & (1 << 4)) == 0)
- /* shift with amount */
- shift = (fault_instruction >> 7) & 0x1f;
- else {
- /* shift with register */
- if ((fault_instruction & (1 << 7)) != 0)
- /* undefined for now so bail out */
- return ABORT_FIXUP_FAILED;
- shift = ((fault_instruction >> 8) & 0xf);
- if (base == shift)
- return ABORT_FIXUP_FAILED;
- DFC_PRINTF(("shift reg=%d ", shift));
- shift = registers[shift];
- }
- DFC_PRINTF(("shift=%08x ", shift));
- switch (((fault_instruction >> 5) & 0x3)) {
- case 0 : /* Logical left */
- offset = (int)(((u_int)offset) << shift);
- break;
- case 1 : /* Logical Right */
- if (shift == 0) shift = 32;
- offset = (int)(((u_int)offset) >> shift);
- break;
- case 2 : /* Arithmetic Right */
- if (shift == 0) shift = 32;
- offset = (int)(((int)offset) >> shift);
- break;
- case 3 : /* Rotate right (rol or rxx) */
- return ABORT_FIXUP_FAILED;
- break;
- }
-
- DFC_PRINTF(("abt: fixed LDR/STR with "
- "register offset\n"));
- if ((fault_instruction & (1 << 23)))
- offset = -offset;
- DFC_PRINTF(("offset=%08x ", offset));
- registers[base] += offset;
- }
- DFC_PRINTF(("r%d=%08x\n", base, registers[base]));
- }
- }
-
- if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
-
- /* Ok an abort in SVC mode */
-
- /*
- * Copy the SVC r14 into the usr r14 - The usr r14 is garbage
- * as the fault happened in svc mode but we need it in the
- * usr slot so we can treat the registers as an array of ints
- * during fixing.
- * NOTE: This PC is in the position but writeback is not
- * allowed on r15.
- * Doing it like this is more efficient than trapping this
- * case in all possible locations in the prior fixup code.
- */
-
- frame->tf_svc_lr = frame->tf_usr_lr;
- frame->tf_usr_lr = saved_lr;
-
- /*
- * Note the trapframe does not have the SVC r13 so a fault
- * from an instruction with writeback to r13 in SVC mode is
- * not allowed. This should not happen as the kstack is
- * always valid.
- */
- }
-
- /*
- * Now let the early-abort fixup routine have a go, in case it
- * was an LDM, STM, LDC or STC that faulted.
- */
-
- return early_abort_fixup(arg);
-}
-#endif /* CPU_ARM7TDMI */
-
-/*
- * CPU Setup code
- */
-
-#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined (CPU_ARM9) || \
+#if defined (CPU_ARM9) || \
defined(CPU_ARM9E) || \
- defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
@@ -2030,148 +1267,7 @@ parse_cpu_options(args, optlist, cpuctrl
}
return(cpuctrl);
}
-#endif /* CPU_ARM7TDMI || CPU_ARM8 || CPU_SA110 || XSCALE*/
-
-#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8)
-struct cpu_option arm678_options[] = {
-#ifdef COMPAT_12
- { "nocache", IGN, BIC, CPU_CONTROL_IDC_ENABLE },
- { "nowritebuf", IGN, BIC, CPU_CONTROL_WBUF_ENABLE },
-#endif /* COMPAT_12 */
- { "cpu.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
- { "cpu.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
- { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
- { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
- { NULL, IGN, IGN, 0 }
-};
-
-#endif /* CPU_ARM6 || CPU_ARM7 || CPU_ARM7TDMI || CPU_ARM8 */
-
-#ifdef CPU_ARM7TDMI
-struct cpu_option arm7tdmi_options[] = {
- { "arm7.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
- { "arm7.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
- { "arm7.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
- { "arm7.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
-#ifdef COMPAT_12
- { "fpaclk2", BIC, OR, CPU_CONTROL_CPCLK },
-#endif /* COMPAT_12 */
- { "arm700.fpaclk", BIC, OR, CPU_CONTROL_CPCLK },
- { NULL, IGN, IGN, 0 }
-};
-
-void
-arm7tdmi_setup(args)
- char *args;
-{
- int cpuctrl;
-
- cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
- | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
- | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE;
-
- cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl);
- cpuctrl = parse_cpu_options(args, arm7tdmi_options, cpuctrl);
-
-#ifdef __ARMEB__
- cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
-
- /* Clear out the cache */
- cpu_idcache_wbinv_all();
-
- /* Set the control register */
- ctrl = cpuctrl;
- cpu_control(0xffffffff, cpuctrl);
-}
-#endif /* CPU_ARM7TDMI */
-
-#ifdef CPU_ARM8
-struct cpu_option arm8_options[] = {
- { "arm8.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
- { "arm8.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
- { "arm8.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
- { "arm8.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
-#ifdef COMPAT_12
- { "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
-#endif /* COMPAT_12 */
- { "cpu.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
- { "arm8.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
- { NULL, IGN, IGN, 0 }
-};
-
-void
-arm8_setup(args)
- char *args;
-{
- int integer;
- int cpuctrl, cpuctrlmask;
- int clocktest;
- int setclock = 0;
-
- cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
- | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
- | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE;
- cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
- | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
- | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
- | CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_ROM_ENABLE
- | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE;
-
-#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
- cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
-#endif
-
- cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl);
- cpuctrl = parse_cpu_options(args, arm8_options, cpuctrl);
-
-#ifdef __ARMEB__
- cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
-
- /* Get clock configuration */
- clocktest = arm8_clock_config(0, 0) & 0x0f;
-
- /* Special ARM8 clock and test configuration */
- if (get_bootconf_option(args, "arm8.clock.reset", BOOTOPT_TYPE_BOOLEAN, &integer)) {
- clocktest = 0;
- setclock = 1;
- }
- if (get_bootconf_option(args, "arm8.clock.dynamic", BOOTOPT_TYPE_BOOLEAN, &integer)) {
- if (integer)
- clocktest |= 0x01;
- else
- clocktest &= ~(0x01);
- setclock = 1;
- }
- if (get_bootconf_option(args, "arm8.clock.sync", BOOTOPT_TYPE_BOOLEAN, &integer)) {
- if (integer)
- clocktest |= 0x02;
- else
- clocktest &= ~(0x02);
- setclock = 1;
- }
- if (get_bootconf_option(args, "arm8.clock.fast", BOOTOPT_TYPE_BININT, &integer)) {
- clocktest = (clocktest & ~0xc0) | (integer & 3) << 2;
- setclock = 1;
- }
- if (get_bootconf_option(args, "arm8.test", BOOTOPT_TYPE_BININT, &integer)) {
- clocktest |= (integer & 7) << 5;
- setclock = 1;
- }
-
- /* Clear out the cache */
- cpu_idcache_wbinv_all();
-
- /* Set the control register */
- ctrl = cpuctrl;
- cpu_control(0xffffffff, cpuctrl);
-
- /* Set the clock/test register */
- if (setclock)
- arm8_clock_config(0x7f, clocktest);
-}
-#endif /* CPU_ARM8 */
+#endif /* CPU_ARM9 || XSCALE*/
#ifdef CPU_ARM9
struct cpu_option arm9_options[] = {
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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