svn commit: r260207 - head/sys/net
George V. Neville-Neil
gnn at FreeBSD.org
Thu Jan 2 21:30:59 UTC 2014
Author: gnn
Date: Thu Jan 2 21:30:59 2014
New Revision: 260207
URL: http://svnweb.freebsd.org/changeset/base/260207
Log:
Convert #defines to enums so that the values are visible in the debugger.
Requested by: gibbs
MFC after: 2 weeks
Modified:
head/sys/net/sff8472.h
Modified: head/sys/net/sff8472.h
==============================================================================
--- head/sys/net/sff8472.h Thu Jan 2 21:26:59 2014 (r260206)
+++ head/sys/net/sff8472.h Thu Jan 2 21:30:59 2014 (r260207)
@@ -62,104 +62,107 @@
/* Table 3.1 Two-wire interface ID: Data Fields */
-#define SFF_8472_BASE 0xa0 /* Base address for all our queries. */
-#define SFF_8472_ID 0 /* Transceiver Type (Table 3.2) */
-#define SFF_8472_EXT_ID 1 /* Extended transceiver type (Table 3.3) */
-#define SFF_8472_CONNECTOR 2 /* Connector type (Table 3.4) */
-#define SFF_8472_TRANS_START 3 /* Elec or Optical Compatibility
+enum {
+ SFF_8472_BASE = 0xa0, /* Base address for all our queries. */
+ SFF_8472_ID = 0, /* Transceiver Type (Table 3.2) */
+ SFF_8472_EXT_ID = 1, /* Extended transceiver type (Table 3.3) */
+ SFF_8472_CONNECTOR = 2, /* Connector type (Table 3.4) */
+ SFF_8472_TRANS_START = 3, /* Elec or Optical Compatibility
* (Table 3.5) */
-#define SFF_8472_TRANS_END 10
-#define SFF_8472_ENCODING 11 /* Encoding Code for high speed
- * serial encoding algorithm (see
- * Table 3.6) */
-#define SFF_8472_BITRATE 12 /* Nominal signaling rate, units
- * of 100MBd. (see details for
- * rates > 25.0Gb/s) */
-#define SFF_8472_RATEID 13 /* Type of rate select
- * functionality (see Table
- * 3.6a) */
-#define SFF_8472_LEN_SMF_KM 14 /* Link length supported for single
+ SFF_8472_TRANS_END = 10,
+ SFF_8472_ENCODING = 11, /* Encoding Code for high speed
+ * serial encoding algorithm (see
+ * Table 3.6) */
+ SFF_8472_BITRATE = 12, /* Nominal signaling rate, units
+ * of 100MBd. (see details for
+ * rates > 25.0Gb/s) */
+ SFF_8472_RATEID = 13, /* Type of rate select
+ * functionality (see Table
+ * 3.6a) */
+ SFF_8472_LEN_SMF_KM = 14, /* Link length supported for single
* mode fiber, units of km */
-#define SFF_8472_LEN_SMF 15 /* Link length supported for single
+ SFF_8472_LEN_SMF = 15, /* Link length supported for single
* mode fiber, units of 100 m */
-#define SFF_8472_LEN_50UM 16 /* Link length supported for 50 um
+ SFF_8472_LEN_50UM = 16, /* Link length supported for 50 um
* OM2 fiber, units of 10 m */
-#define SFF_8472_LEN_625UM 17 /* Link length supported for 62.5
+ SFF_8472_LEN_625UM = 17, /* Link length supported for 62.5
* um OM1 fiber, units of 10 m */
-#define SFF_8472_LEN_OM4 18 /* Link length supported for 50um
+ SFF_8472_LEN_OM4 = 18, /* Link length supported for 50um
* OM4 fiber, units of 10m.
* Alternatively copper or direct
* attach cable, units of m */
-#define SFF_8472_LEN_OM3 19 /* Link length supported for 50 um OM3 fiber, units of 10 m */
-#define SFF_8472_VENDOR_START 20 /* Vendor name [Address A0h, Bytes
+ SFF_8472_LEN_OM3 = 19, /* Link length supported for 50 um OM3 fiber, units of 10 m */
+ SFF_8472_VENDOR_START = 20, /* Vendor name [Address A0h, Bytes
* 20-35] */
-#define SFF_8472_VENDOR_END 35
-#define SFF_8472_TRANS 36 /* Transceiver Code for electronic
+ SFF_8472_VENDOR_END = 35,
+ SFF_8472_TRANS = 36, /* Transceiver Code for electronic
* or optical compatibility (see
* Table 3.5) */
-#define SFF_8472_VENDOR_OUI_START 37 /* Vendor OUI SFP vendor IEEE
+ SFF_8472_VENDOR_OUI_START = 37, /* Vendor OUI SFP vendor IEEE
* company ID */
-#define SFF_8472_VENDOR_OUI_END 39
-#define SFF_8472_PN_START 40 /* Vendor PN */
-#define SFF_8472_PN_END 55
-#define SFF_8472_REV_START 56 /* Vendor Revision */
-#define SFF_8472_REV_END 59
-#define SFF_8472_WAVELEN_START 60 /* Wavelength Laser wavelength
+ SFF_8472_VENDOR_OUI_END = 39,
+ SFF_8472_PN_START = 40, /* Vendor PN */
+ SFF_8472_PN_END = 55,
+ SFF_8472_REV_START = 56, /* Vendor Revision */
+ SFF_8472_REV_END = 59,
+ SFF_8472_WAVELEN_START = 60, /* Wavelength Laser wavelength
* (Passive/Active Cable
* Specification Compliance) */
-#define SFF_8472_WAVELEN_END 61
-#define SFF_8472_CC_BASE 63 /* CC_BASE Check code for Base ID
+ SFF_8472_WAVELEN_END = 61,
+ SFF_8472_CC_BASE = 63, /* CC_BASE Check code for Base ID
* Fields (addresses 0 to 62) */
/*
* Extension Fields (optional) check the options before reading other
* addresses.
*/
-#define SFF_8472_OPTIONS_MSB 64 /* Options Indicates which optional
+ SFF_8472_OPTIONS_MSB = 64, /* Options Indicates which optional
* transceiver signals are
* implemented */
-#define SFF_8472_OPTIONS_LSB 65 /* (see Table 3.7) */
-#define SFF_8472_BR_MAX 66 /* BR max Upper bit rate margin,
+ SFF_8472_OPTIONS_LSB = 65, /* (see Table 3.7) */
+ SFF_8472_BR_MAX = 66, /* BR max Upper bit rate margin,
* units of % (see details for
* rates > 25.0Gb/s) */
-#define SFF_8472_BR_MIN 67 /* Lower bit rate margin, units of
+ SFF_8472_BR_MIN = 67, /* Lower bit rate margin, units of
* % (see details for rates >
* 25.0Gb/s) */
-#define SFF_8472_SN_START 68 /* Vendor SN [Address A0h, Bytes 68-83] */
-#define SFF_8472_SN_END 83
-#define SFF_8472_DATE_START 84 /* Date code Vendor’s manufacturing
+ SFF_8472_SN_START = 68, /* Vendor SN [Address A0h, Bytes 68-83] */
+ SFF_8472_SN_END = 83,
+ SFF_8472_DATE_START = 84, /* Date code Vendor’s manufacturing
* date code (see Table 3.8) */
-#define SFF_8472_DATE_END 91
-#define SFF_8472_DIAG_TYPE 92 /* Diagnostic Monitoring Type
+ SFF_8472_DATE_END = 91,
+ SFF_8472_DIAG_TYPE = 92, /* Diagnostic Monitoring Type
* Indicates which type of
* diagnostic monitoring is
* implemented (if any) in the
* transceiver (see Table 3.9)
*/
-#define SFF_8472_DIAG_IMPL (1 << 6) /* Required to be 1 */
-#define SFF_8472_DIAG_INTERNAL (1 << 5) /* Internal measurements. */
-#define SFF_8472_DIAG_EXTERNAL (1 << 4) /* External measurements. */
-#define SFF_8472_DIAG_POWER (1 << 3) /* Power measurement type */
-#define SFF_8472_DIAG_ADDR_CHG (1 << 2) /* Address change required.
- * See SFF-8472 doc. */
-#define SFF_8472_ENHANCED 93 /* Enhanced Options Indicates which
+ SFF_8472_ENHANCED = 93, /* Enhanced Options Indicates which
* optional enhanced features are
* implemented (if any) in the
* transceiver (see Table 3.10) */
-#define SFF_8472_COMPLIANCE 94 /* SFF-8472 Compliance Indicates
+ SFF_8472_COMPLIANCE = 94, /* SFF-8472 Compliance Indicates
* which revision of SFF-8472 the
* transceiver complies with. (see
* Table 3.12)*/
-#define SFF_8472_CC_EXT 95 /* Check code for the Extended ID
+ SFF_8472_CC_EXT = 95, /* Check code for the Extended ID
* Fields (addresses 64 to 94)
*/
-#define SFF_8472_VENDOR_RSRVD_START 96
-#define SFF_8472_VENDOR_RSRVD_END 127
+ SFF_8472_VENDOR_RSRVD_START = 96,
+ SFF_8472_VENDOR_RSRVD_END = 127,
-#define SFF_8472_RESERVED_START 128
-#define SFF_8472_RESERVED_END 255
+ SFF_8472_RESERVED_START = 128,
+ SFF_8472_RESERVED_END = 255
+};
+
+#define SFF_8472_DIAG_IMPL (1 << 6) /* Required to be 1 */
+#define SFF_8472_DIAG_INTERNAL (1 << 5) /* Internal measurements. */
+#define SFF_8472_DIAG_EXTERNAL (1 << 4) /* External measurements. */
+#define SFF_8472_DIAG_POWER (1 << 3) /* Power measurement type */
+#define SFF_8472_DIAG_ADDR_CHG (1 << 2) /* Address change required.
+ * See SFF-8472 doc. */
/*
* Diagnostics are available at the two wire address 0xa2. All
@@ -167,77 +170,78 @@
* see which, if any are supported.
*/
-#define SFF_8472_DIAG 0xa2 /* Base address for diagnostics. */
+enum {SFF_8472_DIAG = 0xa2}; /* Base address for diagnostics. */
/*
* Table 3.15 Alarm and Warning Thresholds All values are 2 bytes
* and MUST be read in a single read operation starting at the MSB
*/
-#define SFF_8472_TEMP_HIGH_ALM 0 /* Temp High Alarm */
-#define SFF_8472_TEMP_LOW_ALM 2 /* Temp Low Alarm */
-#define SFF_8472_TEMP_HIGH_WARN 4 /* Temp High Warning */
-#define SFF_8472_TEMP_LOW_WARN 6 /* Temp Low Warning */
-#define SFF_8472_VOLTAGE_HIGH_ALM 8 /* Voltage High Alarm */
-#define SFF_8472_VOLTAGE_LOW_ALM 10 /* Voltage Low Alarm */
-#define SFF_8472_VOLTAGE_HIGH_WARN 12 /* Voltage High Warning */
-#define SFF_8472_VOLTAGE_LOW_WARN 14 /* Voltage Low Warning */
-#define SFF_8472_BIAS_HIGH_ALM 16 /* Bias High Alarm */
-#define SFF_8472_BIAS_LOW_ALM 18 /* Bias Low Alarm */
-#define SFF_8472_BIAS_HIGH_WARN 20 /* Bias High Warning */
-#define SFF_8472_BIAS_LOW_WARN 22 /* Bias Low Warning */
-#define SFF_8472_TX_POWER_HIGH_ALM 24 /* TX Power High Alarm */
-#define SFF_8472_TX_POWER_LOW_ALM 26 /* TX Power Low Alarm */
-#define SFF_8472_TX_POWER_HIGH_WARN 28 /* TX Power High Warning */
-#define SFF_8472_TX_POWER_LOW_WARN 30 /* TX Power Low Warning */
-#define SFF_8472_RX_POWER_HIGH_ALM 32 /* RX Power High Alarm */
-#define SFF_8472_RX_POWER_LOW_ALM 34 /* RX Power Low Alarm */
-#define SFF_8472_RX_POWER_HIGH_WARN 36 /* RX Power High Warning */
-#define SFF_8472_RX_POWER_LOW_WARN 38 /* RX Power Low Warning */
+enum {
+ SFF_8472_TEMP_HIGH_ALM = 0, /* Temp High Alarm */
+ SFF_8472_TEMP_LOW_ALM = 2, /* Temp Low Alarm */
+ SFF_8472_TEMP_HIGH_WARN = 4, /* Temp High Warning */
+ SFF_8472_TEMP_LOW_WARN = 6, /* Temp Low Warning */
+ SFF_8472_VOLTAGE_HIGH_ALM = 8, /* Voltage High Alarm */
+ SFF_8472_VOLTAGE_LOW_ALM = 10, /* Voltage Low Alarm */
+ SFF_8472_VOLTAGE_HIGH_WARN = 12, /* Voltage High Warning */
+ SFF_8472_VOLTAGE_LOW_WARN = 14, /* Voltage Low Warning */
+ SFF_8472_BIAS_HIGH_ALM = 16, /* Bias High Alarm */
+ SFF_8472_BIAS_LOW_ALM = 18, /* Bias Low Alarm */
+ SFF_8472_BIAS_HIGH_WARN = 20, /* Bias High Warning */
+ SFF_8472_BIAS_LOW_WARN = 22, /* Bias Low Warning */
+ SFF_8472_TX_POWER_HIGH_ALM = 24, /* TX Power High Alarm */
+ SFF_8472_TX_POWER_LOW_ALM = 26, /* TX Power Low Alarm */
+ SFF_8472_TX_POWER_HIGH_WARN = 28, /* TX Power High Warning */
+ SFF_8472_TX_POWER_LOW_WARN = 30, /* TX Power Low Warning */
+ SFF_8472_RX_POWER_HIGH_ALM = 32, /* RX Power High Alarm */
+ SFF_8472_RX_POWER_LOW_ALM = 34, /* RX Power Low Alarm */
+ SFF_8472_RX_POWER_HIGH_WARN = 36, /* RX Power High Warning */
+ SFF_8472_RX_POWER_LOW_WARN = 38, /* RX Power Low Warning */
-#define SFF_8472_RX_POWER4 56 /* Rx_PWR(4) Single precision
+ SFF_8472_RX_POWER4 = 56, /* Rx_PWR(4) Single precision
* floating point calibration data
* - Rx optical power. Bit 7 of
* byte 56 is MSB. Bit 0 of byte
* 59 is LSB. Rx_PWR(4) should be
* set to zero for “internally
* calibrated” devices. */
-#define SFF_8472_RX_POWER3 60 /* Rx_PWR(3) Single precision
+ SFF_8472_RX_POWER3 = 60, /* Rx_PWR(3) Single precision
* floating point calibration data
* - Rx optical power. Bit 7 of
* byte 60 is MSB. Bit 0 of byte 63
* is LSB. Rx_PWR(3) should be set
* to zero for “internally
* calibrated” devices.*/
-#define SFF_8472_RX_POWER2 64 /* Rx_PWR(2) Single precision
+ SFF_8472_RX_POWER2 = 64, /* Rx_PWR(2) Single precision
* floating point calibration data,
* Rx optical power. Bit 7 of byte
* 64 is MSB, bit 0 of byte 67 is
* LSB. Rx_PWR(2) should be set to
* zero for “internally calibrated”
* devices. */
-#define SFF_8472_RX_POWER1 68 /* Rx_PWR(1) Single precision
+ SFF_8472_RX_POWER1 = 68, /* Rx_PWR(1) Single precision
* floating point calibration data,
* Rx optical power. Bit 7 of byte
* 68 is MSB, bit 0 of byte 71 is
* LSB. Rx_PWR(1) should be set to
* 1 for “internally calibrated”
* devices. */
-#define SFF_8472_RX_POWER0 72 /* Rx_PWR(0) Single precision
+ SFF_8472_RX_POWER0 = 72, /* Rx_PWR(0) Single precision
* floating point calibration data,
* Rx optical power. Bit 7 of byte
* 72 is MSB, bit 0 of byte 75 is
* LSB. Rx_PWR(0) should be set to
* zero for “internally calibrated”
* devices. */
-#define SFF_8472_TX_I_SLOPE 76 /* Tx_I(Slope) Fixed decimal
+ SFF_8472_TX_I_SLOPE = 76, /* Tx_I(Slope) Fixed decimal
* (unsigned) calibration data,
* laser bias current. Bit 7 of
* byte 76 is MSB, bit 0 of byte 77
* is LSB. Tx_I(Slope) should be
* set to 1 for “internally
* calibrated” devices. */
-#define SFF_8472_TX_I_OFFSET 78 /* Tx_I(Offset) Fixed decimal
+ SFF_8472_TX_I_OFFSET = 78, /* Tx_I(Offset) Fixed decimal
* (signed two’s complement)
* calibration data, laser bias
* current. Bit 7 of byte 78 is
@@ -245,7 +249,7 @@
* LSB. Tx_I(Offset) should be set
* to zero for “internally
* calibrated” devices. */
-#define SFF_8472_TX_POWER_SLOPE 80 /* Tx_PWR(Slope) Fixed decimal
+ SFF_8472_TX_POWER_SLOPE = 80, /* Tx_PWR(Slope) Fixed decimal
* (unsigned) calibration data,
* transmitter coupled output
* power. Bit 7 of byte 80 is MSB,
@@ -253,22 +257,22 @@
* Tx_PWR(Slope) should be set to 1
* for “internally calibrated”
* devices. */
-#define SFF_8472_TX_POWER_OFFSET 82 /* Tx_PWR(Offset) Fixed decimal
- * (signed two’s complement)
- * calibration data, transmitter
- * coupled output power. Bit 7 of
- * byte 82 is MSB, bit 0 of byte 83
- * is LSB. Tx_PWR(Offset) should be
- * set to zero for “internally
- * calibrated” devices. */
-#define SFF_8472_T_SLOPE 84 /* T (Slope) Fixed decimal
+ SFF_8472_TX_POWER_OFFSET = 82, /* Tx_PWR(Offset) Fixed decimal
+ * (signed two’s complement)
+ * calibration data, transmitter
+ * coupled output power. Bit 7 of
+ * byte 82 is MSB, bit 0 of byte 83
+ * is LSB. Tx_PWR(Offset) should be
+ * set to zero for “internally
+ * calibrated” devices. */
+ SFF_8472_T_SLOPE = 84, /* T (Slope) Fixed decimal
* (unsigned) calibration data,
* internal module temperature. Bit
* 7 of byte 84 is MSB, bit 0 of
* byte 85 is LSB. T(Slope) should
* be set to 1 for “internally
* calibrated” devices. */
-#define SFF_8472_T_OFFSET 86 /* T (Offset) Fixed decimal (signed
+ SFF_8472_T_OFFSET = 86, /* T (Offset) Fixed decimal (signed
* two’s complement) calibration
* data, internal module
* temperature. Bit 7 of byte 86 is
@@ -276,7 +280,7 @@
* T(Offset) should be set to zero
* for “internally calibrated”
* devices. */
-#define SFF_8472_V_SLOPE 88 /* V (Slope) Fixed decimal
+ SFF_8472_V_SLOPE = 88, /* V (Slope) Fixed decimal
* (unsigned) calibration data,
* internal module supply
* voltage. Bit 7 of byte 88 is
@@ -284,7 +288,7 @@
* LSB. V(Slope) should be set to 1
* for “internally calibrated”
* devices. */
-#define SFF_8472_V_OFFSET 90 /* V (Offset) Fixed decimal (signed
+ SFF_8472_V_OFFSET = 90, /* V (Offset) Fixed decimal (signed
* two’s complement) calibration
* data, internal module supply
* voltage. Bit 7 of byte 90 is
@@ -292,21 +296,21 @@
* LSB. V(Offset) should be set to
* zero for “internally calibrated”
* devices. */
-#define SFF_8472_CHECKSUM 95 /* Checksum Byte 95 contains the
+ SFF_8472_CHECKSUM = 95, /* Checksum Byte 95 contains the
* low order 8 bits of the sum of
* bytes 0 – 94. */
- /* Internal measurements. */
+ /* Internal measurements. */
-#define SFF_8472_TEMP 96 /* Internally measured module temperature. */
-#define SFF_8472_VCC 98 /* Internally measured supply
+ SFF_8472_TEMP = 96, /* Internally measured module temperature. */
+ SFF_8472_VCC = 98, /* Internally measured supply
* voltage in transceiver.
*/
-#define SFF_8472_TX_BIAS 100 /* Internally measured TX Bias Current. */
-#define SFF_8472_TX_POWER 102 /* Measured TX output power. */
-#define SFF_8472_RX_POWER 104 /* Measured RX input power. */
-
-#define SFF_8472_STATUS 110 /* See below */
+ SFF_8472_TX_BIAS = 100, /* Internally measured TX Bias Current. */
+ SFF_8472_TX_POWER = 102, /* Measured TX output power. */
+ SFF_8472_RX_POWER = 104, /* Measured RX input power. */
+ SFF_8472_STATUS = 110 /* See below */
+};
/* Status Bits Described */
/*
@@ -372,20 +376,22 @@
#define SFF_8472_STATUS_DATA_READY (1 << 0)
/* Table 3.2 Identifier values */
-#define SFF_8472_ID_UNKNOWN 0x0 /* Unknown or unspecified */
-#define SFF_8472_ID_GBIC 0x1 /* GBIC */
-#define SFF_8472_ID_SFF 0x2 /* Module soldered to motherboard (ex: SFF)*/
-#define SFF_8472_ID_SFP 0x3 /* SFP or SFP “Plus” */
-#define SFF_8472_ID_XBI 0x4 /* Reserved for “300 pin XBI” devices */
-#define SFF_8472_ID_XENPAK 0x5 /* Reserved for “Xenpak” devices */
-#define SFF_8472_ID_XFP 0x6 /* Reserved for “XFP” devices */
-#define SFF_8472_ID_XFF 0x7 /* Reserved for “XFF” devices */
-#define SFF_8472_ID_XFPE 0x8 /* Reserved for “XFP-E” devices */
-#define SFF_8472_ID_XPAK 0x9 /* Reserved for “XPak” devices */
-#define SFF_8472_ID_X2 0xA /* Reserved for “X2” devices */
-#define SFF_8472_ID_DWDM_SFP 0xB /* Reserved for “DWDM-SFP” devices */
-#define SFF_8472_ID_QSFP 0xC /* Reserved for “QSFP” devices */
-#define SFF_8472_ID_LAST SFF_8472_ID_QSFP
+enum {
+ SFF_8472_ID_UNKNOWN = 0x0, /* Unknown or unspecified */
+ SFF_8472_ID_GBIC = 0x1, /* GBIC */
+ SFF_8472_ID_SFF = 0x2, /* Module soldered to motherboard (ex: SFF)*/
+ SFF_8472_ID_SFP = 0x3, /* SFP or SFP “Plus” */
+ SFF_8472_ID_XBI = 0x4, /* Reserved for “300 pin XBI” devices */
+ SFF_8472_ID_XENPAK = 0x5, /* Reserved for “Xenpak” devices */
+ SFF_8472_ID_XFP = 0x6, /* Reserved for “XFP” devices */
+ SFF_8472_ID_XFF = 0x7, /* Reserved for “XFF” devices */
+ SFF_8472_ID_XFPE = 0x8, /* Reserved for “XFP-E” devices */
+ SFF_8472_ID_XPAK = 0x9, /* Reserved for “XPak” devices */
+ SFF_8472_ID_X2 = 0xA, /* Reserved for “X2” devices */
+ SFF_8472_ID_DWDM_SFP = 0xB, /* Reserved for “DWDM-SFP” devices */
+ SFF_8472_ID_QSFP = 0xC, /* Reserved for “QSFP” devices */
+ SFF_8472_ID_LAST = SFF_8472_ID_QSFP
+ };
static char *sff_8472_id[SFF_8472_ID_LAST + 1] = {"Unknown",
"GBIC",
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