svn commit: r256707 - in head/sys/arm: arm include

Olivier Houchard cognet at FreeBSD.org
Thu Oct 17 21:06:21 UTC 2013


Author: cognet
Date: Thu Oct 17 21:06:19 2013
New Revision: 256707
URL: http://svnweb.freebsd.org/changeset/base/256707

Log:
  - Switch to use WBWA mappings for page tables on armv6, this is needed for SMP.
  - Fix PTE_SYNC() for PIPT L2 caches, using the virtual address wasn't so useful.
  - Use PTE_SYNC() for >= armv6

Modified:
  head/sys/arm/arm/cpufunc_asm_armv7.S
  head/sys/arm/arm/pmap-v6.c
  head/sys/arm/include/pmap.h

Modified: head/sys/arm/arm/cpufunc_asm_armv7.S
==============================================================================
--- head/sys/arm/arm/cpufunc_asm_armv7.S	Thu Oct 17 20:23:28 2013	(r256706)
+++ head/sys/arm/arm/cpufunc_asm_armv7.S	Thu Oct 17 21:06:19 2013	(r256707)
@@ -57,9 +57,9 @@ __FBSDID("$FreeBSD$");
 #define PT_OUTER_WBWA	(1 << 3)
 	
 #ifdef SMP
-#define PT_ATTR	(PT_S|PT_INNER_WT|PT_OUTER_WT|PT_NOS)
+#define PT_ATTR	(PT_S|PT_INNER_WBWA|PT_OUTER_WBWA|PT_NOS)
 #else
-#define PT_ATTR	(PT_INNER_WT|PT_OUTER_WT)
+#define PT_ATTR	(PT_INNER_WBWA|PT_OUTER_WBWA)
 #endif
 
 ENTRY(armv7_setttb)
@@ -98,7 +98,7 @@ ENTRY(armv7_tlb_flushID_SE)
 	ldr	r1, .Lpage_mask
 	bic	r0, r0, r1
 #ifdef SMP
-	mcr	p15, 0, r0, c8, c3, 1	/* flush D tlb single entry Inner Shareable*/
+	mcr	p15, 0, r0, c8, c3, 3	/* flush D tlb single entry Inner Shareable*/
 	mcr	p15, 0, r0, c7, c1, 6	/* flush BTB Inner Shareable */
 #else
 	mcr	p15, 0, r0, c8, c7, 1	/* flush D tlb single entry */

Modified: head/sys/arm/arm/pmap-v6.c
==============================================================================
--- head/sys/arm/arm/pmap-v6.c	Thu Oct 17 20:23:28 2013	(r256706)
+++ head/sys/arm/arm/pmap-v6.c	Thu Oct 17 21:06:19 2013	(r256707)
@@ -2441,6 +2441,8 @@ vm_paddr_t
 pmap_kextract(vm_offset_t va)
 {
 
+	if (kernel_vm_end == 0)
+		return (0);
 	return (pmap_extract_locked(kernel_pmap, va));
 }
 
@@ -3295,9 +3297,11 @@ pmap_extract(pmap_t pmap, vm_offset_t va
 {
 	vm_paddr_t pa;
 
-	PMAP_LOCK(pmap);
+	if (kernel_vm_end != 0)
+		PMAP_LOCK(pmap);
 	pa = pmap_extract_locked(pmap, va);
-	PMAP_UNLOCK(pmap);
+	if (kernel_vm_end != 0)
+		PMAP_UNLOCK(pmap);
 	return (pa);
 }
 
@@ -3310,7 +3314,7 @@ pmap_extract_locked(pmap_t pmap, vm_offs
 	vm_paddr_t pa;
 	u_int l1idx;
 
-	if (pmap != kernel_pmap)
+	if (kernel_vm_end != 0 && pmap != kernel_pmap)
 		PMAP_ASSERT_LOCKED(pmap);
 	l1idx = L1_IDX(va);
 	l1pd = pmap->pm_l1->l1_kva[l1idx];

Modified: head/sys/arm/include/pmap.h
==============================================================================
--- head/sys/arm/include/pmap.h	Thu Oct 17 20:23:28 2013	(r256706)
+++ head/sys/arm/include/pmap.h	Thu Oct 17 21:06:19 2013	(r256707)
@@ -63,7 +63,7 @@
 #endif
 #define PTE_CACHE	6
 #define PTE_DEVICE	2
-#define PTE_PAGETABLE	4
+#define PTE_PAGETABLE	6
 #else
 #define PTE_NOCACHE	1
 #define PTE_CACHE	2
@@ -489,7 +489,7 @@ extern int pmap_needs_pte_sync;
 #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1)
 #define	PMAP_NEEDS_PTE_SYNC	1
 #define	PMAP_INCLUDE_PTE_SYNC
-#elif defined(CPU_XSCALE_81342)
+#elif defined(CPU_XSCALE_81342) || defined(ARM_ARCH_7) || defined(ARM_ARCH_7A)
 #define PMAP_NEEDS_PTE_SYNC	1
 #define PMAP_INCLUDE_PTE_SYNC
 #elif (ARM_MMU_SA1 == 0)
@@ -559,11 +559,18 @@ extern int pmap_needs_pte_sync;
 #define	PMAP_INCLUDE_PTE_SYNC
 #endif
 
+#ifdef ARM_L2_PIPT
+#define _sync_l2(pte, size) 	cpu_l2cache_wb_range(vtophys(pte), size)
+#else
+#define _sync_l2(pte, size) 	cpu_l2_cache_wb_range(pte, size)
+#endif
+
 #define	PTE_SYNC(pte)							\
 do {									\
 	if (PMAP_NEEDS_PTE_SYNC) {					\
 		cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
-		cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
+		cpu_drain_writebuf();					\
+		_sync_l2((vm_offset_t)(pte), sizeof(pt_entry_t));\
 	} else								\
 		cpu_drain_writebuf();					\
 } while (/*CONSTCOND*/0)
@@ -573,7 +580,8 @@ do {									\
 	if (PMAP_NEEDS_PTE_SYNC) {					\
 		cpu_dcache_wb_range((vm_offset_t)(pte),			\
 		    (cnt) << 2); /* * sizeof(pt_entry_t) */		\
-		cpu_l2cache_wb_range((vm_offset_t)(pte), 		\
+		cpu_drain_writebuf();					\
+		_sync_l2((vm_offset_t)(pte),		 		\
 		    (cnt) << 2); /* * sizeof(pt_entry_t) */		\
 	} else								\
 		cpu_drain_writebuf();					\


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