svn commit: r252032 - head/sys/amd64/include

[Gleb Smirnoff]

On Mon, Jun 24, 2013 at 11:16:33PM +1000, Bruce Evans wrote:
B> > K> This is quite interesting idea, but I still did not decided if it
B> > K> acceptable.  The issue is that we could add the carry to the other
B> > K> processor counter, if the preemption kicks in at right time between
B> > K> two instructions.  I did not found any argument why would it be
B> > K> wrong, the races for fetch operation seems to be the same with either
B> > K> local update method.
B> >
B> > This would be wrong since update isn't locked. Thus, if we are put on
B> > other CPU between two instructions, and in second instruction updating
B> > another CPU counter simultaneously with the original CPU we were on,
B> > then we are losing an update.
B> 
B> Hmm, this is subtle.  The update is never lost, but is applied to
B> different counter, non-atomically at a later time.  Non-atomicity
B> only matters when there is a carry since the counter only goes
B> transiently backards in this case.  For example: initial state:
B> 
B>      CPU1 counter:  00000000 ffffffff
B>      CPU2 counter:  00000000 fffffffe
B> 
B> Start adding 1 to the first counter, doing it non-atomically by
B> incrementing the low word first.
B> 
B>      CPU1 counter:  00000000 00000000  (carry in CPU1 eflags)
B>      CPU2 counter:  00000000 fffffffe
B> 
B> Get preempted at this point:
B> 
B>      CPU1 counter:  00000000 00000000
B>      CPU2 counter:  00000000 fffffffe  (carry in CPU2 eflags)

Nope, the non-atomicity isn't specific to the case when we carry
bit from least significant part to most one.

The non-atomicity is much simplier: two CPUs write to same memory address
w/o using lock prefix.

Thus, any update mechanism that first calculates absolute per-CPU address,
then writes to it w/o lock, requires critical section. Because preemption
between calculation and write, and later execution on other CPU leads
to two CPUs writing to same address.

-- 
Totus tuus, Glebius.